Alan Modra [Fri, 23 Aug 2002 08:26:13 +0000 (08:26 +0000)]
* elf32-sh.c (elf_sh_plt0_entry_be, elf_sh_plt0_entry_le): Copy
contents of .got.plt[2] to tr0, not address of .got.plt.
(sh_elf_finish_dynamic_symbol): Do not apply GOT_BIAS when
patching absolute plt entry. For shmedia plt entry, set bottom bit
of branch to plt0 as this is a branch to an shmedia instruction.
* elf64-sh64.c (elf_sh64_plt0_entry_be, elf_sh64_plt0_entry_le):
Copy contents of .got.plt[2] to tr0, not address of .got.plt.
(elf_sh64_plt_entry_be, elf_sh64_plt_entry_le): Use ptrel to
branch to plt0.
(sh64_elf64_finish_dynamic_symbol): Do not apply GOT_BIAS when
patching absolute plt entry. For shmedia plt entry, branch to
plt0 is now ptrel, so use relative offset. Set bottom bit of
branch target as it is a branch to an shmedia instruction.
Alan Modra [Fri, 23 Aug 2002 08:14:06 +0000 (08:14 +0000)]
* ld-sh/sh64/rd-sh64.exp: New framework file.
* ld-sh/sh64/init-cmpct.d, ld-sh/sh64/init-media.d,
ld-sh/sh64/init64.d, ld-sh/sh64/init.s: New tests for
correct setting of ISA bit for init and fini entry-points.
Alan Modra [Fri, 23 Aug 2002 08:13:12 +0000 (08:13 +0000)]
* elf32-sh.c (sh_elf_finish_dynamic_sections): Set LSB of DT_INIT
value if .init is an SHmedia function. Similarly for DT_FINI.
* elf64-sh64.c (sh64_elf64_finish_dynamic_sections): Likewise.
* rs6000-tdep.c (struct rs6000_framedata): Add saved_ev and
ev_offset fields.
(skip_prologue): Add support for BookE/e500 instructions.
(e500_extract_return_value): New function.
(frame_get_saved_regs): Add support for saving ev registers and
pseudo gpr's.
(e500_store_return_value): New function.
(rs6000_gdbarch_init): Move up default intializations of
deprecated_extract_return_value and store_return_value. Overwrite
init of store_return_value with e500 specific version.
Set extract_return_value for e500.
Jim Blandy [Thu, 22 Aug 2002 05:50:11 +0000 (05:50 +0000)]
* coffread.c (coff_symfile_read): Don't try to read the line
number table from disk if the image file doesn't have a symbol
table; we'll never actually look at the info anyway, and Windows
ships DLL's with bogus file offsets for the line number data.
* config/tc-ppc.c (ppc_cleanup): Do something only if format
is ELF.
(ppc_apuinfo_section_add): Define only if format is ELF.
(md_assemble): Emit APUinfo section only if format is ELF.
Fix formatting.
* mips-tdep.c (MSYMBOL_IS_SPECIAL, MSYMBOL_SIZE): These are only
used locally, so move them from the target machine header to here.
(mips_set_processor_type, mips_register_name, mips32_next_pc,
mips16_next_pc, cached_proc_desc, mips_set_processor_type):
Make static.
* config/mips/tm-mips.h (MSYMBOL_IS_SPECIAL, MSYMBOL_SIZE): Delete.
* ppc-tdep.h (struct gdbarch_tdep): Add ev registers.
* rs6000-tdep.c (rs6000_register_virtual_type): Return 64 bit
vector type for ev registers.
(e500_pseudo_register_read): New function.
(e500_pseudo_register_write): New function.
(e500_dwarf2_reg_to_regnum): New function.
(PPC_UISA_NOFP_SPRS): New macro.
(PPC_EV_REGS): New macro.
(PPC_GPRS_PSEUDO_REGS): New macro.
(registers_e500): New register set for e500.
(variants): Add e500 variant.
(rs6000_gdbarch_init): Move setting of pc, sp, fp regnums to
before setting architectural dependent variations. Initialize ev
registers numbers. Add case for e500 architecture. Set the
number of pseudo registers.
* config/mips/tm-mips.h (STORE_STRUCT_RETURN): Delete.
(EXTRACT_STRUCT_VALUE_ADDRESS): Delete.
* mips-tdep.c (mips_store_struct_return): New function.
(mips_extract_struct_value_address): New function.
(mips_gdbarch_init): Set store_struct_return and
extract_struct_value_address.
* config/mips/tm-mips.h (STORE_STRUCT_RETURN): Delete.
(EXTRACT_STRUCT_VALUE_ADDRESS): Delete.
* mips-tdep.c (mips_store_struct_return): New function.
(mips_extract_struct_value_address): New function.
(mips_gdbarch_init): Set store_struct_return and
extract_struct_value_address.
* dwarf2read.c (dwarf2_build_psymtabs): Check that
dwarf_line_offset is nonzero before creating dwarf_line_buffer.
(read_file_scope): Check that line_header is nonzero before
decoding macro information.
Mark Kettenis [Tue, 20 Aug 2002 17:59:50 +0000 (17:59 +0000)]
* i386-tdep.h (FP_REGNUM_P): Change such that we don't incorrectly
flag the general-purpose registers as floating-point on targets
that don't support the floating-point registers.
* infcmd.c (do_registers_info): Print vector registers in hex
format only.
(print_vector_info): Check that printing registers
makes sense.
(print_float_info): Ditto.
* mips-tdep.c (mips_gdbarch_init): Update.
(mips_o32_extract_return_value): Rewrite.
(mips_o32_store_return_value): Rewrite.
(mips_o32_xfer_return_value): New function.
(mips_xfer_register): Tweak debug print message. Allow for
buf_offset when dumping the value transfered.
[gas/]
* config/tc-mips.c (macro2): Implement rotates by zero using shifts
by zero.
[gas/testsuite]
* gas/mips/rol.s: Add rotate by zero tests.
* gas/mips/rol.d: Update accordingly.
* gas/mips/rol64.d: Expect rotates by zero to use dsrl.
* rs6000-tdep.c (struct reg): Add field to indicate a pseudo
register.
(P): New macro to define a register as a pseudo register.
(R, R4, R8, R16, FR32, R64, R0): Updated.
(struct variant): Add new fields for number of pseudo registers
and number of total registers.
(tot_num_registers): New macro replacing....
(num_registers): ...deleted macro.
(num_registers): New function.
(num_pseudo_registers): New function.
(variants): Update all variants to intialize new fields correctly.
Postpone initialization of number of pseudo regs and real regs.
(init_variants): New function.
(rs6000_gdbarch_init): Initialize variants. Update calculation of
registers offsets.
* valops.c (search_struct_field): Change error message to treat
return value of 0 from value_static_field as meaning that field is
optimized out.
(value_struct_elt_for_reference): Ditto.
* values.c (value_static_field): Treat an unresolved location the
same as a nonexistent symbol. Fix PR gdb/635.
* mips-tdep.c (mips_xfer_register): New function.
(mips_n32n64_extract_return_value): Rewrite.
(mips_gdbarch_init): For N32 and N64, set extract_return_value
instead of deprecated_extract_return_value.
* config/tc-ppc.c (PPC_OPCODE_CLASSIC): Enable this everywhere
PPC_OPCODE_PPC is, except for BookE architectures.
(md_parse_option): Add support for -mspe.
(md_show_usage): Add -mspe.
(md_parse_option): Add support for -me500 and
-me500x2 to generate code for Motorola e500 core complex.
(md_show_usage): Add -me500 and -me500x2.
(PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI,
PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS,
PPC_APUINFO_BRLOCK): New macros.
(ppc_cleanup): New function.
(ppc_apuinfo_section_add): New function.
(APUID): New macro.
(md_assemble): Collect info and write the APUinfo section.
* ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and
`-mefs'. Turn off AltiVec for E500 and efs.
(print_insn_powerpc): Don't print an AltiVec instruction if the
dialect is not efs.
* ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2,
insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions
for extracting pmrn/evld/evstd/etc operands.
(CRB, CRFD, CRFS, DC, RD): New instruction fields.
(CT): Make this equal to RD + 1.
(PMRN): New operand.
(RA): Update.
(EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands.
(WS): Update.
(EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL.
(ISEL, ISEL_MASK): New instruction form and mask for ISEL.
(XISEL, XISEL_MASK): New instruction form and mask for ISEL.
(CTX, CTX_MASK): New instruction form and mask for context cache
instructions.
(UCTX, UCTX_MASK): New instruction form and mask for user context
cache instructions.
(XC, XC_MASK, XUC, XUC_MASK): New instruction forms.
(CLASSIC): New define.
(PPCESPE): New define.
(PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New
defines for integer select, cache control, branch
locking, power management, cache locking and machine check
APU instructions, respectively.
(efsabs, efsnabs, efsneg, efsadd, efssub, efsmul,
efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt,
efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf,
efsctui, efsctsi, efsctsiz, efsctuf, efsctsf,
evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb,
evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor,
evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi,
evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi,
evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts,
evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh,
evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx,
evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat,
evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx,
evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe,
evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox,
evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv,
evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq,
evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui,
evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg,
evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq,
evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf,
evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf,
evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi,
evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi,
evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw,
evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw,
evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw,
evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw,
evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw,
evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa,
evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian,
evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf,
evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa,
evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan,
evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa,
evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian,
evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi,
evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi,
evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw,
evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw,
evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa,
evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia,
evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan,
evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw,
evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw,
evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex
instructions.
(rfmci): New machine check APU instruction.
(isel): New integer select APU instructino.
(icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls,
dcbtstlse, dcblc, dcblce): New cache control APU instructions.
(mtspefscr, mfspefscr): New instructions.
(mfpmr, mtpmr): New performance monitor APU instructions.
(savecontext): New context cache APU instructions.
(bblels, bbelr): New branch locking APU instructions.
(bblels, bbelr): New instructions.
(mftbl, mftbu, mftb): Set as CLASSIC instructions. Add BOOKE alias.
* ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
instructions.
(PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
e500x2 Integer select, branch locking, performance monitor,
cache locking and machine check APUs, respectively.
(PPC_OPCODE_EFS): New opcode type for efs* instructions.
(PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
* config/mips/tm-linux.h (REALTIME_LO, REALTIME_HI): Define
conditionally.
(JB_PC, JB_ELEMENT_SIZE): Rename to MIPS_LINUX_JB_PC and
MIPS_LINUX_JB_ELEMENT_SIZE.
* mips-linux-tdep.c (supply_gregset, fill_gregset): Use alloca
for MAX_REGISTER_RAW_SIZE arrays.
(mips_linux_get_longjmp_target): Use MIPS_LINUX_JB_PC and
MIPS_LINUX_JB_ELEMENT_SIZE.
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