]> Git Repo - binutils.git/commit - sim/igen/ChangeLog
projects / binutils.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 77bd8df) | patch
o Make tic80 insn file more `cache ready'
authorAndrew Cagney <[email protected]>
Fri, 16 May 1997 03:27:40 +0000 (03:27 +0000)
committerAndrew Cagney <[email protected]>
Fri, 16 May 1997 03:27:40 +0000 (03:27 +0000)
commit37a684b84d5c722848ebdc7203052d65c6b35e30
tree3d7fa5b15efab746e9b8cc87449fa8664b6ed359tree | snapshot
parent77bd8dfa1f3678ea3c3d05f40de29a36802d21f5commit | diff
o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
sim/igen/ChangeLog diff | blob | blame | history
sim/igen/gen-semantics.c diff | blob | blame | history
sim/tic80/ChangeLog diff | blob | blame | history
sim/tic80/Makefile.in diff | blob | blame | history
sim/tic80/cpu.h diff | blob | blame | history
sim/tic80/ic diff | blob | blame | history
sim/tic80/insns diff | blob | blame | history
sim/tic80/interp.c diff | blob | blame | history
sim/tic80/sim-calls.c diff | blob | blame | history
Empty description
This page took 0.023671 seconds and 4 git commands to generate.