X-Git-Url: https://repo.jachan.dev/binutils.git/blobdiff_plain/d285ba8d064bbcfbf518cd6cf0142b5722c8215a..38cf07a6c0bae61ffba00054eb2e025a3910d93c:/opcodes/ChangeLog diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6578fbf37f..adef90c8ba 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,187 @@ +2020-09-08 Alex Coplan + + * aarch64-dis.c (print_operands): Pass CPU features to + aarch64_print_operand(). + * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine + preferred disassembly of system registers. + (SR_RNG): Refactor to use new SR_FEAT2 macro. + (SR_FEAT2): New. + (SR_V8_1_A): New. + (SR_V8_4_A): New. + (SR_V8_A): New. + (SR_V8_R): New. + (SR_EXPAND_ELx): New. + (SR_EXPAND_EL12): New. + (aarch64_sys_regs): Specify which registers are only on + A-profile, add R-profile system registers. + (ENC_BARLAR): New. + (PRBARn_ELx): New. + (PRLARn_ELx): New. + (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for + Armv8-R AArch64. + +2020-09-08 Alex Coplan + + * aarch64-tbl.h (aarch64_feature_v8_r): New. + (ARMV8_R): New. + (V8_R_INSN): New. + (aarch64_opcode_table): Add dfb. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + +2020-09-08 Alex Coplan + + * aarch64-dis.c (arch_variant): New. + (determine_disassembling_preference): Disassemble according to + arch variant. + (select_aarch64_variant): New. + (print_insn_aarch64): Set feature set. + +2020-09-02 Alan Modra + + * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3), + (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9), + (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16), + (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9), + (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID), + (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP), + (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long + for value parameter and update code to suit. + (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16), + (extract_d22, extract_d23, extract_i9): Use unsigned long variables. + +2020-09-02 Alan Modra + + * i386-dis.c (OP_E_memory): Don't cast to signed type when + negating. + (get32, get32s): Use unsigned types in shift expressions. + +2020-09-02 Alan Modra + + * csky-dis.c (print_insn_csky): Use unsigned type for "given". + +2020-09-02 Alan Modra + + * crx-dis.c: Whitespace. + (print_arg): Use unsigned type for longdisp and mask variables, + and for left shift constant. + +2020-09-02 Alan Modra + + * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift. + * bpf-ibld.c: Regenerate. + * epiphany-ibld.c: Regenerate. + * fr30-ibld.c: Regenerate. + * frv-ibld.c: Regenerate. + * ip2k-ibld.c: Regenerate. + * iq2000-ibld.c: Regenerate. + * lm32-ibld.c: Regenerate. + * m32c-ibld.c: Regenerate. + * m32r-ibld.c: Regenerate. + * mep-ibld.c: Regenerate. + * mt-ibld.c: Regenerate. + * or1k-ibld.c: Regenerate. + * xc16x-ibld.c: Regenerate. + * xstormy16-ibld.c: Regenerate. + +2020-09-02 Alan Modra + + * bfin-dis.c (MASKBITS): Use SIGNBIT. + +2020-09-02 Cooper Qu + + * csky-opc.h (csky_v2_opcodes): Move divul and divsl + to CSKYV2_ISA_3E3R3 instruction set. + +2020-09-02 Cooper Qu + + * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws. + +2020-09-01 Alan Modra + + * mep-ibld.c: Regenerate. + +2020-08-31 Cooper Qu + + * csky-dis.c (csky_output_operand): Assign dis_info.value for + OPRND_TYPE_VREG. + +2020-08-30 Alan Modra + + * cr16-dis.c: Formatting. + (parameter): Delete struct typedef. Use dwordU instead + throughout file. + (make_argument ): Simplify detection of cbitb, sbitb + and tbitb. + (make_argument ): Extract 20-bit field not 16-bit. + +2020-08-29 Alan Modra + + PR 26446 + * csky-opc.h (MAX_OPRND_NUM): Define to 5. + (union csky_operand): Use MAX_OPRND_NUM to size oprnds array. + +2020-08-28 Alan Modra + + PR 26449 + PR 26450 + * cgen-ibld.in (insert_1): Use 1UL in forming mask. + (extract_normal): Likewise. + (insert_normal): Likewise, and move past zero length test. + (put_insn_int_value): Handle mask for zero length, use 1UL. + * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, + * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, + * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, + * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. + +2020-08-28 Cooper Qu + + * csky-dis.c (CSKY_DEFAULT_ISA): Define. + (csky_dis_info): Add member isa. + (csky_find_inst_info): Skip instructions that do not belong to + current CPU. + (csky_get_disassembler): Get infomation from attribute section. + (print_insn_csky): Set defualt ISA flag. + * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2. + * csky-opc.h (struct csky_opcode): Change isa_flag16 and + isa_flag32'type to unsigned 64 bits. + +2020-08-26 Jose E. Marchesi + + * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX. + +2020-08-26 David Faust + + * bpf-desc.c: Regenerate. + * bpf-desc.h: Likewise. + * bpf-opc.c: Likewise. + * bpf-opc.h: Likewise. + * disassemble.c (disassemble_init_for_target): Set bits for xBPF + ISA when appropriate. + +2020-08-25 Alan Modra + + PR 26504 + * vax-dis.c (parse_disassembler_options): Always add at least one + to entry_addr_total_slots. + +2020-08-24 Cooper Qu + + * csky-dis.c (csky_find_inst_info): Skip CK860's instructions + in other CPUs to speed up disassembling. + * csky-opc.h (csky_v2_opcodes): Add CK860's instructions, + Change plsli.u16 to plsli.16, change sync's operand format. + +2020-08-21 Cooper Qu + + * csky-opc.h (csky_v2_opcodes): Add instruction bnezad. + +2020-08-21 Nick Clifton + + * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF + symbols. + 2020-08-21 Cooper Qu * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.