X-Git-Url: https://repo.jachan.dev/binutils.git/blobdiff_plain/a00a19e94cc700d757c2fe07ccec78c46a24cd13..25ab47902d12c8ffca6ab50b2b17151f1d86ce9b:/gdb/mips-tdep.c diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index 267b7802f3..df3e94198e 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -25,6 +25,7 @@ #include "defs.h" #include "gdb_string.h" +#include "gdb_assert.h" #include "frame.h" #include "inferior.h" #include "symtab.h" @@ -40,6 +41,7 @@ #include "regcache.h" #include "osabi.h" #include "mips-tdep.h" +#include "block.h" #include "opcode/mips.h" #include "elf/mips.h" @@ -148,6 +150,36 @@ static const char *mips_saved_regsize_string = size_auto; #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) +/* Return the contents of register REGNUM as a signed integer. */ + +static LONGEST +read_signed_register (int regnum) +{ + void *buf = alloca (REGISTER_RAW_SIZE (regnum)); + deprecated_read_register_gen (regnum, buf); + return (extract_signed_integer (buf, REGISTER_RAW_SIZE (regnum))); +} + +static LONGEST +read_signed_register_pid (int regnum, ptid_t ptid) +{ + ptid_t save_ptid; + LONGEST retval; + + if (ptid_equal (ptid, inferior_ptid)) + return read_signed_register (regnum); + + save_ptid = inferior_ptid; + + inferior_ptid = ptid; + + retval = read_signed_register (regnum); + + inferior_ptid = save_ptid; + + return retval; +} + /* Return the MIPS ABI associated with GDBARCH. */ enum mips_abi mips_abi (struct gdbarch *gdbarch) @@ -213,7 +245,7 @@ mips_xfer_register (struct regcache *regcache, int reg_num, int length, enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, int buf_offset) { - bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE); + bfd_byte reg[MAX_REGISTER_SIZE]; int reg_offset = 0; /* Need to transfer the left or right part of the register, based on the targets byte order. */ @@ -320,8 +352,8 @@ int gdb_print_insn_mips (bfd_vma, disassemble_info *); static void mips_print_register (int, int); -static mips_extra_func_info_t -heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int); +static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, + struct frame_info *, int); static CORE_ADDR heuristic_proc_start (CORE_ADDR); @@ -333,8 +365,9 @@ static void mips_show_processor_type_command (char *, int); static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); -static mips_extra_func_info_t -find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame); +static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, + struct frame_info *next_frame, + int cur_frame); static CORE_ADDR after_prologue (CORE_ADDR pc, mips_extra_func_info_t proc_desc); @@ -359,23 +392,57 @@ static struct cmd_list_element *showmipscmdlist = NULL; /* A set of original names, to be used when restoring back to generic registers from a specific set. */ +static char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; -char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; -char **mips_processor_reg_names = mips_generic_reg_names; +/* Integer registers 0 thru 31 are handled explicitly by + mips_register_name(). Processor specific registers 32 and above + are listed in the sets of register names assigned to + mips_processor_reg_names. */ +static char **mips_processor_reg_names = mips_generic_reg_names; +/* Return the name of the register corresponding to REGNO. */ static const char * -mips_register_name (int i) -{ - return mips_processor_reg_names[i]; +mips_register_name (int regno) +{ + /* GPR names for all ABIs other than n32/n64. */ + static char *mips_gpr_names[] = { + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", + }; + + /* GPR names for n32 and n64 ABIs. */ + static char *mips_n32_n64_gpr_names[] = { + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" + }; + + enum mips_abi abi = mips_abi (current_gdbarch); + + /* The MIPS integer registers are always mapped from 0 to 31. The + names of the registers (which reflects the conventions regarding + register use) vary depending on the ABI. */ + if (0 <= regno && regno < 32) + { + if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) + return mips_n32_n64_gpr_names[regno]; + else + return mips_gpr_names[regno]; + } + else if (32 <= regno && regno < NUM_REGS) + return mips_processor_reg_names[regno - 32]; + else + internal_error (__FILE__, __LINE__, + "mips_register_name: bad register number %d", regno); } + /* *INDENT-OFF* */ /* Names of IDT R3041 registers. */ char *mips_r3041_reg_names[] = { - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", "sr", "lo", "hi", "bad", "cause","pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", @@ -389,10 +456,6 @@ char *mips_r3041_reg_names[] = { /* Names of IDT R3051 registers. */ char *mips_r3051_reg_names[] = { - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", "sr", "lo", "hi", "bad", "cause","pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", @@ -406,10 +469,6 @@ char *mips_r3051_reg_names[] = { /* Names of IDT R3081 registers. */ char *mips_r3081_reg_names[] = { - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", "sr", "lo", "hi", "bad", "cause","pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", @@ -423,10 +482,6 @@ char *mips_r3081_reg_names[] = { /* Names of LSI 33k registers. */ char *mips_lsi33k_reg_names[] = { - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", "epc", "hi", "lo", "sr", "cause","badvaddr", "dcic", "bpc", "bda", "", "", "", "", "", "", "", "", "", "", "", "", "", @@ -492,12 +547,12 @@ void mips_print_extra_frame_info (struct frame_info *fi) { if (fi - && fi->extra_info - && fi->extra_info->proc_desc - && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS) + && get_frame_extra_info (fi) + && get_frame_extra_info (fi)->proc_desc + && get_frame_extra_info (fi)->proc_desc->pdr.framereg < NUM_REGS) printf_filtered (" frame pointer is at %s+%s\n", - REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg), - paddr_d (fi->extra_info->proc_desc->pdr.frameoffset)); + REGISTER_NAME (get_frame_extra_info (fi)->proc_desc->pdr.framereg), + paddr_d (get_frame_extra_info (fi)->proc_desc->pdr.frameoffset)); } /* Number of bytes of storage in the actual machine representation for @@ -598,9 +653,9 @@ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG Note: kevinb/2002-08-01: The definition below should faithfully reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE - definitions found in config/mips/tm-*.h. I'm concerned about - the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause - though. In some cases FP_REGNUM is in this range, and I doubt + definitions found in config/mips/tm-*.h. I'm concerned about the + ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause though. + In some cases DEPRECATED_FP_REGNUM is in this range, and I doubt that this code is correct for the 64-bit case. */ static struct type * @@ -634,7 +689,7 @@ mips_register_virtual_type (int reg) static CORE_ADDR mips_read_sp (void) { - return ADDR_BITS_REMOVE (read_register (SP_REGNUM)); + return read_signed_register (SP_REGNUM); } /* Should the upper word of 64-bit addresses be zeroed? */ @@ -1420,21 +1475,21 @@ mips_find_saved_regs (struct frame_info *fci) { for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) { - reg_position = fci->frame + SIGFRAME_REGSAVE_OFF + reg_position = get_frame_base (fci) + SIGFRAME_REGSAVE_OFF + ireg * SIGFRAME_REG_SIZE; get_frame_saved_regs (fci)[ireg] = reg_position; } for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) { - reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF + reg_position = get_frame_base (fci) + SIGFRAME_FPREGSAVE_OFF + ireg * SIGFRAME_REG_SIZE; get_frame_saved_regs (fci)[FP0_REGNUM + ireg] = reg_position; } - get_frame_saved_regs (fci)[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; + get_frame_saved_regs (fci)[PC_REGNUM] = get_frame_base (fci) + SIGFRAME_PC_OFF; return; } - proc_desc = fci->extra_info->proc_desc; + proc_desc = get_frame_extra_info (fci)->proc_desc; if (proc_desc == NULL) /* I'm not sure how/whether this can happen. Normally when we can't find a proc_desc, we "synthesize" one using heuristic_proc_desc @@ -1449,7 +1504,8 @@ mips_find_saved_regs (struct frame_info *fci) a signal, we assume that all registers have been saved. This assumes that all register saves in a function happen before the first function call. */ - (fci->next == NULL || (get_frame_type (fci->next) == SIGTRAMP_FRAME)) + (get_next_frame (fci) == NULL + || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME)) /* In a dummy frame we know exactly where things are saved. */ && !PROC_DESC_IS_DUMMY (proc_desc) @@ -1496,7 +1552,7 @@ mips_find_saved_regs (struct frame_info *fci) /* Fill in the offsets for the registers which gen_mask says were saved. */ - reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); + reg_position = get_frame_base (fci) + PROC_REG_OFFSET (proc_desc); for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) if (gen_mask & 0x80000000) { @@ -1517,7 +1573,7 @@ mips_find_saved_regs (struct frame_info *fci) int sreg_count = (inst >> 6) & 3; /* Check if the ra register was pushed on the stack. */ - reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); + reg_position = get_frame_base (fci) + PROC_REG_OFFSET (proc_desc); if (inst & 0x20) reg_position -= MIPS_SAVED_REGSIZE; @@ -1532,7 +1588,7 @@ mips_find_saved_regs (struct frame_info *fci) /* Fill in the offsets for the registers which float_mask says were saved. */ - reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); + reg_position = get_frame_base (fci) + PROC_FREG_OFFSET (proc_desc); /* Apparently, the freg_offset gives the offset to the first 64 bit saved. @@ -1576,7 +1632,7 @@ mips_frame_init_saved_regs (struct frame_info *frame) { mips_find_saved_regs (frame); } - get_frame_saved_regs (frame)[SP_REGNUM] = frame->frame; + get_frame_saved_regs (frame)[SP_REGNUM] = get_frame_base (frame); } static CORE_ADDR @@ -1586,21 +1642,29 @@ read_next_frame_reg (struct frame_info *fi, int regno) CORE_ADDR addr; int realnum; enum lval_type lval; - void *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); - frame_register_unwind (fi, regno, &optimized, &lval, &addr, &realnum, - raw_buffer); - /* FIXME: cagney/2002-09-13: This is just soooo bad. The MIPS - should have a pseudo register range that correspons to the ABI's, - rather than the ISA's, view of registers. These registers would - then implicitly describe their size and hence could be used - without the below munging. */ - if (lval == lval_memory) + char raw_buffer[MAX_REGISTER_SIZE]; + + if (fi == NULL) { - if (regno < 32) + regcache_cooked_read (current_regcache, regno, raw_buffer); + } + else + { + frame_register_unwind (fi, regno, &optimized, &lval, &addr, &realnum, + raw_buffer); + /* FIXME: cagney/2002-09-13: This is just soooo bad. The MIPS + should have a pseudo register range that correspons to the ABI's, + rather than the ISA's, view of registers. These registers would + then implicitly describe their size and hence could be used + without the below munging. */ + if (lval == lval_memory) { - /* Only MIPS_SAVED_REGSIZE bytes of GP registers are - saved. */ - return read_memory_integer (addr, MIPS_SAVED_REGSIZE); + if (regno < 32) + { + /* Only MIPS_SAVED_REGSIZE bytes of GP registers are + saved. */ + return read_memory_integer (addr, MIPS_SAVED_REGSIZE); + } } } @@ -1680,8 +1744,11 @@ mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) { CORE_ADDR pc, tmp; - pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : - prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); + pc = ((fromleaf) + ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) + : get_next_frame (prev) + ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) + : read_pc ()); tmp = SKIP_TRAMPOLINE_CODE (pc); return tmp ? tmp : pc; } @@ -1691,7 +1758,7 @@ static CORE_ADDR mips_frame_saved_pc (struct frame_info *frame) { CORE_ADDR saved_pc; - mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; + mips_extra_func_info_t proc_desc = get_frame_extra_info (frame)->proc_desc; /* We have to get the saved pc from the sigcontext if it is a signal handler frame. */ int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME) ? PC_REGNUM @@ -1704,7 +1771,7 @@ mips_frame_saved_pc (struct frame_info *frame) saved_pc = tmp; } else if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) - saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); + saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); else saved_pc = read_next_frame_reg (frame, pcreg); @@ -1781,10 +1848,10 @@ heuristic_proc_start (CORE_ADDR pc) if (start_pc < fence) { /* It's not clear to me why we reach this point when - stop_soon_quietly, but with this test, at least we + stop_soon, but with this test, at least we don't print out warnings for every child forked (eg, on decstation). 22apr93 rich@cygnus.com. */ - if (!stop_soon_quietly) + if (stop_soon == NO_STOP_QUIETLY) { static int blurb_printed = 0; @@ -2322,7 +2389,7 @@ non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) return NULL; } - sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); + sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); /* If we never found a PDR for this function in symbol reading, then examine prologues to find the information. */ @@ -2405,10 +2472,9 @@ static CORE_ADDR get_frame_pointer (struct frame_info *frame, mips_extra_func_info_t proc_desc) { - return ADDR_BITS_REMOVE (read_next_frame_reg (frame, - PROC_FRAME_REG (proc_desc)) + - PROC_FRAME_OFFSET (proc_desc) - - PROC_FRAME_ADJUST (proc_desc)); + return (read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) + + PROC_FRAME_OFFSET (proc_desc) + - PROC_FRAME_ADJUST (proc_desc)); } static mips_extra_func_info_t cached_proc_desc; @@ -2418,7 +2484,7 @@ mips_frame_chain (struct frame_info *frame) { mips_extra_func_info_t proc_desc; CORE_ADDR tmp; - CORE_ADDR saved_pc = FRAME_SAVED_PC (frame); + CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame); if (saved_pc == 0 || inside_entry_file (saved_pc)) return 0; @@ -2433,7 +2499,7 @@ mips_frame_chain (struct frame_info *frame) /* A dummy frame, uses SP not FP. Get the old SP value. If all is well, frame->frame the bottom of the current frame will contain that value. */ - return frame->frame; + return get_frame_base (frame); } /* Look up the procedure descriptor for this PC. */ @@ -2463,15 +2529,26 @@ static void mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) { int regnum; + mips_extra_func_info_t proc_desc; - /* Use proc_desc calculated in frame_chain */ - mips_extra_func_info_t proc_desc = - fci->next ? cached_proc_desc : find_proc_desc (get_frame_pc (fci), fci->next, 1); + if (get_frame_type (fci) == DUMMY_FRAME) + return; + + /* Use proc_desc calculated in frame_chain. When there is no + next frame, i.e, get_next_frame (fci) == NULL, we call + find_proc_desc () to calculate it, passing an explicit + NULL as the frame parameter. */ + proc_desc = + get_next_frame (fci) + ? cached_proc_desc + : find_proc_desc (get_frame_pc (fci), + NULL /* i.e, get_next_frame (fci) */, + 1); frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info)); - fci->saved_regs = NULL; - fci->extra_info->proc_desc = + deprecated_set_frame_saved_regs_hack (fci, NULL); + get_frame_extra_info (fci)->proc_desc = proc_desc == &temp_proc_desc ? 0 : proc_desc; if (proc_desc) { @@ -2481,7 +2558,7 @@ mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) interrupted by a signal at it's very start. */ if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc) && !PROC_DESC_IS_DUMMY (proc_desc)) - deprecated_update_frame_base_hack (fci, read_next_frame_reg (fci->next, SP_REGNUM)); + deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), SP_REGNUM)); else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0)) /* Do not ``fix'' fci->frame. It will have the value of the generic dummy frame's top-of-stack (since the draft @@ -2491,7 +2568,7 @@ mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) part of the dummy frames data. */ /* Do nothing. */; else - deprecated_update_frame_base_hack (fci, get_frame_pointer (fci->next, proc_desc)); + deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc)); if (proc_desc == &temp_proc_desc) { @@ -2517,18 +2594,18 @@ mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) value of the stack pointer register. The other saved_regs values are addresses (in the inferior) at which a given register's value may be found. */ - get_frame_saved_regs (fci)[SP_REGNUM] = fci->frame; + get_frame_saved_regs (fci)[SP_REGNUM] = get_frame_base (fci); } } /* hack: if argument regs are saved, guess these contain args */ /* assume we can't tell how many args for now */ - fci->extra_info->num_args = -1; + get_frame_extra_info (fci)->num_args = -1; for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) { if (PROC_REG_MASK (proc_desc) & (1 << regnum)) { - fci->extra_info->num_args = regnum - A0_REGNUM + 1; + get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1; break; } } @@ -2620,11 +2697,10 @@ mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) } static CORE_ADDR -mips_eabi_push_arguments (int nargs, - struct value **args, - CORE_ADDR sp, - int struct_return, - CORE_ADDR struct_addr) +mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, + struct regcache *regcache, CORE_ADDR bp_addr, int nargs, + struct value **args, CORE_ADDR sp, int struct_return, + CORE_ADDR struct_addr) { int argreg; int float_argreg; @@ -2632,6 +2708,14 @@ mips_eabi_push_arguments (int nargs, int len = 0; int stack_offset = 0; + /* For shared libraries, "t9" needs to point at the function + address. */ + regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); + + /* Set the return address register to point to the entry point of + the program, where a breakpoint lies in wait. */ + regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); + /* First ensure that the stack and structure return address (if any) are properly aligned. The stack has to be at least 64-bit aligned even on 32-bit machines, because doubles must be 64-bit @@ -2651,7 +2735,7 @@ mips_eabi_push_arguments (int nargs, if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_eabi_push_arguments: sp=0x%s allocated %d\n", + "mips_eabi_push_dummy_call: sp=0x%s allocated %d\n", paddr_nz (sp), ROUND_UP (len, 16)); /* Initialize the integer and float register pointers. */ @@ -2663,7 +2747,7 @@ mips_eabi_push_arguments (int nargs, { if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n", + "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", argreg, paddr_nz (struct_addr)); write_register (argreg++, struct_addr); } @@ -2674,7 +2758,7 @@ mips_eabi_push_arguments (int nargs, for (argnum = 0; argnum < nargs; argnum++) { char *val; - char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); + char valbuf[MAX_REGISTER_SIZE]; struct value *arg = args[argnum]; struct type *arg_type = check_typedef (VALUE_TYPE (arg)); int len = TYPE_LENGTH (arg_type); @@ -2682,7 +2766,7 @@ mips_eabi_push_arguments (int nargs, if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_eabi_push_arguments: %d len=%d type=%d", + "mips_eabi_push_dummy_call: %d len=%d type=%d", argnum + 1, len, (int) typecode); /* The EABI passes structures that do not fit in a register by @@ -2690,7 +2774,7 @@ mips_eabi_push_arguments (int nargs, if (len > MIPS_SAVED_REGSIZE && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) { - store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); + store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); typecode = TYPE_CODE_PTR; len = MIPS_SAVED_REGSIZE; val = valbuf; @@ -2870,14 +2954,13 @@ mips_eabi_push_arguments (int nargs, return sp; } -/* N32/N64 version of push_arguments. */ +/* N32/N64 version of push_dummy_call. */ static CORE_ADDR -mips_n32n64_push_arguments (int nargs, - struct value **args, - CORE_ADDR sp, - int struct_return, - CORE_ADDR struct_addr) +mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, + struct regcache *regcache, CORE_ADDR bp_addr, int nargs, + struct value **args, CORE_ADDR sp, int struct_return, + CORE_ADDR struct_addr) { int argreg; int float_argreg; @@ -2885,6 +2968,14 @@ mips_n32n64_push_arguments (int nargs, int len = 0; int stack_offset = 0; + /* For shared libraries, "t9" needs to point at the function + address. */ + regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); + + /* Set the return address register to point to the entry point of + the program, where a breakpoint lies in wait. */ + regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); + /* First ensure that the stack and structure return address (if any) are properly aligned. The stack has to be at least 64-bit aligned even on 32-bit machines, because doubles must be 64-bit @@ -2902,7 +2993,7 @@ mips_n32n64_push_arguments (int nargs, if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_n32n64_push_arguments: sp=0x%s allocated %d\n", + "mips_n32n64_push_dummy_call: sp=0x%s allocated %d\n", paddr_nz (sp), ROUND_UP (len, 16)); /* Initialize the integer and float register pointers. */ @@ -2914,7 +3005,7 @@ mips_n32n64_push_arguments (int nargs, { if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n", + "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", argreg, paddr_nz (struct_addr)); write_register (argreg++, struct_addr); } @@ -2925,7 +3016,7 @@ mips_n32n64_push_arguments (int nargs, for (argnum = 0; argnum < nargs; argnum++) { char *val; - char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); + char valbuf[MAX_REGISTER_SIZE]; struct value *arg = args[argnum]; struct type *arg_type = check_typedef (VALUE_TYPE (arg)); int len = TYPE_LENGTH (arg_type); @@ -2933,7 +3024,7 @@ mips_n32n64_push_arguments (int nargs, if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_n32n64_push_arguments: %d len=%d type=%d", + "mips_n32n64_push_dummy_call: %d len=%d type=%d", argnum + 1, len, (int) typecode); val = (char *) VALUE_CONTENTS (arg); @@ -3092,14 +3183,13 @@ mips_n32n64_push_arguments (int nargs, return sp; } -/* O32 version of push_arguments. */ +/* O32 version of push_dummy_call. */ static CORE_ADDR -mips_o32_push_arguments (int nargs, - struct value **args, - CORE_ADDR sp, - int struct_return, - CORE_ADDR struct_addr) +mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, + struct regcache *regcache, CORE_ADDR bp_addr, int nargs, + struct value **args, CORE_ADDR sp, int struct_return, + CORE_ADDR struct_addr) { int argreg; int float_argreg; @@ -3107,6 +3197,14 @@ mips_o32_push_arguments (int nargs, int len = 0; int stack_offset = 0; + /* For shared libraries, "t9" needs to point at the function + address. */ + regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); + + /* Set the return address register to point to the entry point of + the program, where a breakpoint lies in wait. */ + regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); + /* First ensure that the stack and structure return address (if any) are properly aligned. The stack has to be at least 64-bit aligned even on 32-bit machines, because doubles must be 64-bit @@ -3124,7 +3222,7 @@ mips_o32_push_arguments (int nargs, if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_o32_push_arguments: sp=0x%s allocated %d\n", + "mips_o32_push_dummy_call: sp=0x%s allocated %d\n", paddr_nz (sp), ROUND_UP (len, 16)); /* Initialize the integer and float register pointers. */ @@ -3136,7 +3234,7 @@ mips_o32_push_arguments (int nargs, { if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_o32_push_arguments: struct_return reg=%d 0x%s\n", + "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", argreg, paddr_nz (struct_addr)); write_register (argreg++, struct_addr); stack_offset += MIPS_STACK_ARGSIZE; @@ -3148,7 +3246,7 @@ mips_o32_push_arguments (int nargs, for (argnum = 0; argnum < nargs; argnum++) { char *val; - char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); + char valbuf[MAX_REGISTER_SIZE]; struct value *arg = args[argnum]; struct type *arg_type = check_typedef (VALUE_TYPE (arg)); int len = TYPE_LENGTH (arg_type); @@ -3156,7 +3254,7 @@ mips_o32_push_arguments (int nargs, if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_o32_push_arguments: %d len=%d type=%d", + "mips_o32_push_dummy_call: %d len=%d type=%d", argnum + 1, len, (int) typecode); val = (char *) VALUE_CONTENTS (arg); @@ -3391,14 +3489,13 @@ mips_o32_push_arguments (int nargs, return sp; } -/* O64 version of push_arguments. */ +/* O64 version of push_dummy_call. */ static CORE_ADDR -mips_o64_push_arguments (int nargs, - struct value **args, - CORE_ADDR sp, - int struct_return, - CORE_ADDR struct_addr) +mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, + struct regcache *regcache, CORE_ADDR bp_addr, int nargs, + struct value **args, CORE_ADDR sp, int struct_return, + CORE_ADDR struct_addr) { int argreg; int float_argreg; @@ -3406,6 +3503,14 @@ mips_o64_push_arguments (int nargs, int len = 0; int stack_offset = 0; + /* For shared libraries, "t9" needs to point at the function + address. */ + regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); + + /* Set the return address register to point to the entry point of + the program, where a breakpoint lies in wait. */ + regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); + /* First ensure that the stack and structure return address (if any) are properly aligned. The stack has to be at least 64-bit aligned even on 32-bit machines, because doubles must be 64-bit @@ -3423,7 +3528,7 @@ mips_o64_push_arguments (int nargs, if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_o64_push_arguments: sp=0x%s allocated %d\n", + "mips_o64_push_dummy_call: sp=0x%s allocated %d\n", paddr_nz (sp), ROUND_UP (len, 16)); /* Initialize the integer and float register pointers. */ @@ -3435,7 +3540,7 @@ mips_o64_push_arguments (int nargs, { if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_o64_push_arguments: struct_return reg=%d 0x%s\n", + "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", argreg, paddr_nz (struct_addr)); write_register (argreg++, struct_addr); stack_offset += MIPS_STACK_ARGSIZE; @@ -3447,7 +3552,7 @@ mips_o64_push_arguments (int nargs, for (argnum = 0; argnum < nargs; argnum++) { char *val; - char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); + char valbuf[MAX_REGISTER_SIZE]; struct value *arg = args[argnum]; struct type *arg_type = check_typedef (VALUE_TYPE (arg)); int len = TYPE_LENGTH (arg_type); @@ -3455,7 +3560,7 @@ mips_o64_push_arguments (int nargs, if (mips_debug) fprintf_unfiltered (gdb_stdlog, - "mips_o64_push_arguments: %d len=%d type=%d", + "mips_o64_push_dummy_call: %d len=%d type=%d", argnum + 1, len, (int) typecode); val = (char *) VALUE_CONTENTS (arg); @@ -3690,127 +3795,13 @@ mips_o64_push_arguments (int nargs, return sp; } -static CORE_ADDR -mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp) -{ - /* Set the return address register to point to the entry - point of the program, where a breakpoint lies in wait. */ - write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ()); - return sp; -} - -static void -mips_push_register (CORE_ADDR * sp, int regno) -{ - char *buffer = alloca (MAX_REGISTER_RAW_SIZE); - int regsize; - int offset; - if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno)) - { - regsize = MIPS_SAVED_REGSIZE; - offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG - ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE - : 0); - } - else - { - regsize = REGISTER_RAW_SIZE (regno); - offset = 0; - } - *sp -= regsize; - deprecated_read_register_gen (regno, buffer); - write_memory (*sp, buffer + offset, regsize); -} - -/* MASK(i,j) == (1<info; - CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM)); - CORE_ADDR old_sp = sp; - link->next = linked_proc_desc_table; - linked_proc_desc_table = link; - -/* FIXME! are these correct ? */ -#define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ -#define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) -#define FLOAT_REG_SAVE_MASK MASK(0,19) -#define FLOAT_SINGLE_REG_SAVE_MASK \ - ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) - /* - * The registers we must save are all those not preserved across - * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. - * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI - * and FP Control/Status registers. - * - * - * Dummy frame layout: - * (high memory) - * Saved PC - * Saved MMHI, MMLO, FPC_CSR - * Saved R31 - * Saved R28 - * ... - * Saved R1 - * Saved D18 (i.e. F19, F18) - * ... - * Saved D0 (i.e. F1, F0) - * Argument build area and stack arguments written via mips_push_arguments - * (low memory) - */ - - /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ - PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM; - PROC_FRAME_OFFSET (proc_desc) = 0; - PROC_FRAME_ADJUST (proc_desc) = 0; - mips_push_register (&sp, PC_REGNUM); - mips_push_register (&sp, HI_REGNUM); - mips_push_register (&sp, LO_REGNUM); - mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); - - /* Save general CPU registers */ - PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK; - /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ - PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE; - for (ireg = 32; --ireg >= 0;) - if (PROC_REG_MASK (proc_desc) & (1 << ireg)) - mips_push_register (&sp, ireg); - - /* Save floating point registers starting with high order word */ - PROC_FREG_MASK (proc_desc) = - MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK - : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; - /* PROC_FREG_OFFSET is the offset of the first saved *double* register - from FP. */ - PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8; - for (ireg = 32; --ireg >= 0;) - if (PROC_FREG_MASK (proc_desc) & (1 << ireg)) - mips_push_register (&sp, ireg + FP0_REGNUM); - - /* Update the frame pointer for the call dummy and the stack pointer. - Set the procedure's starting and ending addresses to point to the - call dummy address at the entry point. */ - write_register (PUSH_FP_REGNUM, old_sp); - write_register (SP_REGNUM, sp); - PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS (); - PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4; - SET_PROC_DESC_IS_DUMMY (proc_desc); - PROC_PC_REG (proc_desc) = RA_REGNUM; -} - static void mips_pop_frame (void) { register int regnum; struct frame_info *frame = get_current_frame (); CORE_ADDR new_sp = get_frame_base (frame); - mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; + mips_extra_func_info_t proc_desc; if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) { @@ -3819,9 +3810,10 @@ mips_pop_frame (void) return; } - write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); + proc_desc = get_frame_extra_info (frame)->proc_desc; + write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); if (get_frame_saved_regs (frame) == NULL) - FRAME_INIT_SAVED_REGS (frame); + DEPRECATED_FRAME_INIT_SAVED_REGS (frame); for (regnum = 0; regnum < NUM_REGS; regnum++) if (regnum != SP_REGNUM && regnum != PC_REGNUM && get_frame_saved_regs (frame)[regnum]) @@ -3877,13 +3869,6 @@ mips_pop_frame (void) } } -static void -mips_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, - struct value **args, struct type *type, int gcc_p) -{ - write_register(T9_REGNUM, fun); -} - /* Floating point register management. Background: MIPS1 & 2 fp registers are 32 bits wide. To support @@ -4001,161 +3986,133 @@ mips_read_fp_register_double (int regno, char *rare_buffer) } static void -mips_print_register (int regnum, int all) -{ - char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); - - /* Get the data in raw format. */ - if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer)) - { - printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); - return; - } - - /* If we have a actual 32-bit floating point register (or we are in - 32-bit compatibility mode), and the register is even-numbered, - also print it as a double (spanning two registers). */ - if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT - && (REGISTER_RAW_SIZE (regnum) == 4 - || mips2_fp_compat ()) - && !((regnum - FP0_REGNUM) & 1)) - { - char *dbuffer = alloca (2 * MAX_REGISTER_RAW_SIZE); - - mips_read_fp_register_double (regnum, dbuffer); - - printf_filtered ("(d%d: ", regnum - FP0_REGNUM); - val_print (mips_double_register_type (), dbuffer, 0, 0, - gdb_stdout, 0, 1, 0, Val_pretty_default); - printf_filtered ("); "); - } - fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); - - /* The problem with printing numeric register names (r26, etc.) is that - the user can't use them on input. Probably the best solution is to - fix it so that either the numeric or the funky (a2, etc.) names - are accepted on input. */ - if (regnum < MIPS_NUMREGS) - printf_filtered ("(r%d): ", regnum); - else - printf_filtered (": "); - - /* If virtual format is floating, print it that way. */ - if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) - if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ()) - { - /* We have a meaningful 64-bit value in this register. Show - it as a 32-bit float and a 64-bit double. */ - int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG); - - printf_filtered (" (float) "); - val_print (mips_float_register_type (), raw_buffer + offset, 0, 0, - gdb_stdout, 0, 1, 0, Val_pretty_default); - printf_filtered (", (double) "); - val_print (mips_double_register_type (), raw_buffer, 0, 0, - gdb_stdout, 0, 1, 0, Val_pretty_default); - } - else - val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, - gdb_stdout, 0, 1, 0, Val_pretty_default); - /* Else print as integer in hex. */ - else - { - int offset; - - if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) - offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); - else - offset = 0; - - print_scalar_formatted (raw_buffer + offset, - REGISTER_VIRTUAL_TYPE (regnum), - 'x', 0, gdb_stdout); - } -} - -/* Replacement for generic do_registers_info. - Print regs in pretty columns. */ - -static int -do_fp_register_row (int regnum) +mips_print_fp_register (int regnum) { /* do values for FP (float) regs */ char *raw_buffer; double doub, flt1, flt2; /* doubles extracted from raw hex data */ - int inv1, inv2, inv3; + int inv1, inv2, namelen; raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); + printf_filtered ("%s:", REGISTER_NAME (regnum)); + printf_filtered ("%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), ""); + if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ()) { - /* 4-byte registers: we can fit two registers per row. */ - /* Also print every pair of 4-byte regs as an 8-byte double. */ + /* 4-byte registers: Print hex and floating. Also print even + numbered registers as doubles. */ mips_read_fp_register_single (regnum, raw_buffer); flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); - mips_read_fp_register_single (regnum + 1, raw_buffer); - flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2); + print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', + gdb_stdout); - mips_read_fp_register_double (regnum, raw_buffer); - doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3); - - printf_filtered (" %-5s", REGISTER_NAME (regnum)); + printf_filtered (" flt: "); if (inv1) - printf_filtered (": "); + printf_filtered (" "); else printf_filtered ("%-17.9g", flt1); - printf_filtered (" %-5s", REGISTER_NAME (regnum + 1)); - if (inv2) - printf_filtered (": "); - else - printf_filtered ("%-17.9g", flt2); - - printf_filtered (" dbl: "); - if (inv3) - printf_filtered (""); - else - printf_filtered ("%-24.17g", doub); - printf_filtered ("\n"); + if (regnum % 2 == 0) + { + mips_read_fp_register_double (regnum, raw_buffer); + doub = unpack_double (mips_double_register_type (), raw_buffer, + &inv2); - /* may want to do hex display here (future enhancement) */ - regnum += 2; + printf_filtered (" dbl: "); + if (inv2) + printf_filtered (""); + else + printf_filtered ("%-24.17g", doub); + } } else { - /* Eight byte registers: print each one as float AND as double. */ + /* Eight byte registers: print each one as hex, float and double. */ mips_read_fp_register_single (regnum, raw_buffer); - flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1); + flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); mips_read_fp_register_double (regnum, raw_buffer); - doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3); + doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); + + + print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', + gdb_stdout); - printf_filtered (" %-5s: ", REGISTER_NAME (regnum)); + printf_filtered (" flt: "); if (inv1) printf_filtered (""); else - printf_filtered ("flt: %-17.9g", flt1); + printf_filtered ("%-17.9g", flt1); printf_filtered (" dbl: "); - if (inv3) + if (inv2) printf_filtered (""); else printf_filtered ("%-24.17g", doub); + } +} - printf_filtered ("\n"); - /* may want to do hex display here (future enhancement) */ - regnum++; +static void +mips_print_register (int regnum, int all) +{ + char raw_buffer[MAX_REGISTER_SIZE]; + int offset; + + if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) + { + mips_print_fp_register (regnum); + return; } - return regnum; + + /* Get the data in raw format. */ + if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer)) + { + printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); + return; + } + + fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); + + /* The problem with printing numeric register names (r26, etc.) is that + the user can't use them on input. Probably the best solution is to + fix it so that either the numeric or the funky (a2, etc.) names + are accepted on input. */ + if (regnum < MIPS_NUMREGS) + printf_filtered ("(r%d): ", regnum); + else + printf_filtered (": "); + + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); + else + offset = 0; + + print_scalar_formatted (raw_buffer + offset, + REGISTER_VIRTUAL_TYPE (regnum), + 'x', 0, gdb_stdout); } +/* Replacement for generic do_registers_info. + Print regs in pretty columns. */ + +static int +do_fp_register_row (int regnum) +{ + printf_filtered (" "); + mips_print_fp_register (regnum); + printf_filtered ("\n"); + return regnum + 1; +} + + /* Print a row's worth of GP (int) registers, with name labels above */ static int do_gp_register_row (int regnum) { /* do values for GP (int) regs */ - char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); + char raw_buffer[MAX_REGISTER_SIZE]; int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ int col, byte; int start_regnum = regnum; @@ -4616,7 +4573,7 @@ return_value_location (struct type *valtype, static void mips_eabi_extract_return_value (struct type *valtype, - char regbuf[REGISTER_BYTES], + char regbuf[], char *valbuf) { struct return_value_word lo; @@ -4635,7 +4592,7 @@ mips_eabi_extract_return_value (struct type *valtype, static void mips_o64_extract_return_value (struct type *valtype, - char regbuf[REGISTER_BYTES], + char regbuf[], char *valbuf) { struct return_value_word lo; @@ -4658,7 +4615,7 @@ mips_o64_extract_return_value (struct type *valtype, static void mips_eabi_store_return_value (struct type *valtype, char *valbuf) { - char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); + char raw_buffer[MAX_REGISTER_SIZE]; struct return_value_word lo; struct return_value_word hi; return_value_location (valtype, &hi, &lo); @@ -4680,7 +4637,7 @@ mips_eabi_store_return_value (struct type *valtype, char *valbuf) static void mips_o64_store_return_value (struct type *valtype, char *valbuf) { - char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); + char raw_buffer[MAX_REGISTER_SIZE]; struct return_value_word lo; struct return_value_word hi; return_value_location (valtype, &hi, &lo); @@ -4762,7 +4719,7 @@ mips_o32_xfer_return_value (struct type *type, /* A struct that contains one or two floats. Each value is part in the least significant part of their floating point register.. */ - bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE); + bfd_byte reg[MAX_REGISTER_SIZE]; int regnum; int field; for (field = 0, regnum = FP0_REGNUM; @@ -4874,7 +4831,7 @@ mips_n32n64_xfer_return_value (struct type *type, /* A struct that contains one or two floats. Each value is part in the least significant part of their floating point register.. */ - bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE); + bfd_byte reg[MAX_REGISTER_SIZE]; int regnum; int field; for (field = 0, regnum = FP0_REGNUM; @@ -4948,12 +4905,6 @@ mips_n32n64_store_return_value (struct type *type, char *valbuf) mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf); } -static void -mips_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) -{ - /* Nothing to do -- push_arguments does all the work. */ -} - static CORE_ADDR mips_extract_struct_value_address (struct regcache *regcache) { @@ -5174,19 +5125,6 @@ gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info) return print_insn_little_mips (memaddr, info); } -/* Old-style breakpoint macros. - The IDT board uses an unusual breakpoint value, and sometimes gets - confused when it sees the usual MIPS breakpoint instruction. */ - -#define BIG_BREAKPOINT {0, 0x5, 0, 0xd} -#define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} -#define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} -#define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} -#define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} -#define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} -#define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} -#define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} - /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program counter value to determine whether a 16- or 32-bit breakpoint should be used. It returns a pointer to a string of bytes that encode a breakpoint @@ -5201,17 +5139,19 @@ mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) { if (pc_is_mips16 (*pcptr)) { - static unsigned char mips16_big_breakpoint[] = - MIPS16_BIG_BREAKPOINT; + static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5}; *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); *lenptr = sizeof (mips16_big_breakpoint); return mips16_big_breakpoint; } else { - static unsigned char big_breakpoint[] = BIG_BREAKPOINT; - static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; - static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; + /* The IDT board uses an unusual breakpoint value, and + sometimes gets confused when it sees the usual MIPS + breakpoint instruction. */ + static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd}; + static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd}; + static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd}; *lenptr = sizeof (big_breakpoint); @@ -5229,19 +5169,16 @@ mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) { if (pc_is_mips16 (*pcptr)) { - static unsigned char mips16_little_breakpoint[] = - MIPS16_LITTLE_BREAKPOINT; + static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8}; *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); *lenptr = sizeof (mips16_little_breakpoint); return mips16_little_breakpoint; } else { - static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; - static unsigned char pmon_little_breakpoint[] = - PMON_LITTLE_BREAKPOINT; - static unsigned char idt_little_breakpoint[] = - IDT_LITTLE_BREAKPOINT; + static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0}; + static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0}; + static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0}; *lenptr = sizeof (little_breakpoint); @@ -5470,7 +5407,6 @@ mips_get_saved_register (char *raw_buffer, CORE_ADDR addrx; enum lval_type lvalx; int optimizedx; - int realnum; if (!target_has_registers) error ("No registers."); @@ -5482,8 +5418,8 @@ mips_get_saved_register (char *raw_buffer, lvalp = &lvalx; if (optimizedp == NULL) optimizedp = &optimizedx; - frame_register_unwind (get_next_frame (frame), regnum, optimizedp, lvalp, - addrp, &realnum, raw_buffer); + generic_unwind_get_saved_register (raw_buffer, optimizedp, addrp, frame, + regnum, lvalp); /* FIXME: cagney/2002-09-13: This is just so bad. The MIPS should have a pseudo register range that correspons to the ABI's, rather than the ISA's, view of registers. These registers would then @@ -5498,7 +5434,7 @@ mips_get_saved_register (char *raw_buffer, /* Only MIPS_SAVED_REGSIZE bytes of GP registers are saved. */ LONGEST val = read_memory_integer ((*addrp), MIPS_SAVED_REGSIZE); - store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); + store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), val); } } } @@ -5522,23 +5458,45 @@ mips_saved_pc_after_call (struct frame_info *frame) static int mips_stab_reg_to_regnum (int num) { - if (num < 32) + if (num >= 0 && num < 32) return num; - else + else if (num >= 38 && num < 70) return num + FP0_REGNUM - 38; + else if (num == 70) + return HI_REGNUM; + else if (num == 71) + return LO_REGNUM; + else + { + /* This will hopefully (eventually) provoke a warning. Should + we be calling complaint() here? */ + return NUM_REGS + NUM_PSEUDO_REGS; + } } -/* Convert a ecoff register number to a gdb REGNUM */ + +/* Convert a dwarf, dwarf2, or ecoff register number to a gdb REGNUM */ static int -mips_ecoff_reg_to_regnum (int num) +mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) { - if (num < 32) + if (num >= 0 && num < 32) return num; - else + else if (num >= 32 && num < 64) return num + FP0_REGNUM - 32; + else if (num == 64) + return HI_REGNUM; + else if (num == 65) + return LO_REGNUM; + else + { + /* This will hopefully (eventually) provoke a warning. Should + we be calling complaint() here? */ + return NUM_REGS + NUM_PSEUDO_REGS; + } } + /* Convert an integer into an address. By first converting the value into a pointer and then extracting it signed, the address is guarenteed to be correctly sign extended. */ @@ -5598,8 +5556,6 @@ static struct gdbarch * mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) { - static LONGEST mips_call_dummy_words[] = - {0}; struct gdbarch *gdbarch; struct gdbarch_tdep *tdep; int elf_flags; @@ -5607,9 +5563,9 @@ mips_gdbarch_init (struct gdbarch_info info, /* Reset the disassembly info, in case it was set to something non-default. */ - tm_print_insn_info.flavour = bfd_target_unknown_flavour; - tm_print_insn_info.arch = bfd_arch_unknown; - tm_print_insn_info.mach = 0; + deprecated_tm_print_insn_info.flavour = bfd_target_unknown_flavour; + deprecated_tm_print_insn_info.arch = bfd_arch_unknown; + deprecated_tm_print_insn_info.mach = 0; elf_flags = 0; @@ -5690,6 +5646,34 @@ mips_gdbarch_init (struct gdbarch_info info, if (wanted_abi != MIPS_ABI_UNKNOWN) mips_abi = wanted_abi; + /* We have to set deprecated_tm_print_insn_info before looking for a + pre-existing architecture, otherwise we may return before we get + a chance to set it up. */ + if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) + { + /* Set up the disassembler info, so that we get the right + register names from libopcodes. */ + if (mips_abi == MIPS_ABI_N32) + deprecated_tm_print_insn_info.disassembler_options = "gpr-names=n32"; + else + deprecated_tm_print_insn_info.disassembler_options = "gpr-names=64"; + deprecated_tm_print_insn_info.flavour = bfd_target_elf_flavour; + deprecated_tm_print_insn_info.arch = bfd_arch_mips; + if (info.bfd_arch_info != NULL + && info.bfd_arch_info->arch == bfd_arch_mips + && info.bfd_arch_info->mach) + deprecated_tm_print_insn_info.mach = info.bfd_arch_info->mach; + else + deprecated_tm_print_insn_info.mach = bfd_mach_mips8000; + } + else + /* This string is not recognized explicitly by the disassembler, + but it tells the disassembler to not try to guess the ABI from + the bfd elf headers, such that, if the user overrides the ABI + of a program linked as NewABI, the disassembly will follow the + register naming conventions specified by the user. */ + deprecated_tm_print_insn_info.disassembler_options = "gpr-names=32"; + if (gdbarch_debug) { fprintf_unfiltered (gdb_stdlog, @@ -5729,8 +5713,8 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_double_bit (gdbarch, 64); set_gdbarch_long_double_bit (gdbarch, 64); set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size); - set_gdbarch_max_register_raw_size (gdbarch, 8); - set_gdbarch_max_register_virtual_size (gdbarch, 8); + set_gdbarch_deprecated_max_register_raw_size (gdbarch, 8); + set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 8); tdep->found_abi = found_abi; tdep->mips_abi = mips_abi; @@ -5745,7 +5729,7 @@ mips_gdbarch_init (struct gdbarch_info info, switch (mips_abi) { case MIPS_ABI_O32: - set_gdbarch_push_arguments (gdbarch, mips_o32_push_arguments); + set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value); set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value); tdep->mips_default_saved_regsize = 4; @@ -5764,7 +5748,7 @@ mips_gdbarch_init (struct gdbarch_info info, mips_o32_use_struct_convention); break; case MIPS_ABI_O64: - set_gdbarch_push_arguments (gdbarch, mips_o64_push_arguments); + set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); tdep->mips_default_saved_regsize = 8; @@ -5783,7 +5767,7 @@ mips_gdbarch_init (struct gdbarch_info info, mips_o32_use_struct_convention); break; case MIPS_ABI_EABI32: - set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments); + set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); tdep->mips_default_saved_regsize = 4; @@ -5802,7 +5786,7 @@ mips_gdbarch_init (struct gdbarch_info info, mips_eabi_use_struct_convention); break; case MIPS_ABI_EABI64: - set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments); + set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); tdep->mips_default_saved_regsize = 8; @@ -5821,7 +5805,7 @@ mips_gdbarch_init (struct gdbarch_info info, mips_eabi_use_struct_convention); break; case MIPS_ABI_N32: - set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments); + set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); tdep->mips_default_saved_regsize = 8; @@ -5834,25 +5818,13 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_long_bit (gdbarch, 32); set_gdbarch_ptr_bit (gdbarch, 32); set_gdbarch_long_long_bit (gdbarch, 64); - - /* Set up the disassembler info, so that we get the right - register names from libopcodes. */ - tm_print_insn_info.flavour = bfd_target_elf_flavour; - tm_print_insn_info.arch = bfd_arch_mips; - if (info.bfd_arch_info != NULL - && info.bfd_arch_info->arch == bfd_arch_mips - && info.bfd_arch_info->mach) - tm_print_insn_info.mach = info.bfd_arch_info->mach; - else - tm_print_insn_info.mach = bfd_mach_mips8000; - set_gdbarch_use_struct_convention (gdbarch, mips_n32n64_use_struct_convention); set_gdbarch_reg_struct_has_addr (gdbarch, mips_n32n64_reg_struct_has_addr); break; case MIPS_ABI_N64: - set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments); + set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); tdep->mips_default_saved_regsize = 8; @@ -5865,18 +5837,6 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_long_bit (gdbarch, 64); set_gdbarch_ptr_bit (gdbarch, 64); set_gdbarch_long_long_bit (gdbarch, 64); - - /* Set up the disassembler info, so that we get the right - register names from libopcodes. */ - tm_print_insn_info.flavour = bfd_target_elf_flavour; - tm_print_insn_info.arch = bfd_arch_mips; - if (info.bfd_arch_info != NULL - && info.bfd_arch_info->arch == bfd_arch_mips - && info.bfd_arch_info->mach) - tm_print_insn_info.mach = info.bfd_arch_info->mach; - else - tm_print_insn_info.mach = bfd_mach_mips8000; - set_gdbarch_use_struct_convention (gdbarch, mips_n32n64_use_struct_convention); set_gdbarch_reg_struct_has_addr (gdbarch, @@ -5940,9 +5900,9 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_register_name (gdbarch, mips_register_name); set_gdbarch_read_pc (gdbarch, mips_read_pc); set_gdbarch_write_pc (gdbarch, generic_target_write_pc); - set_gdbarch_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ + set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ set_gdbarch_read_sp (gdbarch, mips_read_sp); - set_gdbarch_write_sp (gdbarch, generic_target_write_sp); + set_gdbarch_deprecated_dummy_write_sp (gdbarch, generic_target_write_sp); /* Add/remove bits from an address. The MIPS needs be careful to ensure that all 32 bit addresses are sign extended to 64 bits. */ @@ -5955,28 +5915,18 @@ mips_gdbarch_init (struct gdbarch_info info, /* Map debug register numbers onto internal register numbers. */ set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); - set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum); + set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); + set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); /* Initialize a frame */ - set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); - set_gdbarch_frame_init_saved_regs (gdbarch, mips_frame_init_saved_regs); + set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_frame_init_saved_regs); + set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); /* MIPS version of CALL_DUMMY */ - set_gdbarch_call_dummy_p (gdbarch, 1); - set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); - set_gdbarch_push_return_address (gdbarch, mips_push_return_address); - set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); - set_gdbarch_pop_frame (gdbarch, mips_pop_frame); - set_gdbarch_call_dummy_start_offset (gdbarch, 0); - set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); - set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); - set_gdbarch_call_dummy_length (gdbarch, 0); - set_gdbarch_fix_call_dummy (gdbarch, mips_fix_call_dummy); - set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); - set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); - set_gdbarch_push_return_address (gdbarch, mips_push_return_address); + set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame); set_gdbarch_frame_align (gdbarch, mips_frame_align); set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); set_gdbarch_register_convertible (gdbarch, mips_register_convertible); @@ -5985,21 +5935,21 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_register_convert_to_raw (gdbarch, mips_register_convert_to_raw); - set_gdbarch_frame_chain (gdbarch, mips_frame_chain); + set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain); set_gdbarch_frameless_function_invocation (gdbarch, generic_frameless_function_invocation_not); - set_gdbarch_frame_saved_pc (gdbarch, mips_frame_saved_pc); + set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc); set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); set_gdbarch_frame_args_skip (gdbarch, 0); - set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register); + set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register); set_gdbarch_inner_than (gdbarch, core_addr_lessthan); set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); set_gdbarch_decr_pc_after_break (gdbarch, 0); set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); - set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); + set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); @@ -6018,7 +5968,6 @@ mips_gdbarch_init (struct gdbarch_info info, /* Hook in OS ABI-specific overrides, if they have been registered. */ gdbarch_init_osabi (info, gdbarch); - set_gdbarch_store_struct_return (gdbarch, mips_store_struct_return); set_gdbarch_extract_struct_value_address (gdbarch, mips_extract_struct_value_address); @@ -6042,6 +5991,38 @@ mips_abi_update (char *ignore_args, int from_tty, gdbarch_update_p (info); } +/* Print out which MIPS ABI is in use. */ + +static void +show_mips_abi (char *ignore_args, int from_tty) +{ + if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) + printf_filtered ( + "The MIPS ABI is unknown because the current architecture is not MIPS.\n"); + else + { + enum mips_abi global_abi = global_mips_abi (); + enum mips_abi actual_abi = mips_abi (current_gdbarch); + const char *actual_abi_str = mips_abi_strings[actual_abi]; + + if (global_abi == MIPS_ABI_UNKNOWN) + printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n", + actual_abi_str); + else if (global_abi == actual_abi) + printf_filtered ( + "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", + actual_abi_str); + else + { + /* Probably shouldn't happen... */ + printf_filtered ( + "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", + actual_abi_str, + mips_abi_strings[global_abi]); + } + } +} + static void mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) { @@ -6140,8 +6121,6 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) fprintf_unfiltered (file, "mips_dump_tdep: BADVADDR_REGNUM = %d\n", BADVADDR_REGNUM); - fprintf_unfiltered (file, - "mips_dump_tdep: BIG_BREAKPOINT = delete?\n"); fprintf_unfiltered (file, "mips_dump_tdep: CAUSE_REGNUM = %d\n", CAUSE_REGNUM); @@ -6166,19 +6145,12 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) fprintf_unfiltered (file, "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", GDB_TARGET_IS_MIPS64); - fprintf_unfiltered (file, - "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n", - GEN_REG_SAVE_MASK); fprintf_unfiltered (file, "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n", XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT)); fprintf_unfiltered (file, "mips_dump_tdep: HI_REGNUM = %d\n", HI_REGNUM); - fprintf_unfiltered (file, - "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n"); - fprintf_unfiltered (file, - "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n"); fprintf_unfiltered (file, "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", XSTRING (IGNORE_HELPER_CALL (PC))); @@ -6193,8 +6165,6 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) fprintf_unfiltered (file, "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", LAST_EMBED_REGNUM); - fprintf_unfiltered (file, - "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n"); fprintf_unfiltered (file, "mips_dump_tdep: LO_REGNUM = %d\n", LO_REGNUM); @@ -6215,13 +6185,9 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) #endif fprintf_unfiltered (file, "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n"); - fprintf_unfiltered (file, - "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n"); fprintf_unfiltered (file, "mips_dump_tdep: MIPS16_INSTLEN = %d\n", MIPS16_INSTLEN); - fprintf_unfiltered (file, - "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n"); fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); fprintf_unfiltered (file, @@ -6245,10 +6211,6 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) "mips_dump_tdep: OP_LDFPR = used?\n"); fprintf_unfiltered (file, "mips_dump_tdep: OP_LDGPR = used?\n"); - fprintf_unfiltered (file, - "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n"); - fprintf_unfiltered (file, - "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n"); fprintf_unfiltered (file, "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); @@ -6282,9 +6244,6 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); - fprintf_unfiltered (file, - "mips_dump_tdep: PUSH_FP_REGNUM = %d\n", - PUSH_FP_REGNUM); fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM); @@ -6435,8 +6394,8 @@ _initialize_mips_tdep (void) internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); - if (!tm_print_insn) /* Someone may have already set it */ - tm_print_insn = gdb_print_insn_mips; + if (!deprecated_tm_print_insn) /* Someone may have already set it */ + deprecated_tm_print_insn = gdb_print_insn_mips; /* Add root prefix command for all "set mips"/"show mips" commands */ add_prefix_cmd ("mips", no_class, set_mips_command, @@ -6489,8 +6448,9 @@ This option can be set to one of:\n\ " eabi32\n" " eabi64", &setmipscmdlist); - add_show_from_set (c, &showmipscmdlist); set_cmd_sfunc (c, mips_abi_update); + add_cmd ("abi", class_obscure, show_mips_abi, + "Show ABI in use by MIPS target", &showmipscmdlist); /* Let the user turn off floating point and set the fence post for heuristic_proc_start. */