// -*- C -*-
//
+// In mips.igen, the semantics for many of the instructions were created
+// using code generated by gencode. Those semantic segments could be
+// greatly simplified.
+//
// <insn> ::=
// <insn-word> { "+" <insn-word> }
// ":" <format-name>
// Models known by this simulator
-:model:::mipsI:mipsI:
-:model:::mipsII:mipsII:
-:model:::mipsIII:mipsIII:
-:model:::mipsIV:mipsIV:
+:model:::mipsI:mips3000:
+:model:::mipsII:mips6000:
+:model:::mipsIII:mips4000:
+:model:::mipsIV:mips8000:
:model:::mips16:mips16:
-// start-sanitize-r5900
-:model:::r5900:mips5900:
-// end-sanitize-r5900
:model:::r3900:mips3900:
-// start-sanitize-tx19
-:model:::tx19:tx19:
-// end-sanitize-tx19
-// start-sanitize-vr5400
-:model:::vr5400:mips5400:
-:model:::mdmx:mdmx:
-// end-sanitize-vr5400
+:model:::vr4100:mips4100:
:model:::vr5000:mips5000:
+// Helper:
+//
+// Simulate a 32 bit delayslot instruction
+//
+
+:function:::address_word:delayslot32:address_word target
+{
+ instruction_word delay_insn;
+ sim_events_slip (SD, 1);
+ DSPC = CIA;
+ CIA = CIA + 4; /* NOTE not mips16 */
+ STATE |= simDELAYSLOT;
+ delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
+ idecode_issue (CPU_, delay_insn, (CIA));
+ STATE &= ~simDELAYSLOT;
+ return target;
+}
+
+:function:::address_word:nullify_next_insn32:
+{
+ sim_events_slip (SD, 1);
+ dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
+ return CIA + 8;
+}
+
+// Helper:
+//
+// Check that an access to a HI/LO register meets timing requirements
+//
+// The following requirements exist:
+//
+// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
+// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
+// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
+// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
+//
+
+:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
+{
+ if (history->mf.timestamp + 3 > time)
+ {
+ sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
+ itable[MY_INDEX].name,
+ new, (long) CIA,
+ (long) history->mf.cia);
+ return 0;
+ }
+ return 1;
+}
+
+:function:::int:check_mt_hilo:hilo_history *history
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*vr5000:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = check_mf_cycles (SD_, history, time, "MT");
+ history->mt.timestamp = time;
+ history->mt.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_mt_hilo:hilo_history *history
+*r3900:
+{
+ signed64 time = sim_events_time (SD);
+ history->mt.timestamp = time;
+ history->mt.cia = CIA;
+ return 1;
+}
+
+
+:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = 1;
+ if (peer != NULL
+ && peer->mt.timestamp > history->op.timestamp
+ && history->mt.timestamp < history->op.timestamp
+ && ! (history->mf.timestamp > history->op.timestamp
+ && history->mf.timestamp < peer->mt.timestamp)
+ && ! (peer->mf.timestamp > history->op.timestamp
+ && peer->mf.timestamp < peer->mt.timestamp))
+ {
+ /* The peer has been written to since the last OP yet we have
+ not */
+ sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
+ itable[MY_INDEX].name,
+ (long) CIA,
+ (long) history->op.cia,
+ (long) peer->mt.cia);
+ ok = 0;
+ }
+ history->mf.timestamp = time;
+ history->mf.cia = CIA;
+ return ok;
+}
+
+
+
+:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*vr5000:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP"));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
+// The r3900 mult and multu insns _can_ be exectuted immediatly after
+// a mf{hi,lo}
+:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*r3900:
+{
+ /* FIXME: could record the fact that a stall occured if we want */
+ signed64 time = sim_events_time (SD);
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return 1;
+}
+
+
+:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP"));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
+
+
+
+
//
// Mips Architecture:
//
//
+
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- ALU32_BEGIN (GPR[RS]);
- ALU32_ADD (GPR[RT]);
- ALU32_END (GPR[RD]);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ {
+ ALU32_BEGIN (GPR[RS]);
+ ALU32_ADD (GPR[RT]);
+ ALU32_END (GPR[RD]);
+ }
+ TRACE_ALU_RESULT (GPR[RD]);
}
+
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
"addi r<RT>, r<RS>, IMMEDIATE"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- ALU32_BEGIN (GPR[RS]);
- ALU32_ADD (EXTEND16 (IMMEDIATE));
- ALU32_END (GPR[RT]);
+ TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
+ {
+ ALU32_BEGIN (GPR[RS]);
+ ALU32_ADD (EXTEND16 (IMMEDIATE));
+ ALU32_END (GPR[RT]);
+ }
+ TRACE_ALU_RESULT (GPR[RT]);
}
+
+:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+ GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
-"add r<RT>, r<RS>, <IMMEDIATE>"
+"addiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
- GPR[RT] = EXTEND32 (temp);
+ do_addiu (SD_, RS, RT, IMMEDIATE);
}
+
+:function:::void:do_addu:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
+"addu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- signed32 temp = GPR[RS] + GPR[RT];
- GPR[RD] = EXTEND32 (temp);
+ do_addu (SD_, RS, RT, RD);
}
+
+:function:::void:do_and:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = GPR[rs] & GPR[rt];
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
"and r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = GPR[RS] & GPR[RT];
+ do_and (SD_, RS, RT, RD);
}
+
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
"and r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
+ TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
GPR[RT] = GPR[RS] & IMMEDIATE;
+ TRACE_ALU_RESULT (GPR[RT]);
}
+
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
"beq r<RS>, r<RT>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
"beql r<RS>, r<RT>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] >= 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
"bgezall r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
RA = (CIA + 8);
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] >= 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
"bgezl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
if ((signed_word) GPR[RS] > 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
"bgtzl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] > 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] <= 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
"bgezl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
if ((signed_word) GPR[RS] <= 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
if ((signed_word) GPR[RS] < 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
RA = (CIA + 8);
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] < 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
"bltzall r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] < 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
"bltzl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] < 0)
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
"bnel r<RS>, r<RT>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
- DELAY_SLOT (NIA + offset);
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000000,20.CODE,001101:SPECIAL:32::BREAK
"break"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- SignalException(BreakPoint, instruction_0);
+ /* Check for some break instruction which are reserved for use by the simulator. */
+ unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
+ if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
+ break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
+ {
+ sim_engine_halt (SD, CPU, NULL, cia,
+ sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
+ }
+ else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
+ break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
+ {
+ if (STATE & simDELAYSLOT)
+ PC = cia - 4; /* reference the branch instruction */
+ else
+ PC = cia;
+ SignalException(BreakPoint, instruction_0);
+ }
+
+ else
+ {
+ /* If we get this far, we're not an instruction reserved by the sim. Raise
+ the exception. */
+ SignalException(BreakPoint, instruction_0);
+ }
}
-0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
-"cop<ZZ> <COP_FUN>"
-*mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
- DecodeCoproc (instruction_0);
-}
+
+
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
"dadd r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
/* this check's for overflow */
- ALU64_BEGIN (GPR[RS]);
- ALU64_ADD (GPR[RT]);
- ALU64_END (GPR[RD]);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ {
+ ALU64_BEGIN (GPR[RS]);
+ ALU64_ADD (GPR[RT]);
+ ALU64_END (GPR[RD]);
+ }
+ TRACE_ALU_RESULT (GPR[RD]);
}
+
011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
"daddi r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- ALU64_BEGIN (GPR[RS]);
- ALU64_ADD (EXTEND16 (IMMEDIATE));
- ALU64_END (GPR[RT]);
+ TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
+ {
+ ALU64_BEGIN (GPR[RS]);
+ ALU64_ADD (EXTEND16 (IMMEDIATE));
+ ALU64_END (GPR[RT]);
+ }
+ TRACE_ALU_RESULT (GPR[RT]);
}
+
+:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+ GPR[rt] = GPR[rs] + EXTEND16 (immediate);
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
"daddu r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
+ do_daddiu (SD_, RS, RT, IMMEDIATE);
}
+
+:function:::void:do_daddu:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = GPR[rs] + GPR[rt];
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
"daddu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = GPR[RS] + GPR[RT];
+ do_daddu (SD_, RS, RT, RD);
}
-000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
-"ddiv r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+
+:function:::void:do_ddiv:int rs, int rt
{
- CHECKHILO ("Division");
+ check_div_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- signed64 n = GPR[RS];
- signed64 d = GPR[RT];
+ signed64 n = GPR[rs];
+ signed64 d = GPR[rt];
+ signed64 hi;
+ signed64 lo;
if (d == 0)
{
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
+ lo = SIGNED64 (0x8000000000000000);
+ hi = 0;
}
else if (d == -1 && n == SIGNED64 (0x8000000000000000))
{
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
+ lo = SIGNED64 (0x8000000000000000);
+ hi = 0;
}
else
{
- LO = (n / d);
- HI = (n % d);
+ lo = (n / d);
+ hi = (n % d);
}
+ HI = hi;
+ LO = lo;
}
+ TRACE_ALU_RESULT2 (HI, LO);
}
-
-
-000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
-"ddivu r<RS>, r<RT>"
+000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
+"ddiv r<RS>, r<RT>"
*mipsIII:
*mipsIV:
-*r3900:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- CHECKHILO ("Division");
+ do_ddiv (SD_, RS, RT);
+}
+
+
+
+:function:::void:do_ddivu:int rs, int rt
+{
+ check_div_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- unsigned64 n = GPR[RS];
- unsigned64 d = GPR[RT];
+ unsigned64 n = GPR[rs];
+ unsigned64 d = GPR[rt];
+ unsigned64 hi;
+ unsigned64 lo;
if (d == 0)
{
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
+ lo = SIGNED64 (0x8000000000000000);
+ hi = 0;
}
else
{
- LO = (n / d);
- HI = (n % d);
+ lo = (n / d);
+ hi = (n % d);
}
+ HI = hi;
+ LO = lo;
}
+ TRACE_ALU_RESULT2 (HI, LO);
}
-
-000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
-"div r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
+"ddivu r<RS>, r<RT>"
+*mipsIII:
+*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- CHECKHILO("Division");
+ do_ddivu (SD_, RS, RT);
+}
+
+
+
+:function:::void:do_div:int rs, int rt
+{
+ check_div_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- signed32 n = GPR[RS];
- signed32 d = GPR[RT];
+ signed32 n = GPR[rs];
+ signed32 d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (n % d);
}
}
+ TRACE_ALU_RESULT2 (HI, LO);
}
-
-000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
-"divu r<RS>, r<RT>"
+000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
+"div r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- CHECKHILO ("Division");
+ do_div (SD_, RS, RT);
+}
+
+
+
+:function:::void:do_divu:int rs, int rt
+{
+ check_div_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- unsigned32 n = GPR[RS];
- unsigned32 d = GPR[RT];
+ unsigned32 n = GPR[rs];
+ unsigned32 d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (n % d);
}
}
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
+"divu r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ do_divu (SD_, RS, RT);
}
-:function:::void:do_dmult:int rs, int rt, int rd, int signed_p
+
+:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
{
unsigned64 lo;
unsigned64 hi;
int sign;
unsigned64 op1 = GPR[rs];
unsigned64 op2 = GPR[rt];
- CHECKHILO ("Multiplication");
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
/* make signed multiply unsigned */
sign = 0;
if (signed_p)
HI = hi;
if (rd != 0)
GPR[rd] = lo;
+ TRACE_ALU_RESULT2 (HI, LO);
}
+:function:::void:do_dmult:int rs, int rt, int rd
+{
+ do_dmultx (SD_, rs, rt, rd, 1);
+}
000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
*mipsIII,mipsIV:
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*vr4100:
{
- do_dmult (SD_, RS, RT, 0, 1);
+ do_dmult (SD_, RS, RT, 0);
}
000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>":RD == 0
"dmult r<RD>, r<RS>, r<RT>"
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
- do_dmult (SD_, RS, RT, RD, 1);
+ do_dmult (SD_, RS, RT, RD);
}
+:function:::void:do_dmultu:int rs, int rt, int rd
+{
+ do_dmultx (SD_, rs, rt, rd, 0);
+}
+
000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
*mipsIII,mipsIV:
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*vr4100:
{
- do_dmult (SD_, RS, RT, 0, 0);
+ do_dmultu (SD_, RS, RT, 0);
}
000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
"dmultu r<RD>, r<RS>, r<RT>":RD == 0
"dmultu r<RS>, r<RT>"
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
- do_dmult (SD_, RS, RT, RD, 0);
+ do_dmultu (SD_, RS, RT, RD);
+}
+
+:function:::void:do_dsll:int rt, int rd, int shift
+{
+ GPR[rd] = GPR[rt] << shift;
}
+:function:::void:do_dsllv:int rs, int rt, int rd
+{
+ int s = MASKED64 (GPR[rs], 5, 0);
+ GPR[rd] = GPR[rt] << s;
+}
00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = SHIFT;
- GPR[RD] = GPR[RT] << s;
+ do_dsll (SD_, RT, RD, SHIFT);
}
"dsll32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
int s = 32 + SHIFT;
GPR[RD] = GPR[RT] << s;
}
-
000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = MASKED64 (GPR[RS], 5, 0);
- GPR[RD] = GPR[RT] << s;
+ do_dsllv (SD_, RS, RT, RD);
+}
+
+:function:::void:do_dsra:int rt, int rd, int shift
+{
+ GPR[rd] = ((signed64) GPR[rt]) >> shift;
}
"dsra r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = SHIFT;
- GPR[RD] = ((signed64) GPR[RT]) >> s;
+ do_dsra (SD_, RT, RD, SHIFT);
}
"dsra32 r<RT>, r<RD>, <SHIFT>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
int s = 32 + SHIFT;
GPR[RD] = ((signed64) GPR[RT]) >> s;
}
+:function:::void:do_dsrav:int rs, int rt, int rd
+{
+ int s = MASKED64 (GPR[rs], 5, 0);
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = ((signed64) GPR[rt]) >> s;
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
"dsra32 r<RT>, r<RD>, r<RS>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = MASKED64 (GPR[RS], 5, 0);
- GPR[RD] = ((signed64) GPR[RT]) >> s;
+ do_dsrav (SD_, RS, RT, RD);
+}
+
+:function:::void:do_dsrl:int rt, int rd, int shift
+{
+ GPR[rd] = (unsigned64) GPR[rt] >> shift;
}
00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
-"dsrav r<RD>, r<RT>, <SHIFT>"
+"dsrl r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = SHIFT;
- GPR[RD] = (unsigned64) GPR[RT] >> s;
+ do_dsrl (SD_, RT, RD, SHIFT);
}
"dsrl32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
int s = 32 + SHIFT;
GPR[RD] = (unsigned64) GPR[RT] >> s;
}
+:function:::void:do_dsrlv:int rs, int rt, int rd
+{
+ int s = MASKED64 (GPR[rs], 5, 0);
+ GPR[rd] = (unsigned64) GPR[rt] >> s;
+}
+
+
+
000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
"dsrl32 r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = MASKED64 (GPR[RS], 5, 0);
- GPR[RD] = (unsigned64) GPR[RT] >> s;
+ do_dsrlv (SD_, RS, RT, RD);
}
"dsub r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- ALU64_BEGIN (GPR[RS]);
- ALU64_SUB (GPR[RT]);
- ALU64_END (GPR[RD]);
-}
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ {
+ ALU64_BEGIN (GPR[RS]);
+ ALU64_SUB (GPR[RT]);
+ ALU64_END (GPR[RD]);
+ }
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+:function:::void:do_dsubu:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = GPR[rs] - GPR[rt];
+ TRACE_ALU_RESULT (GPR[rd]);
+}
000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
"dsubu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = GPR[RS] - GPR[RT];
+ do_dsubu (SD_, RS, RT, RD);
}
000010,26.INSTR_INDEX:NORMAL:32::J
"j <INSTR_INDEX>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
/* NOTE: The region used is that of the delay slot NIA and NOT the
current instruction */
000011,26.INSTR_INDEX:NORMAL:32::JAL
"jal <INSTR_INDEX>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
/* NOTE: The region used is that of the delay slot and NOT the
current instruction */
DELAY_SLOT (region | (INSTR_INDEX << 2));
}
-
000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word temp = GPR[RS];
GPR[RD] = CIA + 8;
000000,5.RS,000000000000000001000:SPECIAL:32::JR
"jr r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
DELAY_SLOT (GPR[RS]);
}
-:function:::void:do_load_byte:address_word gpr_base, int rt, signed16 offset
+:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
{
- address_word vaddr = offset + gpr_base;
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
+ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
+ unsigned int byte;
address_word paddr;
int uncached;
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ if ((vaddr & access) != 0)
{
- unsigned64 memval = 0;
- address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- LoadMemory (&memval, NULL, uncached, AccessLength_BYTE, paddr, vaddr, isDATA, isREAL);
- byte = ((vaddr & mask) ^ bigend);
- GPR[rt] = EXTEND8 ((memval >> (8 * byte)));
+ SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
}
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ return (memval >> (8 * byte));
}
+
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- do_load_byte (SD_, GPR[BASE], RT, OFFSET);
-#if 0
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((uword64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- uword64 memval = 0;
- uword64 memval1 = 0;
- uword64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
- }
- }
- }
-#endif
+ GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
}
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
"lbu r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
- }
- }
- }
+ GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
}
"ld r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = memval;
- }
- }
- }
+ GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
- }
- }
- }
+ COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
+
+
011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
"ldl r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
- }
- }
- }
+ GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
"ldr r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
- {
- unsigned64 srcmask;
- if (byte == 0)
- srcmask = 0;
- else
- srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
- GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
- }
- }
- }
- }
+ GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
"lh r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
- }
- }
- }
+ GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
"lhu r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
- }
- }
- }
+ GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
}
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
"lld r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
address_word paddr;
int uncached;
if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
"lui r<RT>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
+ TRACE_ALU_INPUT1 (IMMEDIATE);
GPR[RT] = EXTEND32 (IMMEDIATE << 16);
+ TRACE_ALU_RESULT (GPR[RT]);
}
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
"lw r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
- }
- }
- }
+ GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
+}
+
+
+:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ unsigned int word;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+ int nr_lhs_bits;
+ int nr_rhs_bits;
+ unsigned_word lhs_mask;
+ unsigned_word temp;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem == 0)
+ paddr = paddr & ~access;
+
+ /* compute where within the word/mem we are */
+ byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
+ word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
+ nr_lhs_bits = 8 * byte + 8;
+ nr_rhs_bits = 8 * access - 8 * byte;
+ /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
+
+ /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
+ (long) ((unsigned64) vaddr >> 32), (long) vaddr,
+ (long) ((unsigned64) paddr >> 32), (long) paddr,
+ word, byte, nr_lhs_bits, nr_rhs_bits); */
+
+ LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
+ if (word == 0)
+ {
+ /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
+ temp = (memval << nr_rhs_bits);
+ }
+ else
+ {
+ /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
+ temp = (memval >> nr_lhs_bits);
+ }
+ lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
+ rt = (rt & ~lhs_mask) | (temp & lhs_mask);
+
+ /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
+ (long) ((unsigned64) memval >> 32), (long) memval,
+ (long) ((unsigned64) temp >> 32), (long) temp,
+ (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
+ (long) (rt >> 32), (long) rt); */
+ return rt;
}
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
"lwl r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
+}
+
+
+:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem != 0)
+ paddr = paddr & ~access;
+ byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+ /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
+ LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
+ /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
+ (long) paddr, byte, (long) paddr, (long) memval); */
{
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
- memval >>= 32;
- }
- GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
- }
+ unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
+ rt &= ~screen;
+ rt |= (memval >> (8 * byte)) & screen;
}
+ return rt;
}
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
"lwr r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
- memval >>= 32;
- }
- {
- unsigned64 srcmask;
- if (byte == 0)
- srcmask = 0;
- else
- srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
- GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
- }
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
- }
- }
+ GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
}
"lwu r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
}
+:function:::void:do_mfhi:int rd
+{
+ check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT1 (HI);
+ GPR[rd] = HI;
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = HI;
-#if 0
- HIACCESS = 3;
-#endif
+ do_mfhi (SD_, RD);
}
+
+:function:::void:do_mflo:int rd
+{
+ check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
+ TRACE_ALU_INPUT1 (LO);
+ GPR[rd] = LO;
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = LO;
-#if 0
- LOACCESS = 3; /* 3rd instruction will be safe */
-#endif
+ do_mflo (SD_, RD);
}
+
000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
if (GPR[RT] != 0)
GPR[RD] = GPR[RS];
}
+
000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
if (GPR[RT] == 0)
GPR[RD] = GPR[RS];
}
+
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-#if 0
- if (HIACCESS != 0)
- sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
-#endif
+{
+ check_mt_hilo (SD_, HIHISTORY);
HI = GPR[RS];
-#if 0
- HIACCESS = 3; /* 3rd instruction will be safe */
-#endif
}
+
000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
"mtlo r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-#if 0
- if (LOACCESS != 0)
- sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
-#endif
+{
+ check_mt_hilo (SD_, LOHISTORY);
LO = GPR[RS];
-#if 0
- LOACCESS = 3; /* 3rd instruction will be safe */
-#endif
}
-000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
-"mult r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+
+:function:::void:do_mult:int rs, int rt, int rd
{
signed64 prod;
- CHECKHILO ("Multiplication");
- prod = (((signed64)(signed32) GPR[RS])
- * ((signed64)(signed32) GPR[RT]));
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = (((signed64)(signed32) GPR[rs])
+ * ((signed64)(signed32) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
+ if (rd != 0)
+ GPR[rd] = LO;
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
+"mult r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+{
+ do_mult (SD_, RS, RT, 0);
}
+
+
000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
"mult r<RD>, r<RS>, r<RT>"
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- signed64 prod;
- CHECKHILO ("Multiplication");
- prod = (((signed64)(signed32) GPR[RS])
- * ((signed64)(signed32) GPR[RT]));
+ do_mult (SD_, RS, RT, RD);
+}
+
+
+:function:::void:do_multu:int rs, int rt, int rd
+{
+ unsigned64 prod;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = (((unsigned64)(unsigned32) GPR[rs])
+ * ((unsigned64)(unsigned32) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
- if (RD != 0)
- GPR[RD] = LO;
+ if (rd != 0)
+ GPR[rd] = LO;
+ TRACE_ALU_RESULT2 (HI, LO);
}
-
000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
{
- unsigned64 prod;
- CHECKHILO ("Multiplication");
- prod = (((unsigned64)(unsigned32) GPR[RS])
- * ((unsigned64)(unsigned32) GPR[RT]));
- LO = EXTEND32 (VL4_8 (prod));
- HI = EXTEND32 (VH4_8 (prod));
+ do_multu (SD_, RS, RT, 0);
}
+
000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
"multu r<RD>, r<RS>, r<RT>"
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned64 prod;
- CHECKHILO ("Multiplication");
- prod = (((unsigned64)(unsigned32) GPR[RS])
- * ((unsigned64)(unsigned32) GPR[RT]));
- LO = EXTEND32 (VL4_8 (prod));
- HI = EXTEND32 (VH4_8 (prod));
- if (RD != 0)
- GPR[RD] = LO;
+ do_multu (SD_, RS, RT, 0);
}
+:function:::void:do_nor:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = ~ (GPR[rs] | GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
"nor r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = ~ (GPR[RS] | GPR[RT]);
+ do_nor (SD_, RS, RT, RD);
}
+:function:::void:do_or:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = (GPR[rs] | GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
"or r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = (GPR[RS] | GPR[RT]);
+ do_or (SD_, RS, RT, RD);
}
+
+:function:::void:do_ori:int rs, int rt, unsigned immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], immediate);
+ GPR[rt] = (GPR[rs] | immediate);
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
"ori r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RT] = (GPR[RS] | IMMEDIATE);
+ do_ori (SD_, RS, RT, IMMEDIATE);
}
110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
}
}
+:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
+ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ if ((vaddr & access) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
+ }
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ memval = (word << (8 * byte));
+ StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
+}
+
+
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
"sb r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- byte = ((vaddr & mask) ^ (bigend << shift));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
"scd r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
address_word paddr;
int uncached;
if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
"sd r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = op2;
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
}
"sdl r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- memval = (op2 >> (8 * (7 - byte)));
- StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
+ do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
"sdr r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- address_word paddr;
- int uncached;
- unsigned64 memval;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
- AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- if (BigEndianMem)
- paddr &= ~mask;
- byte = ((vaddr & mask) ^ bigend);
- memval = (GPR[RT] << (byte * 8));
- StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,0,paddr,vaddr,isREAL);
+ do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
"sh r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- byte = ((vaddr & mask) ^ (bigend << shift));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
+:function:::void:do_sll:int rt, int rd, int shift
+{
+ unsigned32 temp = (GPR[rt] << shift);
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"sll r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = SHIFT;
- unsigned32 temp = (GPR[RT] << s);
- GPR[RD] = EXTEND32 (temp);
+ do_sll (SD_, RT, RD, SHIFT);
}
+:function:::void:do_sllv:int rs, int rt, int rd
+{
+ int s = MASKED (GPR[rs], 4, 0);
+ unsigned32 temp = (GPR[rt] << s);
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = MASKED (GPR[RS], 4, 0);
- unsigned32 temp = (GPR[RT] << s);
- GPR[RD] = EXTEND32 (temp);
+ do_sllv (SD_, RS, RT, RD);
}
+:function:::void:do_slt:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
+ do_slt (SD_, RS, RT, RD);
}
+:function:::void:do_slti:int rs, int rt, unsigned16 immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+ GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
"slti r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
+ do_slti (SD_, RS, RT, IMMEDIATE);
}
+:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+ GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
+ do_sltiu (SD_, RS, RT, IMMEDIATE);
+}
+
+
+
+:function:::void:do_sltu:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
+ do_sltu (SD_, RS, RT, RD);
}
+:function:::void:do_sra:int rt, int rd, int shift
+{
+ signed32 temp = (signed32) GPR[rt] >> shift;
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
"sra r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = SHIFT;
- signed32 temp = (signed32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_sra (SD_, RT, RD, SHIFT);
}
+
+:function:::void:do_srav:int rs, int rt, int rd
+{
+ int s = MASKED (GPR[rs], 4, 0);
+ signed32 temp = (signed32) GPR[rt] >> s;
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = MASKED (GPR[RS], 4, 0);
- signed32 temp = (signed32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_srav (SD_, RS, RT, RD);
}
+
+:function:::void:do_srl:int rt, int rd, int shift
+{
+ unsigned32 temp = (unsigned32) GPR[rt] >> shift;
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
"srl r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = SHIFT;
- unsigned32 temp = (unsigned32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_srl (SD_, RT, RD, SHIFT);
}
+:function:::void:do_srlv:int rs, int rt, int rd
+{
+ int s = MASKED (GPR[rs], 4, 0);
+ unsigned32 temp = (unsigned32) GPR[rt] >> s;
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = MASKED (GPR[RS], 4, 0);
- unsigned32 temp = (unsigned32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_srlv (SD_, RS, RT, RD);
}
000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- ALU32_BEGIN (GPR[RS]);
- ALU32_SUB (GPR[RT]);
- ALU32_END (GPR[RD]);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ {
+ ALU32_BEGIN (GPR[RS]);
+ ALU32_SUB (GPR[RT]);
+ ALU32_END (GPR[RD]);
+ }
+ TRACE_ALU_RESULT (GPR[RD]);
}
+:function:::void:do_subu:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
+ do_subu (SD_, RS, RT, RD);
}
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
"sw r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
-*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*vr4100:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
+}
+
+
+
+:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ unsigned int word;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+ int nr_lhs_bits;
+ int nr_rhs_bits;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem == 0)
+ paddr = paddr & ~access;
+
+ /* compute where within the word/mem we are */
+ byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
+ word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
+ nr_lhs_bits = 8 * byte + 8;
+ nr_rhs_bits = 8 * access - 8 * byte;
+ /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
+ /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
+ (long) ((unsigned64) vaddr >> 32), (long) vaddr,
+ (long) ((unsigned64) paddr >> 32), (long) paddr,
+ word, byte, nr_lhs_bits, nr_rhs_bits); */
+
+ if (word == 0)
+ {
+ memval = (rt >> nr_rhs_bits);
+ }
+ else
+ {
+ memval = (rt << nr_lhs_bits);
+ }
+ /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
+ (long) ((unsigned64) rt >> 32), (long) rt,
+ (long) ((unsigned64) memval >> 32), (long) memval); */
+ StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
}
101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
"swl r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- memval = (op2 >> (8 * (3 - byte)));
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
- memval <<= 32;
- }
- StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
+ do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
+:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem != 0)
+ paddr &= ~access;
+ byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+ memval = (rt << (byte * 8));
+ StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
+}
+
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
"swr r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
- unsigned64 memval = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- address_word paddr;
- int uncached;
- address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
- AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- if (BigEndianMem)
- paddr &= ~mask;
- byte = ((vaddr & mask) ^ bigend);
- memval = (GPR[RT] << (byte * 8));
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2))
- memval <<= 32;
- StoreMemory(uncached,(AccessLength_WORD - byte),memval,0,paddr,vaddr,isREAL);
+{
+ do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
SyncOperation (STYPE);
}
000000,20.CODE,001100:SPECIAL:32::SYSCALL
"syscall <CODE>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
SignalException(SystemCall, instruction_0);
}
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
}
+:function:::void:do_xor:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = GPR[rs] ^ GPR[rt];
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = GPR[RS] ^ GPR[RT];
+ do_xor (SD_, RS, RT, RD);
}
+:function:::void:do_xori:int rs, int rt, unsigned16 immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], immediate);
+ GPR[rt] = GPR[rs] ^ immediate;
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
"xori r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RT] = GPR[RS] ^ IMMEDIATE;
+ do_xori (SD_, RS, RT, IMMEDIATE);
}
\f
010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
"abs.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
// BC1T
// BC1TL
-010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
+010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
"bc1%s<TF>%s<ND> <OFFSET>"
*mipsI,mipsII,mipsIII:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
+ check_branch_bug ();
TRACE_BRANCH_INPUT (PREVCOC1());
if (PREVCOC1() == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
TRACE_BRANCH_RESULT (dest);
+ mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
}
}
-010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
+010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+#*vr4100:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
+ check_branch_bug ();
if (GETFCC(CC) == TF)
{
- DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
+ address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
+ mark_branch_bug (dest);
+ DELAY_SLOT (dest);
}
else if (ND)
{
+
+
+
// C.EQ.S
// C.EQ.D
// ...
}
}
-010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
+010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
+"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
*mipsI,mipsII,mipsIII:
-"c.%s<COND>.%s<FMT> f<FS>, f<FT>":
{
do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
}
-010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
+010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
}
"ceil.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
// CFC1
// CTC1
-010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
+010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
"c%s<X>c1 r<RT>, f<FS>"
*mipsI:
*mipsII:
/* else NOP */
}
}
-010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
+010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
"c%s<X>c1 r<RT>, f<FS>"
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if (X)
{
010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
"cvt.d.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"cvt.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
"cvt.s.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
"cvt.w.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
// DMFC1
// DMTC1
-010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
+010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
"dm%s<X>c1 r<RT>, f<FS>"
*mipsIII:
{
PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
}
}
-010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
+010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
"dm%s<X>c1 r<RT>, f<FS>"
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
if (X)
{
"floor.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- unsigned64 memval;
- AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
- LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
- }
+ COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + op2);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- COP_LD(1,destreg,memval);;
- }
- }
- }
+ COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
}
110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = EXTEND16 (OFFSET);
- int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
- signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((uword64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- uword64 memval = 0;
- uword64 memval1 = 0;
- uword64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte UNUSED;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + op2);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
}
"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
// MFC1
// MTC1
-010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
+010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
"m%s<X>c1 r<RT>, f<FS>"
*mipsI:
*mipsII:
else /*MFC1*/
PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
}
-010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
+010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
"m%s<X>c1 r<RT>, f<FS>"
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
+ int fs = FS;
if (X)
/*MTC1*/
StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
"mov.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"mov%s<TF> r<RD>, r<RS>, <CC>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
if (GETFCC(CC) == TF)
GPR[RD] = GPR[RS];
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
unsigned32 instruction = instruction_0;
int format = ((instruction >> 21) & 0x00000007);
010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
"neg.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
*mipsIV:
"recip.%s<FMT> f<FD>, f<FS>"
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"round.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsIV:
"rsqrt.%s<FMT> f<FD>, f<FS>"
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- address_word paddr;
- unsigned64 memval;
- AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
- memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
- }
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
}
-
-010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
+010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
+"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
- unsigned32 instruction = instruction_0;
- int fs = ((instruction >> 11) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + op2);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = (unsigned64)COP_SD(1,fs);
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
}
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
"swc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
signed_word offset = EXTEND16 (OFFSET);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
{
uword64 memval = 0;
uword64 memval1 = 0;
- uword64 mask = 0x7;
+ uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
+ address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
+ StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
}
}
}
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
"trunc.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+
+010000,01000,00000,16.OFFSET:COP0:32::BC0F
+"bc0f <OFFSET>"
+// stub needed for eCos as tx39 hardware bug workaround
+*r3900:
+{
+ /* do nothing */
+}
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
"bc0fl <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
010000,01000,00001,16.OFFSET:COP0:32::BC0T
"bc0t <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-
+*vr4100:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
"bc0tl <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
010000,10000,000000000000000,111001:COP0:32::DI
"di"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
010000,10000,000000000000000,111000:COP0:32::EI
"ei"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
010000,10000,000000000000000,011000:COP0:32::ERET
"eret"
*mipsIII:
*mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+{
+ if (SR & status_ERL)
+ {
+ /* Oops, not yet available */
+ sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
+ NIA = EPC;
+ SR &= ~status_ERL;
+ }
+ else
+ {
+ NIA = EPC;
+ SR &= ~status_EXL;
+ }
+}
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
"mfc0 r<RT>, r<RD> # <REGX>"
*mipsI,mipsII,mipsIII,mipsIV:
+*r3900:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
+ TRACE_ALU_INPUT0 ();
DecodeCoproc (instruction_0);
+ TRACE_ALU_RESULT (GPR[RT]);
}
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
"mtc0 r<RT>, r<RD> # <REGX>"
*mipsI,mipsII,mipsIII,mipsIV:
+*r3900:
+*vr4100:
+*vr5000:
+{
+ DecodeCoproc (instruction_0);
+}
+
+
+010000,10000,000000000000000,010000:COP0:32::RFE
+"rfe"
+*mipsI,mipsII,mipsIII,mipsIV:
+*r3900:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
{
DecodeCoproc (instruction_0);
}
+0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
+"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*r3900:
+{
+ DecodeCoproc (instruction_0);
+}
+
+
+
010000,10000,000000000000000,001000:COP0:32::TLBP
"tlbp"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
010000,10000,000000000000000,000001:COP0:32::TLBR
"tlbr"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
010000,10000,000000000000000,000010:COP0:32::TLBWI
"tlbwi"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
010000,10000,000000000000000,000110:COP0:32::TLBWR
"tlbwr"
*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
\f
-:include:16::m16.igen
-// start-sanitize-vr5400
-:include::vr5400:vr5400.igen
-:include:64,f::mdmx.igen
-// end-sanitize-vr5400
-// start-sanitize-r5900
-:include::r5900:r5900.igen
-// end-sanitize-r5900
+:include:::m16.igen
+:include:::tx.igen
+:include:::vr.igen
\f
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME What is this instruction?
-// 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
-// *mipsI:
-// *mipsII:
-// *mipsIII:
-// *mipsIV:
-// // start-sanitize-r5900
-// *r5900:
-// // end-sanitize-r5900
-// *r3900:
-// // start-sanitize-tx19
-// *tx19:
-// // end-sanitize-tx19
-// {
-// unsigned32 instruction = instruction_0;
-// signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-// {
-// if (CoProcPresent(3))
-// SignalException(CoProcessorUnusable);
-// else
-// SignalException(ReservedInstruction,instruction);
-// }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME What is this?
-// 11100,******,00001:RR:16::SDBBP
-// *mips16:
-// {
-// unsigned32 instruction = instruction_0;
-// if (have_extendval)
-// SignalException (ReservedInstruction, instruction);
-// {
-// SignalException(DebugBreakPoint,instruction);
-// }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME What is this?
-// 000000,********************,001110:SPECIAL:32::SDBBP
-// *r3900:
-// {
-// unsigned32 instruction = instruction_0;
-// {
-// SignalException(DebugBreakPoint,instruction);
-// }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
-// // isn't yet reconized by this simulator.
-// 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
-// *vr4100:
-// {
-// unsigned32 instruction = instruction_0;
-// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-// {
-// CHECKHILO("Multiply-Add");
-// {
-// unsigned64 temp = (op1 * op2);
-// temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
-// LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
-// HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
-// }
-// }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
-// // isn't yet reconized by this simulator.
-// 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
-// *vr4100:
-// {
-// unsigned32 instruction = instruction_0;
-// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-// {
-// CHECKHILO("Multiply-Add");
-// {
-// unsigned64 temp = (op1 * op2);
-// LO = LO + temp;
-// }
-// }
-// }
-
-// end-sanitize-cygnus-never
projects / binutils.git / blobdiff