+start-sanitize-am33
+
+ * m10300-dis.c (disassemble): When printing RREGs and XRREGs, map
+ from raw register #s to symbolic names to make debugging easier.
+
+end-sanitize-am33
+
+ * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define.
+
+
+ * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
+start-sanitize-cygnus
+ * Makefile.am (CGENDIR): Set via configure.
+ (CGEN): New variable.
+ (CGENFILES): object.scm renamed to cos.scm.
+ (run-cgen): Renamed from cgen. stamp file renamed to stamp-$prefix.
+ (stamp-m32r): Pass prefix to run-cgen.
+ * Makefile.in: Regenerate.
+ * cgen-dis.in: Ditto.
+ * cgen-opc.in: Ditto.
+ * cgen.sh: New args cgen,prefix. Delete args scheme,schemeflags.
+ * configure.in: AC_SUBST cgen,cgendir. No longer look for guile.
+ * configure: Regenerate.
+end-sanitize-cygnus
+
+start-sanitize-am33
+
+ * m10300-opc.c: Reorder "movbu" and "movhu" instructions too.
+
+
+ * m10300-opc.c: Reorder more instructions so that we do not
+ accidentally match a mn10300 instruction when we really
+ wanted an am33 instruction.
+
+end-sanitize-am33
+
+ * m10300-dis.c: Only recognize instructions from the currently
+ selected machine.
+ * m10300-opc.c: Add field indicating the particular variant of
+ the mn10300 each instruction is available on.
+
+
+ * configure.in: For bfd_vax_arch, build vax-dis.lo.
+ * Makefile.am: Rebuild dependencies.
+ (CFILES): Add vax-dis.c.
+ (ALL_MACHINES): Add vax-dis.lo.
+ * aclocal.m4: Rebuild with current libtool.
+ * configure, Makefile.in: Rebuild.
+
+
+ * vax-dis.c: New file, from work by Pauline Middelink
+ * disassemble.c (ARCH_vax): Define if ARCH_all.
+ (disassembler): Add case for ARCH_vax.
+ * makefile.vms: Support compilation on vms/vax.
+
+start-sanitize-sky
+
+ * dvp-opc.c (DVP_OPERAND_RELOC_11_S4): Temporarily back out
+ the DVP_OPERAND_RELOC_11_S4 relocation.
+
+end-sanitize-sky
+start-sanitize-am33
+
+ * m10300-dis.c (print_insn_mn10300): 0xf7 opcode prefix specifies
+ 4 byte instructions.
+ (disassemble): Correctly handle FMT_D10 instructions.
+
+ * m10300-opc.c (mn10300_opcodes): Fix typo in IMM24 versions of the
+ am33 shift instructions.
+
+ * m10300-dis.c (print_insn_mn10300): 0xf9 opcode prefix specifies
+ 3 byte instructions.
+ (disassemble): Handle new instruction formats FMT_D6, FMT_D7, FMT_D8
+ FMT_D9 and FMT_D10. Handle various new opcode flags for the am33.
+
+ * m10300-opc.c (IMM32_HIGH8_MEM): New operand type.
+ (mn10300_opcodes): Reorder so as to try and select opcodes from
+ the core chip when multiple alternatives exist. Change several
+ am33 instructions to use IMM32_HIGH8_MEM. Fix typos in "mac" and
+ "macbu" instructions. Fix typos in a couple DSP instructions too.
+
+end-sanitize-am33
+
+ * m10200-dis.c (print_insn_mn10200): Fix various non-portabilities
+ related to sign extension and the size of ints.
+
+
+ * m10300-opc.c: Support one operand "asr", "lsr" and "asl"
+ instructions. Support (sp) addressing mode by expanding it into
+ (0,sp).
+
+start-sanitize-sky
+
+ * dvp-opc.c (LIMM11, LUIMM15): New symbol types
+ DVP_OPERAND_RELOC_U15_S3 and DVP_OPERAND_RELOC_11_S4 to allow labels to
+ be used as immediate values.
+
+end-sanitize-sky
+start-sanitize-am33
+
+ * m10300-opc.c: Support 4 byte DSP instructions.
+
+end-sanitize-am33
+
+ * mips-dis.c (_print_insn_mips): Fix argument interchange typo.
+
+start-sanitize-am33
+
+ * m10300-opc.c: Support 6 and 7 byte am33 instructions.
+
+end-sanitize-am33
+
+ * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op.
+
+start-sanitize-am33
+
+ * m10300-opc.c: Support for 3 byte and 4 byte extended instructions
+ found on the mn10300.
+
+end-sanitize-am33
+
+ * i386-dis.c: Add support for fxsave, fxrstor, sysenter and
+ sysexit.
+
+
+ * mips-dis.c (print_insn_little_mips): Previously, instruction
+ printing references the symbol table to determine whether the
+ instruction resides in a block regular instructions or mips16
+ instructions. However, when the disassembler gets used in other
+ environments where the symbol table is not present, we no longer
+ rely in the symbol table, rather, use the low bit of the
+ instructions address to guess. There should be no change for usage
+ of the disassembler in host based programse, gdb ,objdump.
+ (print_insn_big_mips): ditto.
+ (print_insn_mips): ditto
+
+
+ * m10200-dis.c (print_insn_mn10200): Don't bomb on unknown opcodes.
+
+
+start-sanitize-am33
+ * m10300-opc.c (USP, SSP, MSP, PC, IMM4, EPSW, RN0, RM1): New
+ operands for the am33.
+ (mn10300_opcodes): Add new instructions from the am33.
+end-sanitize-am33
+ * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall".
+
* i386-dis.c (index16): Add '%' to register names. Use ','
end-sanitize-r5900
start-sanitize-vr5400
-
+
* mips-opc.c (macc, maccu, macchi, macchiu, msac, msacu, msachi, msachiu):
Change pinfo to use WR_HILO.
-end-sanitize-vr5400
+end-sanitize-vr5400
start-sanitize-d30v
* d30v-opc.c (d30v_format_table): Change definition of SHORT_B3
and SHORT_B3b formats to use Rb instead of Ra.
-
+
Add FLAG_MUL16 to MUL2XH opcode.
Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension
* m32r-opc.c: Regenerated - SPECIAL attribute added to some
- insns.
+ insns.
* m32r-opc.h: Regenerated - SPECIAL attribute added to some
insns.
-
+
end-sanitize-m32rx
start-sanitize-d30v
end-sanitize-d30v
start-sanitize-r5900
-
+
* mips-opc.c (break): Added 20-bit single-operand break
instruction for R5900 only.
* dis-buf.c: Internationalised.
start-sanitize-sky
* dvp-dis.c: Internationalised.
- * dvp-opc.c: Internationalised.
+ * dvp-opc.c: Internationalised.
end-sanitize-sky
* h8300-dis.c: Internationalised.
* h8500-dis.c: Internationalised.
* arm-dis.c (print_insn_arm): Add "_all" extension to 'C'
- operator.
+ operator.
* ns32k-dis.c (bit_extract_simple): New function to extract bits
from an arbitrary valid buffer instead of fetching them on demand
- using fetch_data().
+ using fetch_data().
(invalid_float): use bit_extract_simple() instead of bit_extract().
start-sanitize-m32rx
- * m32r-opc.c: Fix SATB bit pattern. Add extra control registers.
- * m32r-opc.h: Add extra control registers.
+ * m32r-opc.c: Fix SATB bit pattern. Add extra control registers.
+ * m32r-opc.h: Add extra control registers.
end-sanitize-m32rx
start-sanitize-r5900
- * mips-dis.c: Change '%' to '#' to avoid conflict with vr5400
- support.
+ * mips-dis.c: Change '%' to '#' in r5900 support.
* vu0.h: Likewise.
end-sanitize-r5900
These patches are courtesy of Jonathan Walton and Tony Thompson
-
+
* arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC
relative addresses.
- * m32r-opc.c: Regenerate.
- * m32r-opc.h: Regenerate.
+ * m32r-opc.c: Regenerate.
+ * m32r-opc.h: Regenerate.
* arm-dis.c (print_insn_little_arm): Prevent examination of stored
symbol if none is present.
(print_insn_big_arm): Prevent examination of stored symbol if
- none is present.
+ none is present.
-
+
* d10v-opc.c (d10v_opcodes): Correct entry for RTE.
-
+
* disassemble.c: Remove disasm_symaddr() function.
start-sanitize-tx49
- * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
+ * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
Add tx49 insns and configury.
end-sanitize-tx49
- * v850-opc.c (v850_opcodes): Further rearrangements.
+ * v850-opc.c (v850_opcodes): Further rearrangements.
start-sanitize-d30v
and cmp instructions.
* d30v-opc.c: Correct entries for repeat*, and sat*.
- Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
+ Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
types. Correct several formats.
* d30v-opc.c: (pre_defined_registers): Add dpsw and dpc.
New form: SHORT_A2; a SHORT_A form that needs an even
register as the first operand.
- * d30v-dis.c (print_insn_d30v): Fix problem where the last
+ * d30v-dis.c (print_insn_d30v): Fix problem where the last
instruction was not being disassembled if there were an odd
number of instructions.
start-sanitize-v850e
* v850-dis.c (disassemble): Add support for v850EA instructions.
-
+
* v850-opc.c (insert_i5div, extract_i5div): New Functions.
(v850_opcodes): Add v850EA instructions.
* v850-dis.c (disassemble): Add support for v850E instructions.
-
+
* v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16,
extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9,
insert_spe, extract_spe): New Functions.
(v850_opcodes): Add v850E instructions.
end-sanitize-v850e
-
+
* v850-opc.c: Reorganised and re-layed out to improve readability
and portability.
negating it.
(UNUSED): remove one level of parens, so MSVC doesn't choke on
nesting depth when all the macros are expanded.
-
+
* sparc-opc.c: The fcmp v9a instructions take an integer register
- * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new
+ * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new
field membership.
* mips16-opc.c (mip16_opcodes): same.
* m68k-opc.c (m68k_opcodes): Provide coldfire division module
instructions.
-
+
end-sanitize-coldfire
* m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and
mulul insns on the coldfire.
-
+
* arm-dis.c (print_insn_arm): Don't print instruction bytes.
* m68k-opc.c (m68k_opcodes): Added entries for the tst insns on
the mc68000.
-
+
* m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction.
- * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
+ * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
start-sanitize-tic80
* mips-opc.c: Add macros for cop0, cop1 cop2 and cop3.
- Change mips_opcodes from const array to a pointer,
+ Change mips_opcodes from const array to a pointer,
and change bfd_mips_num_opcodes from const int to int,
- so that we can increase the size of the mips opcodes table
+ so that we can increase the size of the mips opcodes table
dynamically.
start-sanitize-tic80
* d30v-opc.c: Removed references to FLAG_X.
-end-sanitize-d30v
+end-sanitize-d30v
* Makefile.in: Add dependencies on ../bfd/bfd.h as required.
* d30v-opc.c: New file.
* disassemble.c (disassembler) Add entry for d30v.
-end-sanitize-d30v
+end-sanitize-d30v
start-sanitize-tic80
- * tic80-opc.c (tic80_predefined_symbols): Add symbolic
+ * tic80-opc.c (tic80_predefined_symbols): Add symbolic
representations for the floating point BITNUM values.
start-sanitize-r5900
-
+
* mips-opc.c: add r5900.
-
+
end-sanitize-r5900
start-sanitize-tic80
* m68k-opc.c (m68k_opcodes): Changed operand specifier for the
coldfire moveb instruction to not allow an address register as
destination. Although the documentation does not indicate that
- this is invalid, experiments uncovered unexpected behavior.
+ this is invalid, experiments uncovered unexpected behavior.
Added a comment explaining the situation. Thanks to Andreas
Schwab for pointing this out to me.
entries are presorted so that entries with the same mnemonic are
adjacent to each other in the table. Sort the entries for each
instruction so that this is true.
-
+
end-sanitize-tic80
"vsub", "vst", "xnor", and "xor" instructions.
(V_a1): Renamed from V_a, msb of accumulator reg number.
(V_a0): Add macro, lsb of accumulator reg number.
-
+
* tic80-dis.c (print_insn_tic80): Broke excessively long
math instruction packed into a single opcode.
* tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
to explain why it comes after the other vector opcodes.
-
+
end-sanitize-tic80
- * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
+ * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
move insns to handle immediate operands.
-
+
* m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
Remove some opcodes that are possible, but illegal, such
as long immediate instructions with doubles for immediate
values. Add "vadd" and "vld" instructions.
-
+
* tic80-opc.c (tic80_operands): Reorder some table entries to make
followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather
than old TIC80_OPERAND_RELATIVE. Add support for new
TIC80_OPERAND_BASEREL flag bit.
-
+
* tic80-dis.c (print_insn_tic80): Print floating point operands
(P2): Macro for the 'P2' field.
(P1): Macro for the 'P1' field.
(tic80_opcodes): Add entries for "exts", "extu", "fadd",
- "fcmp", and "fdiv".
-
+ "fcmp", and "fdiv".
+
end-sanitize-tic80
(print_insn_tic80): If R_SCALED then print ":s" modifier for operand.
* tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
- (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
+ (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
REG_BASE_M_SI, REG_BASE_M_LI respectively.
(REG_SCALED, LSI_SCALED): New operand types.
(E): New macro for 'E' bit at bit 27.
(tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap
opcodes, including the various size flavors (b,h,w,d) for
the direct load and store instructions.
-
+
* tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit
(MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
masks with "MASK_* & ~M_*" to get the M bit reset.
(tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
-
+
* tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE
start-sanitize-tic80
(tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in.
end-sanitize-tic80
-
+
* mips16-opc.c: Add "abs".
* configure: Regenerate with autoconf.
* tic80-dis.c: Add file.
* tic80-opc.c: Add file.
-
+
end-sanitize-tic80
* m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use
register operands for immediate arithmetic, not, neg, negx, and
set according to condition instructions.
-
+
* m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage
specifier of the effective-address operand in immediate forms of
arithmetic instructions. The specifier for the immediate operand
* mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc"
opcode.
- * mn10300-dis.c (disassemble): Use '$' instead of '%' for
+ * mn10300-dis.c (disassemble): Use '$' instead of '%' for
register prefix.
* mn10300-dis.c (disassemble): Prefix registers with '%'.
* mn10300-opc.c (mn10300_operands): Add "REGS" for a register
list.
(mn10300_opcodes): Use REGS for register list in "movm" instructions.
-
+
* d10v-opc.c (d10v_opcodes): Add3 sets the carry.
* mn10300-opc.c (mn10300_operands): Hijack "bits" field
in MN10300_OPERAND_SPLIT operands for how many bits
appear in the basic insn word. Add IMM32_HIGH24,
- IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
+ IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
(mn10300_opcodes): Use new operands as needed.
* mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8
standard disassembly.
* alpha-opc.c (alpha_operands): Rearrange flags slot.
- (alpha_opcodes): Add new BWX, CIX, and MAX instructions.
+ (alpha_opcodes): Add new BWX, CIX, and MAX instructions.
Recategorize PALcode instructions.
* mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
-
+
* mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
Update many operand fields to deal with signed vs unsigned
issues. Fix one or two typos in the "mov" instruction
opcode, mask and/or operand fields.
-
+
* m68k-opc.c (plusha): Prefer encoding for m68040up, in case
* configure: (bfd_v850v_arch) Add new case.
* configure.in: (bfd_v850_arch) Add new case.
* v850-opc.c: New file.
-
+
* sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
* sh-opc.h (sh_arg_type): Add F_FR0.
(sh_table, case fmac): Add F_FR0 as first argument.
-
+
* sh-opc.h (sh_opcode_info): Increase arg array size to 4.
* sh-opc.h: Added bsrf and braf.
* arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete
bogus [ls]fm{ea,fd} patterns.
* mpw-config.in (target_arch): Compute from canonical target.
(m68k, mips, powerpc, sparc): Add architectures.
* mpw-make.in (disassemble.c.o): Add.
- (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far).
+ (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far).
* mpw-config.in (BFD_MACHINES): Set to a default value.
* mpw-make.in (BFD_MACHINES): Remove wired-in value.
* hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template.
- No space before 'u', 'f', or 'N'.
+ No space before 'u', 'f', or 'N'.
* alpha-opc.h, alpha-dis.c (print_insn_alpha): Add
- FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct
+ FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct
FLOAT_FORMAT_CODE to put out floating point register names.
defined, since gdb has been fixed.
- * hppa-dis.c (print_insn_hppa): Last argument to fput_reg,
+ * hppa-dis.c (print_insn_hppa): Last argument to fput_reg,
fput_reg_r, fput_creg, fput_const, and fputs_filtered should
be a *disassemble_info, not a *FILE.
* hppa-dis.c: Support 'd', '!', and 'a'.
projects / binutils.git / blobdiff