+
+ * sparc.h (F_PREFERRED): Define.
+ (F_PREF_ALIAS): Define.
+
+
+ * v850.h (V850_INVERSE_PCREL): Define.
+
+
+ PR binutils/15068
+ * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
+
+
+ PR binutils/15068
+ * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
+ Add 16-bit opcodes.
+ * tic6xc-opcode-table.h: Add 16-bit insns.
+ * tic6x.h: Add support for 16-bit insns.
+
+
+ * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
+ and mov.b/w/l Rs,@(d:32,ERd).
+
+
+ PR gas/15082
+ * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
+ from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
+ tic6x_operand_xregpair operand coding type.
+ Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
+ opcode field, usu ORXREGD1324 for the src2 operand and remove the
+ TIC6X_FLAG_NO_CROSS.
+
+
+ PR gas/15095
+ * tic6x.h (enum tic6x_coding_method): Add
+ tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
+ separately the msb and lsb of a register pair. This is needed to
+ encode the opcodes in the same way as TI assembler does.
+ * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
+ and rsqrdp opcodes to use the new field coding types.
+
+
+ * arm.h (CRC_EXT_ARMV8): New constant.
+ (ARCH_CRC_ARMV8): New macro.
+
+
+ * aarch64.h (AARCH64_FEATURE_CRC): New macro.
+
+
+ Based on patches from Altera Corporation.
+
+ * nios2.h: New file.
+
+
+ * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
+
+
+ PR gas/15069
+ * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
+
+
+ * v850.h: Add e3v5 support.
+
+
+ * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
+
+
+ * ppc.h (PPC_OPCODE_POWER8): New define.
+ (PPC_OPCODE_HTM): Likewise.
+
+
+ * metag.h: New file.
+
+
+ * cr16.h (make_instruction): Rename to cr16_make_instruction.
+ (match_opcode): Rename to cr16_match_opcode.
+
+
+ * mips.h: Add support for r5900 instructions including lq and sq.
+
+
+ * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
+ (make_instruction,match_opcode): Added function prototypes.
+ (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
+
+
+ * ppc.h (ppc_parse_cpu): Update prototype.
+
+
+ * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
+ opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
+
+
+ * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
+
+
+ * ia64.h (ia64_opnd): Add new operand types.
+
+
+ * sparc.h (F3F4): New macro.
+
+
+ * aarch64.h: New file.
+
+
+ * mips.h (mips_opcode): Add the exclusions field.
+ (OPCODE_IS_MEMBER): Remove macro.
+ (cpu_is_member): New inline function.
+ (opcode_is_member): Likewise.
+
+
+ * mips.h: Document microMIPS DSP ASE usage.
+ (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
+ microMIPS DSP ASE support.
+ (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
+ (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
+ (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
+ (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
+ (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
+ (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
+ (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
+
+
+ * mips.h: Fix a typo in description.
+
+
+ * avr.h: (AVR_ISA_XCH): New define.
+ (AVR_ISA_XMEGA): Use it.
+ (XCH, LAS, LAT, LAC): New XMEGA opcodes.
+
+
+ * m68hc11.h: Add XGate definitions.
+ (struct m68hc11_opcode): Add xg_mask field.
+
+
+ * ppc.h (PPC_OPCODE_VLE): New definition.
+ (PPC_OP_SA): New macro.
+ (PPC_OP_SE_VLE): New macro.
+ (PPC_OP): Use a variable shift amount.
+ (powerpc_operand): Update comments.
+ (PPC_OPSHIFT_INV): New macro.
+ (PPC_OPERAND_CR): Replace with...
+ (PPC_OPERAND_CR_BIT): ...this and
+ (PPC_OPERAND_CR_REG): ...this.
+
+
+
+ * xgate.h: Header file for XGATE assembler.
+
+
+ * sparc.h: Document new arg code' )' for crypto RS3
+ immediates.
+
+ * sparc.h (struct sparc_opcode): New field 'hwcaps'.
+ F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
+ F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
+ F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
+ (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
+ HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
+ HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
+ HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
+ HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
+ HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
+ HWCAP_CBCOND, HWCAP_CRC32): New defines.
+
+
+ * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
+
+
+ * crx.h (cst4_map): Update declaration.
+
+
+ * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
+ TILEGX_OPC_LD_TLS.
+ * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
+ TILEPRO_OPC_LW_TLS_SN.
+
+
+ * i386.h (XACQUIRE_PREFIX_OPCODE): New.
+ (XRELEASE_PREFIX_OPCODE): Likewise.
+
+
+ * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
+ (INSN_OCTEON2): New macro.
+ (CPU_OCTEON2): New macro.
+ (OPCODE_IS_MEMBER): Add Octeon2.
+
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
* mips.h: Define CPU_R14000, CPU_R16000.
- (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
+ (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
* i386.h: Replace CpuMNI with CpuSSSE3.
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
* m68k.h (mcf_mask): Define.
* mips.h (enum): Add macro M_CACHE_AB.
* mips.h: Add INSN_SMARTMIPS define.
* mips.h: Defines udi bits and masks. Add description of
characters which may appear in the args field of udi
For older changes see ChangeLog-9103
\f
+Copyright (C) 2004-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
Local Variables:
mode: change-log
left-margin: 8
projects / binutils.git / blobdiff