#include "coff/pe.h"
#endif
+#ifdef OBJ_XCOFF
+#include "coff/xcoff.h"
+#include "libxcoff.h"
+#endif
+
/* This is the assembler for the PowerPC or POWER (RS/6000) chips. */
/* Tell the main code what the endianness is. */
static void ppc_ef (int);
static void ppc_es (int);
static void ppc_csect (int);
+static void ppc_dwsect (int);
static void ppc_change_csect (symbolS *, offsetT);
static void ppc_function (int);
static void ppc_extern (int);
/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
int ppc_cie_data_alignment;
+/* More than this number of nops in an alignment op gets a branch
+ instead. */
+unsigned long nop_limit = 4;
+
/* The type of processor we are assembling for. This is one or more
of the PPC_OPCODE flags defined in opcode/ppc.h. */
ppc_cpu_t ppc_cpu = 0;
+
+/* Flags set on encountering toc relocs. */
+enum {
+ has_large_toc_reloc = 1,
+ has_small_toc_reloc = 2
+} toc_reloc_types;
\f
/* The target specific pseudo-ops which we support. */
{ "bi", ppc_biei, 0 },
{ "bs", ppc_bs, 0 },
{ "csect", ppc_csect, 0 },
+ { "dwsect", ppc_dwsect, 0 },
{ "data", ppc_section, 'd' },
{ "eb", ppc_eb, 0 },
{ "ec", ppc_ec, 0 },
cause BFD to set the section number of a symbol to N_DEBUG. */
static asection *ppc_coff_debug_section;
+/* Structure to set the length field of the dwarf sections. */
+struct dw_subsection {
+ /* Subsections are simply linked. */
+ struct dw_subsection *link;
+
+ /* The subsection number. */
+ subsegT subseg;
+
+ /* Expression to compute the length of the section. */
+ expressionS end_exp;
+};
+
+static struct dw_section {
+ /* Corresponding section. */
+ segT sect;
+
+ /* Simply linked list of subsections with a label. */
+ struct dw_subsection *list_subseg;
+
+ /* The anonymous subsection. */
+ struct dw_subsection *anon_subseg;
+} dw_sections[XCOFF_DWSECT_NBR_NAMES];
#endif /* OBJ_XCOFF */
#ifdef TE_PE
#else
const char *const md_shortopts = "um:";
#endif
+#define OPTION_NOPS (OPTION_MD_BASE + 0)
const struct option md_longopts[] = {
+ {"nops", required_argument, NULL, OPTION_NOPS},
{NULL, no_argument, NULL, 0}
};
const size_t md_longopts_size = sizeof (md_longopts);
break;
#endif
+ case OPTION_NOPS:
+ {
+ char *end;
+ nop_limit = strtoul (optarg, &end, 0);
+ if (*end)
+ as_bad (_("--nops needs a numeric argument"));
+ }
+ break;
+
default:
return 0;
}
{
fprintf (stream, _("\
PowerPC options:\n\
--a32 generate ELF32/XCOFF32\n\
--a64 generate ELF64/XCOFF64\n\
--u ignored\n\
--mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n\
--mpwr generate code for POWER (RIOS1)\n\
--m601 generate code for PowerPC 601\n\
+-a32 generate ELF32/XCOFF32\n\
+-a64 generate ELF64/XCOFF64\n\
+-u ignored\n\
+-mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n\
+-mpwr generate code for POWER (RIOS1)\n\
+-m601 generate code for PowerPC 601\n\
-mppc, -mppc32, -m603, -m604\n\
- generate code for PowerPC 603/604\n\
--m403 generate code for PowerPC 403\n\
--m405 generate code for PowerPC 405\n\
--m440 generate code for PowerPC 440\n\
--m464 generate code for PowerPC 464\n\
--m476 generate code for PowerPC 476\n\
+ generate code for PowerPC 603/604\n\
+-m403 generate code for PowerPC 403\n\
+-m405 generate code for PowerPC 405\n\
+-m440 generate code for PowerPC 440\n\
+-m464 generate code for PowerPC 464\n\
+-m476 generate code for PowerPC 476\n\
-m7400, -m7410, -m7450, -m7455\n\
- generate code for PowerPC 7400/7410/7450/7455\n\
--m750cl generate code for PowerPC 750cl\n"));
+ generate code for PowerPC 7400/7410/7450/7455\n\
+-m750cl generate code for PowerPC 750cl\n"));
fprintf (stream, _("\
--mppc64, -m620 generate code for PowerPC 620/625/630\n\
--mppc64bridge generate code for PowerPC 64, including bridge insns\n\
--mbooke generate code for 32-bit PowerPC BookE\n\
--ma2 generate code for A2 architecture\n\
--mpower4 generate code for Power4 architecture\n\
--mpower5 generate code for Power5 architecture\n\
--mpower6 generate code for Power6 architecture\n\
--mpower7 generate code for Power7 architecture\n\
--mcell generate code for Cell Broadband Engine architecture\n\
--mcom generate code Power/PowerPC common instructions\n\
--many generate code for any architecture (PWR/PWRX/PPC)\n"));
+-mppc64, -m620 generate code for PowerPC 620/625/630\n\
+-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
+-mbooke generate code for 32-bit PowerPC BookE\n\
+-ma2 generate code for A2 architecture\n\
+-mpower4, -mpwr4 generate code for Power4 architecture\n\
+-mpower5, -mpwr5, -mpwr5x\n\
+ generate code for Power5 architecture\n\
+-mpower6, -mpwr6 generate code for Power6 architecture\n\
+-mpower7, -mpwr7 generate code for Power7 architecture\n\
+-mcell generate code for Cell Broadband Engine architecture\n\
+-mcom generate code Power/PowerPC common instructions\n\
+-many generate code for any architecture (PWR/PWRX/PPC)\n"));
fprintf (stream, _("\
--maltivec generate code for AltiVec\n\
--mvsx generate code for Vector-Scalar (VSX) instructions\n\
--me300 generate code for PowerPC e300 family\n\
--me500, -me500x2 generate code for Motorola e500 core complex\n\
--me500mc, generate code for Freescale e500mc core complex\n\
--me500mc64, generate code for Freescale e500mc64 core complex\n\
--mspe generate code for Motorola SPE instructions\n\
--mregnames Allow symbolic names for registers\n\
--mno-regnames Do not allow symbolic names for registers\n"));
+-maltivec generate code for AltiVec\n\
+-mvsx generate code for Vector-Scalar (VSX) instructions\n\
+-me300 generate code for PowerPC e300 family\n\
+-me500, -me500x2 generate code for Motorola e500 core complex\n\
+-me500mc, generate code for Freescale e500mc core complex\n\
+-me500mc64, generate code for Freescale e500mc64 core complex\n\
+-mspe generate code for Motorola SPE instructions\n\
+-mtitan generate code for AppliedMicro Titan core complex\n\
+-mregnames Allow symbolic names for registers\n\
+-mno-regnames Do not allow symbolic names for registers\n"));
#ifdef OBJ_ELF
fprintf (stream, _("\
--mrelocatable support for GCC's -mrelocatble option\n\
--mrelocatable-lib support for GCC's -mrelocatble-lib option\n\
--memb set PPC_EMB bit in ELF flags\n\
--mlittle, -mlittle-endian, -l, -le\n\
- generate code for a little endian machine\n\
--mbig, -mbig-endian, -b, -be\n\
- generate code for a big endian machine\n\
--msolaris generate code for Solaris\n\
--mno-solaris do not generate code for Solaris\n\
--V print assembler version number\n\
--Qy, -Qn ignored\n"));
+-mrelocatable support for GCC's -mrelocatble option\n\
+-mrelocatable-lib support for GCC's -mrelocatble-lib option\n\
+-memb set PPC_EMB bit in ELF flags\n\
+-mlittle, -mlittle-endian, -le\n\
+ generate code for a little endian machine\n\
+-mbig, -mbig-endian, -be\n\
+ generate code for a big endian machine\n\
+-msolaris generate code for Solaris\n\
+-mno-solaris do not generate code for Solaris\n\
+-K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n\
+-V print assembler version number\n\
+-Qy, -Qn ignored\n"));
#endif
+ fprintf (stream, _("\
+-nops=count when aligning, more than COUNT nops uses a branch\n"));
}
\f
/* Set ppc_cpu if it is not already set. */
const char *default_os = TARGET_OS;
const char *default_cpu = TARGET_CPU;
- if ((ppc_cpu & ~PPC_OPCODE_ANY) == 0)
+ if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0)
{
if (ppc_obj64)
- ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64;
+ ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64;
else if (strncmp (default_os, "aix", 3) == 0
&& default_os[3] >= '4' && default_os[3] <= '9')
- ppc_cpu |= PPC_OPCODE_COMMON | PPC_OPCODE_32;
+ ppc_cpu |= PPC_OPCODE_COMMON;
else if (strncmp (default_os, "aix3", 4) == 0)
- ppc_cpu |= PPC_OPCODE_POWER | PPC_OPCODE_32;
+ ppc_cpu |= PPC_OPCODE_POWER;
else if (strcmp (default_cpu, "rs6000") == 0)
- ppc_cpu |= PPC_OPCODE_POWER | PPC_OPCODE_32;
+ ppc_cpu |= PPC_OPCODE_POWER;
else if (strncmp (default_cpu, "powerpc", 7) == 0)
- ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32;
+ ppc_cpu |= PPC_OPCODE_PPC;
else
as_fatal (_("Unknown default cpu = %s, os = %s"),
default_cpu, default_os);
return bfd_mach_ppc64;
else if (ppc_arch () == bfd_arch_rs6000)
return bfd_mach_rs6k;
+ else if (ppc_cpu & PPC_OPCODE_TITAN)
+ return bfd_mach_ppc_titan;
else
return bfd_mach_ppc;
}
}
}
- if ((op->flags & ppc_cpu & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) != 0
- && ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
- || ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64))
- == (ppc_cpu & (PPC_OPCODE_32 | PPC_OPCODE_64)))
- || (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0)
+ if ((ppc_cpu & op->flags) != 0
&& !(ppc_cpu & op->deprecated))
{
const char *retval;
retval = hash_insert (ppc_hash, op->name, (void *) op);
if (retval != NULL)
{
- /* Ignore Power duplicates for -m601. */
- if ((ppc_cpu & PPC_OPCODE_601) != 0
- && (op->flags & PPC_OPCODE_POWER) != 0)
- continue;
-
as_bad (_("duplicate instruction %s"),
op->name);
bad_insn = TRUE;
macro_end = powerpc_macros + powerpc_num_macros;
for (macro = powerpc_macros; macro < macro_end; macro++)
{
- if ((macro->flags & ppc_cpu) != 0)
+ if ((macro->flags & ppc_cpu) != 0 || (ppc_cpu & PPC_OPCODE_ANY) != 0)
{
const char *retval;
int offset;
p = frag_more (nbytes);
+ memset (p, 0, nbytes);
offset = 0;
if (target_big_endian)
offset = nbytes - size;
toc = bfd_get_section_by_name (stdoutput, ".toc");
if (toc != NULL
+ && toc_reloc_types != has_large_toc_reloc
&& bfd_section_size (stdoutput, toc) > 0x10000)
as_warn (_("TOC section size exceeds 64k"));
}
}
+ switch (reloc)
+ {
+ case BFD_RELOC_PPC_TOC16:
+ toc_reloc_types |= has_small_toc_reloc;
+ break;
+ case BFD_RELOC_PPC64_TOC16_LO:
+ case BFD_RELOC_PPC64_TOC16_HI:
+ case BFD_RELOC_PPC64_TOC16_HA:
+ toc_reloc_types |= has_large_toc_reloc;
+ break;
+ default:
+ break;
+ }
+
if (ppc_obj64
&& (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
{
if (*str != endc
&& (endc != ',' || *str != '\0'))
{
- as_bad (_("syntax error; found `%c' but expected `%c'"), *str, endc);
+ if (*str == '\0')
+ as_bad (_("syntax error; end of line, expected `%c'"), endc);
+ else
+ as_bad (_("syntax error; found `%c', expected `%c'"), *str, endc);
break;
}
#ifdef OBJ_ELF
/* Do we need/want a APUinfo section? */
- if ((ppc_cpu & PPC_OPCODE_E500MC) != 0)
+ if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC)) != 0)
{
/* These are all version "1". */
if (opcode->flags & PPC_OPCODE_SPE)
}
\f
#ifdef OBJ_ELF
-/* For ELF, add support for SHF_EXCLUDE and SHT_ORDERED. */
-
-bfd_vma
-ppc_section_letter (int letter, char **ptr_msg)
-{
- if (letter == 'e')
- return SHF_EXCLUDE;
-
- *ptr_msg = _("Bad .section directive: want a,e,w,x,M,S,G,T in string");
- return -1;
-}
-
-bfd_vma
-ppc_section_word (char *str, size_t len)
-{
- if (len == 7 && strncmp (str, "exclude", 7) == 0)
- return SHF_EXCLUDE;
-
- return -1;
-}
+/* For ELF, add support for SHT_ORDERED. */
int
ppc_section_type (char *str, size_t len)
}
int
-ppc_section_flags (flagword flags, bfd_vma attr, int type)
+ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type)
{
if (type == SHT_ORDERED)
flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES;
- if (attr & SHF_EXCLUDE)
- flags |= SEC_EXCLUDE;
-
return flags;
}
#endif /* OBJ_ELF */
ppc_current_csect = sym;
}
+static void
+ppc_change_debug_section (unsigned int idx, subsegT subseg)
+{
+ segT sec;
+ flagword oldflags;
+ const struct xcoff_dwsect_name *dw = &xcoff_dwsect_names[idx];
+
+ sec = subseg_new (dw->name, subseg);
+ oldflags = bfd_get_section_flags (stdoutput, sec);
+ if (oldflags == SEC_NO_FLAGS)
+ {
+ /* Just created section. */
+ gas_assert (dw_sections[idx].sect == NULL);
+
+ bfd_set_section_flags (stdoutput, sec, SEC_DEBUGGING);
+ bfd_set_section_alignment (stdoutput, sec, 0);
+ dw_sections[idx].sect = sec;
+ }
+
+ /* Not anymore in a csect. */
+ ppc_current_csect = NULL;
+}
+
+/* The .dwsect pseudo-op. Defines a DWARF section. Syntax is:
+ .dwsect flag [, opt-label ]
+*/
+
+static void
+ppc_dwsect (int ignore ATTRIBUTE_UNUSED)
+{
+ offsetT flag;
+ symbolS *opt_label;
+ const struct xcoff_dwsect_name *dw;
+ struct dw_subsection *subseg;
+ struct dw_section *dws;
+ int i;
+
+ /* Find section. */
+ flag = get_absolute_expression ();
+ dw = NULL;
+ for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++)
+ if (xcoff_dwsect_names[i].flag == flag)
+ {
+ dw = &xcoff_dwsect_names[i];
+ break;
+ }
+
+ /* Parse opt-label. */
+ if (*input_line_pointer == ',')
+ {
+ const char *label;
+ char c;
+
+ ++input_line_pointer;
+
+ label = input_line_pointer;
+ c = get_symbol_end ();
+ opt_label = symbol_find_or_make (label);
+ *input_line_pointer = c;
+ }
+ else
+ opt_label = NULL;
+
+ demand_empty_rest_of_line ();
+
+ /* Return now in case of unknown subsection. */
+ if (dw == NULL)
+ {
+ as_bad (_("No known dwarf XCOFF section for flag 0x%08x\n"),
+ (unsigned)flag);
+ return;
+ }
+
+ /* Find the subsection. */
+ dws = &dw_sections[i];
+ subseg = NULL;
+ if (opt_label != NULL && S_IS_DEFINED (opt_label))
+ {
+ /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */
+ if (dws->sect == NULL || S_GET_SEGMENT (opt_label) != dws->sect)
+ {
+ as_bad (_("label %s was not defined in this dwarf section"),
+ S_GET_NAME (opt_label));
+ subseg = dws->anon_subseg;
+ opt_label = NULL;
+ }
+ else
+ subseg = symbol_get_tc (opt_label)->u.dw;
+ }
+
+ if (subseg != NULL)
+ {
+ /* Switch to the subsection. */
+ ppc_change_debug_section (i, subseg->subseg);
+ }
+ else
+ {
+ /* Create a new dw subsection. */
+ subseg = (struct dw_subsection *)
+ xmalloc (sizeof (struct dw_subsection));
+
+ if (opt_label == NULL)
+ {
+ /* The anonymous one. */
+ subseg->subseg = 0;
+ subseg->link = NULL;
+ dws->anon_subseg = subseg;
+ }
+ else
+ {
+ /* A named one. */
+ if (dws->list_subseg != NULL)
+ subseg->subseg = dws->list_subseg->subseg + 1;
+ else
+ subseg->subseg = 1;
+
+ subseg->link = dws->list_subseg;
+ dws->list_subseg = subseg;
+ symbol_get_tc (opt_label)->u.dw = subseg;
+ }
+
+ ppc_change_debug_section (i, subseg->subseg);
+
+ if (dw->def_size)
+ {
+ /* Add the length field. */
+ expressionS *exp = &subseg->end_exp;
+ int sz;
+
+ if (opt_label != NULL)
+ symbol_set_value_now (opt_label);
+
+ /* Add the length field. Note that according to the AIX assembler
+ manual, the size of the length field is 4 for powerpc32 but
+ 12 for powerpc64. */
+ if (ppc_obj64)
+ {
+ /* Write the 64bit marker. */
+ md_number_to_chars (frag_more (4), -1, 4);
+ }
+
+ exp->X_op = O_subtract;
+ exp->X_op_symbol = symbol_temp_new_now ();
+ exp->X_add_symbol = symbol_temp_make ();
+
+ sz = ppc_obj64 ? 8 : 4;
+ exp->X_add_number = -sz;
+ emit_expr (exp, sz);
+ }
+ }
+}
+
/* This function handles the .text and .data pseudo-ops. These
pseudo-ops aren't really used by XCOFF; we implement them for the
convenience of people who aren't used to XCOFF. */
symbol_get_tc (sym)->output = 1;
- if (S_GET_STORAGE_CLASS (sym) == C_STSYM) {
-
- symbol_get_tc (sym)->within = ppc_current_block;
+ if (S_GET_STORAGE_CLASS (sym) == C_STSYM)
+ {
+ /* In this case :
- /* In this case :
+ .bs name
+ .stabx "z",arrays_,133,0
+ .es
- .bs name
- .stabx "z",arrays_,133,0
- .es
+ .comm arrays_,13768,3
- .comm arrays_,13768,3
+ resolve_symbol_value will copy the exp's "within" into sym's when the
+ offset is 0. Since this seems to be corner case problem,
+ only do the correction for storage class C_STSYM. A better solution
+ would be to have the tc field updated in ppc_symbol_new_hook. */
- resolve_symbol_value will copy the exp's "within" into sym's when the
- offset is 0. Since this seems to be corner case problem,
- only do the correction for storage class C_STSYM. A better solution
- would be to have the tc field updated in ppc_symbol_new_hook. */
+ if (exp.X_op == O_symbol)
+ {
+ if (ppc_current_block == NULL)
+ as_bad (_(".stabx of storage class stsym must be within .bs/.es"));
- if (exp.X_op == O_symbol)
- {
- symbol_get_tc (exp.X_add_symbol)->within = ppc_current_block;
- }
- }
+ symbol_get_tc (sym)->within = ppc_current_block;
+ symbol_get_tc (exp.X_add_symbol)->within = ppc_current_block;
+ }
+ }
if (exp.X_op != O_symbol
|| ! S_IS_EXTERNAL (exp.X_add_symbol)
{
/* The fifth argument is the function size. */
++input_line_pointer;
- symbol_get_tc (ext_sym)->size = symbol_new ("L0\001",
- absolute_section,
- (valueT) 0,
- &zero_address_frag);
- pseudo_set (symbol_get_tc (ext_sym)->size);
+ symbol_get_tc (ext_sym)->u.size = symbol_new
+ ("L0\001", absolute_section,(valueT) 0, &zero_address_frag);
+ pseudo_set (symbol_get_tc (ext_sym)->u.size);
}
}
}
cons (byte_count);
}
+void
+ppc_xcoff_end (void)
+{
+ int i;
+
+ for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++)
+ {
+ struct dw_section *dws = &dw_sections[i];
+ struct dw_subsection *dwss;
+
+ if (dws->anon_subseg)
+ {
+ dwss = dws->anon_subseg;
+ dwss->link = dws->list_subseg;
+ }
+ else
+ dwss = dws->list_subseg;
+
+ for (; dwss != NULL; dwss = dwss->link)
+ if (dwss->end_exp.X_add_symbol != NULL)
+ {
+ subseg_set (dws->sect, dwss->subseg);
+ symbol_set_value_now (dwss->end_exp.X_add_symbol);
+ }
+ }
+}
+
#endif /* OBJ_XCOFF */
#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
\f
tc->real_name = NULL;
tc->subseg = 0;
tc->align = 0;
- tc->size = NULL;
+ tc->u.size = NULL;
+ tc->u.dw = NULL;
tc->within = NULL;
if (ppc_stab_symbol)
if (ppc_last_function != (symbolS *) NULL)
as_bad (_("two .function pseudo-ops with no intervening .ef"));
ppc_last_function = sym;
- if (symbol_get_tc (sym)->size != (symbolS *) NULL)
+ if (symbol_get_tc (sym)->u.size != (symbolS *) NULL)
{
- resolve_symbol_value (symbol_get_tc (sym)->size);
+ resolve_symbol_value (symbol_get_tc (sym)->u.size);
SA_SET_SYM_FSIZE (sym,
- (long) S_GET_VALUE (symbol_get_tc (sym)->size));
+ (long) S_GET_VALUE (symbol_get_tc (sym)->u.size));
}
}
else if (S_GET_STORAGE_CLASS (sym) == C_FCN
else if (S_GET_STORAGE_CLASS (sym) == C_STSYM)
{
symbolS *block;
- symbolS *csect;
+ valueT base;
- /* The value is the offset from the enclosing csect. */
block = symbol_get_tc (sym)->within;
- csect = symbol_get_tc (block)->within;
- resolve_symbol_value (csect);
- S_SET_VALUE (sym, S_GET_VALUE (sym) - S_GET_VALUE (csect));
+ if (block)
+ {
+ /* The value is the offset from the enclosing csect. */
+ symbolS *csect;
+
+ csect = symbol_get_tc (block)->within;
+ resolve_symbol_value (csect);
+ base = S_GET_VALUE (csect);
+ }
+ else
+ base = 0;
+
+ S_SET_VALUE (sym, S_GET_VALUE (sym) - base);
}
else if (S_GET_STORAGE_CLASS (sym) == C_BINCL
|| S_GET_STORAGE_CLASS (sym) == C_EINCL)
{
static bfd_vma vma = 0;
+ /* Dwarf sections start at 0. */
+ if (bfd_get_section_flags (NULL, sec) & SEC_DEBUGGING)
+ return;
+
vma = md_section_align (sec, vma);
bfd_set_section_vma (stdoutput, sec, vma);
vma += bfd_section_size (stdoutput, sec);
if (symseg == absolute_section)
return 0;
+ /* Always adjust symbols in debugging sections. */
+ if (bfd_get_section_flags (stdoutput, symseg) & SEC_DEBUGGING)
+ return 1;
+
if (ppc_toc_csect != (symbolS *) NULL
&& fix->fx_addsy != ppc_toc_csect
&& symseg == data_section
&& fix->fx_r_type != BFD_RELOC_LO16_GOTOFF
&& fix->fx_r_type != BFD_RELOC_HI16_GOTOFF
&& fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF
+ && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS
+ && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS
&& fix->fx_r_type != BFD_RELOC_GPREL16
&& fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT
&& fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY
char *dest = fragP->fr_literal + fragP->fr_fix;
fragP->fr_var = 4;
+
+ if (count > 4 * nop_limit && count < 0x2000000)
+ {
+ struct frag *rest;
+
+ /* Make a branch, then follow with nops. Insert another
+ frag to handle the nops. */
+ md_number_to_chars (dest, 0x48000000 + count, 4);
+ count -= 4;
+ if (count == 0)
+ return;
+
+ rest = xmalloc (SIZEOF_STRUCT_FRAG + 4);
+ memcpy (rest, fragP, SIZEOF_STRUCT_FRAG);
+ fragP->fr_next = rest;
+ fragP = rest;
+ rest->fr_address += rest->fr_fix + 4;
+ rest->fr_fix = 0;
+ /* If we leave the next frag as rs_align_code we'll come here
+ again, resulting in a bunch of branches rather than a
+ branch followed by nops. */
+ rest->fr_type = rs_align;
+ dest = rest->fr_literal;
+ }
+
md_number_to_chars (dest, 0x60000000, 4);
if ((ppc_cpu & PPC_OPCODE_POWER6) != 0
projects / binutils.git / blobdiff