+
+ * aclocal.m4, configure: Regenerate.
+
+
+ * config.in, configure: Regenerate.
+
+
+ PR 14072
+ * compile.c: Include config.h before system header files.
+ * sim-main.h: Likewise.
+
+
+ * aclocal.m4, config.in, configure: Regenerate.
+
+
+ * aclocal.m4: New file.
+ * configure: Regenerate.
+
+
+ * configure.ac: Change include to common/acinclude.m4.
+
+
+ * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
+ call. Replace common.m4 include with SIM_AC_COMMON.
+ * configure: Regenerate.
+
+
+ * compile.c (sim_do_command): Delete.
+
+
+ * compile.c (sim_store_register): Update return value to
+ match new API.
+
+
+ * compile.c (sim_write): Add const to buffer arg.
+
+
+ * configure: Regenerate.
+
+ * compile.c(fetch_1): Fix pre-dec, pre-inc, post-dec and post-inc.
+ Index registers not masked memory areas.
+ Only simply increment or decrement.
+ * compile.c(store_1): Ditto.
+
+
+ * config.in: Regenerate.
+ * configure: Likewise.
+
+ * configure: Regenerate.
+
+
+ * compile.c: Add const to remove warning.
+
+
+ * configure: Regenerate to track ../common/common.m4 changes.
+ * config.in: Ditto.
+
+
+ * configure: Regenerate.
+
+
+ * compile.c (sim_resume): Fix the last byte of ARGV for
+ SYS_CMDLINE.
+
+
+ * acconfig.h: Remove.
+ * config.in: Regenerate.
+
+
+ * compile.c (OBITOP): Bit address mask low three bit.
+ * compile.c (decode): Fix warning.
+
+
+ * configure: Regenerated.
+
+
+ * configure: Regenerated.
+
+
+ * configure: Regenerated.
+
+
+ * configure: Regenerate.
+
+
+ * configure.ac: Sinclude aclocal.m4 before common.m4. Add
+ explicit call to AC_CONFIG_HEADER.
+ * configure: Regenerate.
+
+
+ * configure.ac: Update to use ../common/common.m4.
+ * configure: Re-generate.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure.ac: Rename configure.in, require autoconf 2.59.
+ * configure: Re-generate.
+
+
+ * configure: Regenerate for ../common/aclocal.m4 update.
+
+
+ * compile.c (sim_resume): Make sure that dst.reg refers to the
+ right register byte in mova/sz.l @(dd,RnL),ERn.
+ * compile.c (sim_resume): Zero-extend immediate to muls, mulsu,
+ mulxs, divs and divxs.
+
+ * compile.c (sim_load): Update sd->memory_size.
+
+
+ * compile.c (sim_resume): Corrected ANDC operation on EXR for H8S.
+
+
+ * compile.c (sim_load): Don't pass a type to bfd_openr.
+
+
+ * sim-main.h (H8300H_MSIZE): Increase from 18 bits to 24 bits.
+
+
+ * compile.c (set_h8300h): Initialize globals to zero.
+
+
+ * compile.c (h8300_normal_mode): New.
+ (SP): Handle normal mode.
+ (bitfrom): Use normal mode flag to return suitable value.
+ (lvalue): Use normal mode flag to return command line location.
+ (decode): Decode instruction correctly for normal mode.
+ (init_pointers): Initialise memory correctly for normal mode.
+ (sim_resume): Handle cases for normal mode using h8300_normal_mode
+ flag.
+ (sim_store_register): Handle 2 byte PC for normal mode.
+ (sim_fetch_register): Handle 2 byte PC for normal mode.
+ (set_h8300h): Set normal mode flag as per architechture.
+ (sim_load): Allocate 64K for normal mode instead of bigger memory.
+
+
+ * compile.c (decode): Enhancements for mova.
+ Initialize cst, reg, and rdisp inside the loop, for each
+ new instruction. Defer correction of the disp2 values until
+ later, and then adjust them by the size of the first operand,
+ rather than the size of the instruction.
+ (sim_resume): For mova, adjust the size of the second operand
+ according to the type of the first operand (INDEXB vs. INDEXW).
+ In cases where there is only one operand, the other two must
+ both be composed on the fly.
+
+
+ * compile.c (sim_resume): Revert 6-24 change, it does not
+ work with gdb breakpoints.
+
+
+ * compile.c (sim_resume): Handle shll reg, reg and shlr reg, reg.
+ (decode): IMM16 is always zero-extended.
+
+
+ * sim-main.h (SIM_WIFSTOPPED, SIM_WSTOPSIG): Define.
+ * compile.c (sim_resume): Use the above to return stop signal.
+
+
+ * compile.c: Replace "Hitachi" with "Renesas".
+ (decode): Distinguish AV_H8S from AV_H8H.
+ (sim_resume): H8SX can use any register for TAS.
+ (decode): Add support for VECIND.
+ (sim_resume): Implement rte/l and rts/l.
+ (GETSR): New macro (actually old macro reincarnated).
+ (decode): Add handling for IMM2.
+ (sim_resume): Drop extra block around jmp, jsr, rts.
+ Add handling for trapa and rte.
+ For divxu.b, change 0xffff mask to 0xff.
+ (set_h8300h): Add bfd_mach_h8300sxn machine.
+
+
+ * sim-main.h (enum h8_regnum): Turn around order of MACH, MACL
+ and SBR, VBR.
+
+
+ * compile.c (sim_fetch_register): Handle SBR, VBR, MACH, MACL.
+ (sim_store_register): Ditto.
+
+
+ * compile.c (sim_info): Fix typo in output.
+
+ * compile.c (set_h8300h): Replace 'flag' arguments
+ with a bfd_machine argument, and decode it inline.
+ Check for bfd_mach_h8300hn and bfd_mach_h8300sn.
+
+
+ * compile.c: Add h8300sx insns and addressing modes.
+ * sim-main.h: Replaces h8300/inst.h.
+ * Makefile.in: Tweak to bring in some sim/common stuff.
+
+
+ * compile.c (sim_resume): Implement 'daa' and 'das' instructions.
+
+
+ * compile.c (cmdline_location): Added function to
+ return the location of 8-bit (256 locations) where the
+ Command Line arguments would be stored.
+ (decode): Added a TRAP to 0xcc for Commandline
+ processing using pseudo opcode O_SYS_CMDLINE.
+ (sim_resume): Added handling of O_SYS_CMDLINE Trap.
+ (sim_create_inferior): Setting a pointer to
+ Commandline Args array.
+ * inst.h: Added a new variable ptr_command_line for
+ storing pointer to Commandline array.
+
* compile.c (decode): Added code for some more magic traps.
projects / binutils.git / blobdiff