/* Declarations for Intel 80386 opcode table
- Copyright (C) 2007-2018 Free Software Foundation, Inc.
+ Copyright (C) 2007-2022 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
02110-1301, USA. */
#include "opcode/i386.h"
-#ifdef HAVE_LIMITS_H
#include <limits.h>
-#endif
-
#ifndef CHAR_BIT
#define CHAR_BIT 8
#endif
Cpu586,
/* i686 or better required */
Cpu686,
+ /* CMOV Instruction support required */
+ CpuCMOV,
+ /* FXSR Instruction support required */
+ CpuFXSR,
/* CLFLUSH Instruction support required */
CpuClflush,
/* NOP Instruction support required */
CpuSSSE3,
/* SSE4a support required */
CpuSSE4a,
- /* ABM New Instructions required */
- CpuABM,
+ /* LZCNT support required */
+ CpuLZCNT,
+ /* POPCNT support required */
+ CpuPOPCNT,
/* SSE4.1 support required */
CpuSSE4_1,
/* SSE4.2 support required */
CpuAVX512DQ,
/* Intel AVX-512 BW Instructions support required. */
CpuAVX512BW,
- /* Intel L1OM support required */
- CpuL1OM,
- /* Intel K1OM support required */
- CpuK1OM,
/* Intel IAMCU support required */
CpuIAMCU,
/* Xsave/xrstor New Instructions support required */
CpuF16C,
/* Intel BMI2 support required */
CpuBMI2,
- /* LZCNT support required */
- CpuLZCNT,
/* HLE support required */
CpuHLE,
/* RTM support required */
CpuSMAP,
/* SHA instructions required. */
CpuSHA,
- /* VREX support required */
- CpuVREX,
/* CLFLUSHOPT instruction required */
CpuClflushOpt,
/* XSAVES/XRSTORS instruction required */
CpuAVX512_VNNI,
/* Intel AVX-512 BITALG Instructions support required. */
CpuAVX512_BITALG,
+ /* Intel AVX-512 BF16 Instructions support required. */
+ CpuAVX512_BF16,
+ /* Intel AVX-512 VP2INTERSECT Instructions support required. */
+ CpuAVX512_VP2INTERSECT,
+ /* TDX Instructions support required. */
+ CpuTDX,
+ /* Intel AVX VNNI Instructions support required. */
+ CpuAVX_VNNI,
+ /* Intel AVX-512 FP16 Instructions support required. */
+ CpuAVX512_FP16,
+ /* PREFETCHI instruction required */
+ CpuPREFETCHI,
+ /* Intel AVX IFMA Instructions support required. */
+ CpuAVX_IFMA,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
/* CET instructions support required */
CpuIBT,
CpuSHSTK,
+ /* AMX-INT8 instructions required */
+ CpuAMX_INT8,
+ /* AMX-BF16 instructions required */
+ CpuAMX_BF16,
+ /* AMX-FP16 instructions required */
+ CpuAMX_FP16,
+ /* AMX-TILE instructions required */
+ CpuAMX_TILE,
/* GFNI instructions required */
CpuGFNI,
/* VAES instructions required */
CpuWBNOINVD,
/* PCONFIG instructions required */
CpuPCONFIG,
- /* MMX register support required */
- CpuRegMMX,
- /* XMM register support required */
- CpuRegXMM,
- /* YMM register support required */
- CpuRegYMM,
- /* ZMM register support required */
- CpuRegZMM,
- /* Mask register support required */
- CpuRegMask,
+ /* WAITPKG instructions required */
+ CpuWAITPKG,
+ /* UINTR instructions required */
+ CpuUINTR,
+ /* CLDEMOTE instruction required */
+ CpuCLDEMOTE,
+ /* MOVDIRI instruction support required */
+ CpuMOVDIRI,
+ /* MOVDIRR64B instruction required */
+ CpuMOVDIR64B,
+ /* ENQCMD instruction required */
+ CpuENQCMD,
+ /* SERIALIZE instruction required */
+ CpuSERIALIZE,
+ /* RDPRU instruction required */
+ CpuRDPRU,
+ /* MCOMMIT instruction required */
+ CpuMCOMMIT,
+ /* SEV-ES instruction(s) required */
+ CpuSEV_ES,
+ /* TSXLDTRK instruction required */
+ CpuTSXLDTRK,
+ /* KL instruction support required */
+ CpuKL,
+ /* WideKL instruction support required */
+ CpuWideKL,
+ /* HRESET instruction required */
+ CpuHRESET,
+ /* INVLPGB instructions required */
+ CpuINVLPGB,
+ /* TLBSYNC instructions required */
+ CpuTLBSYNC,
+ /* SNP instructions required */
+ CpuSNP,
+
+ /* NOTE: These last three items need to remain last and in this order. */
+
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
unsigned int cpui486:1;
unsigned int cpui586:1;
unsigned int cpui686:1;
+ unsigned int cpucmov:1;
+ unsigned int cpufxsr:1;
unsigned int cpuclflush:1;
unsigned int cpunop:1;
unsigned int cpusyscall:1;
unsigned int cpusmx:1;
unsigned int cpussse3:1;
unsigned int cpusse4a:1;
- unsigned int cpuabm:1;
+ unsigned int cpulzcnt:1;
+ unsigned int cpupopcnt:1;
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpuavx:1;
unsigned int cpuavx512vl:1;
unsigned int cpuavx512dq:1;
unsigned int cpuavx512bw:1;
- unsigned int cpul1om:1;
- unsigned int cpuk1om:1;
unsigned int cpuiamcu:1;
unsigned int cpuxsave:1;
unsigned int cpuxsaveopt:1;
unsigned int cpurdrnd:1;
unsigned int cpuf16c:1;
unsigned int cpubmi2:1;
- unsigned int cpulzcnt:1;
unsigned int cpuhle:1;
unsigned int cpurtm:1;
unsigned int cpuinvpcid:1;
unsigned int cpuprfchw:1;
unsigned int cpusmap:1;
unsigned int cpusha:1;
- unsigned int cpuvrex:1;
unsigned int cpuclflushopt:1;
unsigned int cpuxsaves:1;
unsigned int cpuxsavec:1;
unsigned int cpuavx512_vbmi2:1;
unsigned int cpuavx512_vnni:1;
unsigned int cpuavx512_bitalg:1;
+ unsigned int cpuavx512_bf16:1;
+ unsigned int cpuavx512_vp2intersect:1;
+ unsigned int cputdx:1;
+ unsigned int cpuavx_vnni:1;
+ unsigned int cpuavx512_fp16:1;
+ unsigned int cpuprefetchi:1;
+ unsigned int cpuavx_ifma:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
unsigned int cpuptwrite:1;
unsigned int cpuibt:1;
unsigned int cpushstk:1;
+ unsigned int cpuamx_int8:1;
+ unsigned int cpuamx_bf16:1;
+ unsigned int cpuamx_fp16:1;
+ unsigned int cpuamx_tile:1;
unsigned int cpugfni:1;
unsigned int cpuvaes:1;
unsigned int cpuvpclmulqdq:1;
unsigned int cpuwbnoinvd:1;
unsigned int cpupconfig:1;
- unsigned int cpuregmmx:1;
- unsigned int cpuregxmm:1;
- unsigned int cpuregymm:1;
- unsigned int cpuregzmm:1;
- unsigned int cpuregmask:1;
+ unsigned int cpuwaitpkg:1;
+ unsigned int cpuuintr:1;
+ unsigned int cpucldemote:1;
+ unsigned int cpumovdiri:1;
+ unsigned int cpumovdir64b:1;
+ unsigned int cpuenqcmd:1;
+ unsigned int cpuserialize:1;
+ unsigned int cpurdpru:1;
+ unsigned int cpumcommit:1;
+ unsigned int cpusev_es:1;
+ unsigned int cputsxldtrk:1;
+ unsigned int cpukl:1;
+ unsigned int cpuwidekl:1;
+ unsigned int cpuhreset:1;
+ unsigned int cpuinvlpgb:1;
+ unsigned int cputlbsync:1;
+ unsigned int cpusnp:1;
+ /* NOTE: These last three fields need to remain last and in this order. */
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
{
/* has direction bit. */
D = 0,
- /* set if operands can be words or dwords encoded the canonical way */
+ /* set if operands can be both bytes and words/dwords/qwords, encoded the
+ canonical way; the base_opcode field should hold the encoding for byte
+ operands */
W,
/* load form instruction. Must be placed before store form. */
Load,
/* insn has a modrm byte. */
Modrm,
- /* register is in low 3 bits of opcode */
- ShortForm,
- /* special case for jump insns. */
- Jump,
+ /* special case for jump insns; value has to be 1 */
+#define JUMP 1
/* call and jump */
- JumpDword,
+#define JUMP_DWORD 2
/* loop and jecxz */
- JumpByte,
+#define JUMP_BYTE 3
/* special case for intersegment leaps/calls */
- JumpInterSegment,
+#define JUMP_INTERSEGMENT 4
+ /* absolute address for jump */
+#define JUMP_ABSOLUTE 5
+ Jump,
/* FP insn memory format bit, sized by 0x4 */
FloatMF,
/* src/dest swap for floats. */
FloatR,
/* needs size prefix if in 32-bit mode */
- Size16,
+#define SIZE16 1
/* needs size prefix if in 16-bit mode */
- Size32,
+#define SIZE32 2
/* needs size prefix if in 64-bit mode */
- Size64,
+#define SIZE64 3
+ Size,
/* check register size. */
CheckRegSize,
+ /* Instrucion requires that destination must be distinct from source
+ registers. */
+ DistinctDest,
/* instruction ignores operand size prefix and in Intel mode ignores
mnemonic size suffix check. */
- IgnoreSize,
+#define IGNORESIZE 1
/* default insn size depends on mode */
- DefaultSize,
+#define DEFAULTSIZE 2
+ MnemonicSize,
+ /* any memory size */
+ Anysize,
/* b suffix on instruction illegal */
No_bSuf,
/* w suffix on instruction illegal */
No_ldSuf,
/* instruction needs FWAIT */
FWait,
- /* quick test for string instructions */
+ /* IsString provides for a quick test for string instructions, and
+ its actual value also indicates which of the operands (if any)
+ requires use of the %es segment. */
+#define IS_STRING_ES_OP0 2
+#define IS_STRING_ES_OP1 3
IsString,
+ /* RegMem is for instructions with a modrm byte where the register
+ destination operand should be encoded in the mod and regmem fields.
+ Normally, it will be encoded in the reg field. We add a RegMem
+ flag to indicate that it should be encoded in the regmem field. */
+ RegMem,
/* quick test if branch instruction is MPX supported */
BNDPrefixOk,
- /* quick test if NOTRACK prefix is supported */
- NoTrackPrefixOk,
- /* quick test for lockable instructions */
- IsLockable,
/* fake an extra reg operand for clr, imul and special register
processing for some instructions. */
RegKludge,
/* An implicit xmm0 as the first operand */
Implicit1stXmm0,
- /* The HLE prefix is OK:
- 1. With a LOCK prefix.
- 2. With or without a LOCK prefix.
- 3. With a RELEASE (0xf3) prefix.
- */
-#define HLEPrefixNone 0
-#define HLEPrefixLock 1
-#define HLEPrefixAny 2
-#define HLEPrefixRelease 3
- HLEPrefixOk,
- /* An instruction on which a "rep" prefix is acceptable. */
- RepPrefixOk,
- /* Convert to DWORD */
- ToDword,
- /* Convert to QWORD */
- ToQword,
- /* Address prefix changes operand 0 */
- AddrPrefixOp0,
+#define PrefixNone 0
+#define PrefixRep 1
+#define PrefixHLERelease 2 /* Okay with an XRELEASE (0xf3) prefix. */
+#define PrefixNoTrack 3
+ /* Prefixes implying "LOCK okay" must come after Lock. All others have
+ to come before. */
+#define PrefixLock 4
+#define PrefixHLELock 5 /* Okay with a LOCK prefix. */
+#define PrefixHLEAny 6 /* Okay with or without a LOCK prefix. */
+ PrefixOk,
+ /* Address prefix changes register operand */
+ AddrPrefixOpReg,
/* opcode is a prefix */
IsPrefix,
/* instruction has extension in 8 bit imm */
ImmExt,
/* instruction don't need Rex64 prefix. */
NoRex64,
- /* instruction require Rex64 prefix. */
- Rex64,
/* deprecated fp insn, gets a warning */
Ugh,
/* insn has VEX prefix:
0: Set by the REX.W bit.
1: VEX.W0. Should always be 0.
2: VEX.W1. Should always be 1.
+ 3: VEX.WIG. The VEX.W bit is ignored.
*/
#define VEXW0 1
#define VEXW1 2
+#define VEXWIG 3
VexW,
- /* VEX opcode prefix:
- 0: VEX 0x0F opcode prefix.
- 1: VEX 0x0F38 opcode prefix.
- 2: VEX 0x0F3A opcode prefix
- 3: XOP 0x08 opcode prefix.
- 4: XOP 0x09 opcode prefix
- 5: XOP 0x0A opcode prefix.
+ /* Opcode encoding space (values chosen to be usable directly in
+ VEX/XOP mmmmm and EVEX mm fields):
+ 0: Base opcode space.
+ 1: 0F opcode prefix / space.
+ 2: 0F38 opcode prefix / space.
+ 3: 0F3A opcode prefix / space.
+ 5: EVEXMAP5 opcode prefix / space.
+ 6: EVEXMAP6 opcode prefix / space.
+ 8: XOP 08 opcode space.
+ 9: XOP 09 opcode space.
+ A: XOP 0A opcode space.
+ */
+#define SPACE_BASE 0
+#define SPACE_0F 1
+#define SPACE_0F38 2
+#define SPACE_0F3A 3
+#define SPACE_EVEXMAP5 5
+#define SPACE_EVEXMAP6 6
+#define SPACE_XOP08 8
+#define SPACE_XOP09 9
+#define SPACE_XOP0A 0xA
+ OpcodeSpace,
+ /* Opcode prefix (values chosen to be usable directly in
+ VEX/XOP/EVEX pp fields):
+ 0: None
+ 1: Add 0x66 opcode prefix.
+ 2: Add 0xf3 opcode prefix.
+ 3: Add 0xf2 opcode prefix.
*/
-#define VEX0F 0
-#define VEX0F38 1
-#define VEX0F3A 2
-#define XOP08 3
-#define XOP09 4
-#define XOP0A 5
- VexOpcode,
+#define PREFIX_NONE 0
+#define PREFIX_0X66 1
+#define PREFIX_0XF3 2
+#define PREFIX_0XF2 3
+ OpcodePrefix,
/* number of VEX source operands:
0: <= 2 source operands.
1: 2 XOP source operands.
#define XOP2SOURCES 1
#define VEX3SOURCES 2
VexSources,
- /* instruction has VEX 8 bit imm */
- VexImmExt,
- /* Instruction with vector SIB byte:
+ /* Instruction with a mandatory SIB byte:
1: 128bit vector register.
2: 256bit vector register.
3: 512bit vector register.
*/
-#define VecSIB128 1
-#define VecSIB256 2
-#define VecSIB512 3
- VecSIB,
+#define VECSIB128 1
+#define VECSIB256 2
+#define VECSIB512 3
+#define SIBMEM 4
+ SIB,
+
/* SSE to AVX support required */
SSE2AVX,
- /* No AVX equivalent */
- NoAVX,
/* insn has EVEX prefix:
1: 512bit EVEX prefix.
EVex,
/* AVX512 masking support:
- 1: Zeroing-masking.
+ 1: Zeroing or merging masking depending on operands.
2: Merging-masking.
3: Both zeroing and merging masking.
*/
-#define ZEROING_MASKING 1
+#define DYNAMIC_MASKING 1
#define MERGING_MASKING 2
#define BOTH_MASKING 3
Masking,
- /* Input element size of vector insn:
- 0: 32bit.
- 1: 64bit.
- */
- VecESize,
-
- /* Broadcast factor.
- 0: No broadcast.
- 1: 1to16 broadcast.
- 2: 1to8 broadcast.
+ /* AVX512 broadcast support. The number of bytes to broadcast is
+ 1 << (Broadcast - 1):
+ 1: Byte broadcast.
+ 2: Word broadcast.
+ 3: Dword broadcast.
+ 4: Qword broadcast.
*/
-#define NO_BROADCAST 0
-#define BROADCAST_1TO16 1
-#define BROADCAST_1TO8 2
-#define BROADCAST_1TO4 3
-#define BROADCAST_1TO2 4
+#define BYTE_BROADCAST 1
+#define WORD_BROADCAST 2
+#define DWORD_BROADCAST 3
+#define QWORD_BROADCAST 4
Broadcast,
/* Static rounding control is supported. */
/* Supress All Exceptions is supported. */
SAE,
- /* Copressed Disp8*N attribute. */
+ /* Compressed Disp8*N attribute. */
+#define DISP8_SHIFT_VL 7
Disp8MemShift,
/* Default mask isn't allowed. */
*/
ImplicitQuadGroup,
+ /* Two source operands are swapped. */
+ SwapSources,
+
/* Support encoding optimization. */
Optimize,
ATTSyntax,
/* Intel syntax. */
IntelSyntax,
- /* AMD64. */
- AMD64,
- /* Intel64. */
- Intel64,
+ /* ISA64: Don't change the order without other code adjustments.
+ 0: Common to AMD64 and Intel64.
+ 1: AMD64.
+ 2: Intel64.
+ 3: Only in Intel64.
+ */
+#define AMD64 1
+#define INTEL64 2
+#define INTEL64ONLY 3
+ ISA64,
/* The last bitfield in i386_opcode_modifier. */
- Opcode_Modifier_Max
+ Opcode_Modifier_Num
};
typedef struct i386_opcode_modifier
unsigned int w:1;
unsigned int load:1;
unsigned int modrm:1;
- unsigned int shortform:1;
- unsigned int jump:1;
- unsigned int jumpdword:1;
- unsigned int jumpbyte:1;
- unsigned int jumpintersegment:1;
+ unsigned int jump:3;
unsigned int floatmf:1;
unsigned int floatr:1;
- unsigned int size16:1;
- unsigned int size32:1;
- unsigned int size64:1;
+ unsigned int size:2;
unsigned int checkregsize:1;
- unsigned int ignoresize:1;
- unsigned int defaultsize:1;
+ unsigned int distinctdest:1;
+ unsigned int mnemonicsize:2;
+ unsigned int anysize:1;
unsigned int no_bsuf:1;
unsigned int no_wsuf:1;
unsigned int no_lsuf:1;
unsigned int no_qsuf:1;
unsigned int no_ldsuf:1;
unsigned int fwait:1;
- unsigned int isstring:1;
+ unsigned int isstring:2;
+ unsigned int regmem:1;
unsigned int bndprefixok:1;
- unsigned int notrackprefixok:1;
- unsigned int islockable:1;
unsigned int regkludge:1;
unsigned int implicit1stxmm0:1;
- unsigned int hleprefixok:2;
- unsigned int repprefixok:1;
- unsigned int todword:1;
- unsigned int toqword:1;
- unsigned int addrprefixop0:1;
+ unsigned int prefixok:3;
+ unsigned int addrprefixopreg:1;
unsigned int isprefix:1;
unsigned int immext:1;
unsigned int norex64:1;
- unsigned int rex64:1;
unsigned int ugh:1;
unsigned int vex:2;
unsigned int vexvvvv:2;
unsigned int vexw:2;
- unsigned int vexopcode:3;
+ unsigned int opcodespace:4;
+ unsigned int opcodeprefix:2;
unsigned int vexsources:2;
- unsigned int veximmext:1;
- unsigned int vecsib:2;
+ unsigned int sib:3;
unsigned int sse2avx:1;
- unsigned int noavx:1;
unsigned int evex:3;
unsigned int masking:2;
- unsigned int vecesize:1;
unsigned int broadcast:3;
unsigned int staticrounding:1;
unsigned int sae:1;
unsigned int disp8memshift:3;
unsigned int nodefmask:1;
unsigned int implicitquadgroup:1;
+ unsigned int swapsources:1;
unsigned int optimize:1;
unsigned int attmnemonic:1;
unsigned int attsyntax:1;
unsigned int intelsyntax:1;
- unsigned int amd64:1;
- unsigned int intel64:1;
+ unsigned int isa64:2;
} i386_opcode_modifier;
+/* Operand classes. */
+
+#define CLASS_WIDTH 4
+enum operand_class
+{
+ ClassNone,
+ Reg, /* GPRs and FP regs, distinguished by operand size */
+ SReg, /* Segment register */
+ RegCR, /* Control register */
+ RegDR, /* Debug register */
+ RegTR, /* Test register */
+ RegMMX, /* MMX register */
+ RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
+ RegMask, /* Vector Mask register */
+ RegBND, /* Bound register */
+};
+
+/* Special operand instances. */
+
+#define INSTANCE_WIDTH 3
+enum operand_instance
+{
+ InstanceNone,
+ Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
+ RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
+ RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
+ RegB, /* %bl / %bx / %ebx / %rbx */
+};
+
/* Position of operand_type bits. */
enum
{
- /* Register (qualified by Byte, Word, etc) */
- Reg = 0,
- /* MMX register */
- RegMMX,
- /* Vector registers */
- RegSIMD,
- /* Vector Mask registers */
- RegMask,
- /* Control register */
- Control,
- /* Debug register */
- Debug,
- /* Test register */
- Test,
- /* 2 bit segment register */
- SReg2,
- /* 3 bit segment register */
- SReg3,
+ /* Class and Instance */
+ ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
/* 1 bit immediate */
Imm1,
/* 8 bit immediate */
Disp8,
/* 16 bit displacement */
Disp16,
- /* 32 bit displacement */
+ /* 32 bit displacement (64-bit: sign-extended) */
Disp32,
- /* 32 bit signed displacement */
- Disp32S,
/* 64 bit displacement */
Disp64,
- /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
- Acc,
/* Register which can be used for base or index in memory operand. */
BaseIndex,
- /* Register to hold in/out port addr = dx */
- InOutPortReg,
- /* Register to hold shift count = cl */
- ShiftCount,
- /* Absolute address for jump. */
- JumpAbsolute,
- /* String insn operand with fixed es segment */
- EsSeg,
- /* RegMem is for instructions with a modrm byte where the register
- destination operand should be encoded in the mod and regmem fields.
- Normally, it will be encoded in the reg field. We add a RegMem
- flag to the destination register operand to indicate that it should
- be encoded in the regmem field. */
- RegMem,
- /* Memory. */
- Mem,
- /* BYTE memory. */
+ /* BYTE size. */
Byte,
- /* WORD memory. 2 byte */
+ /* WORD size. 2 byte */
Word,
- /* DWORD memory. 4 byte */
+ /* DWORD size. 4 byte */
Dword,
- /* FWORD memory. 6 byte */
+ /* FWORD size. 6 byte */
Fword,
- /* QWORD memory. 8 byte */
+ /* QWORD size. 8 byte */
Qword,
- /* TBYTE memory. 10 byte */
+ /* TBYTE size. 10 byte */
Tbyte,
- /* XMMWORD memory. */
+ /* XMMWORD size. */
Xmmword,
- /* YMMWORD memory. */
+ /* YMMWORD size. */
Ymmword,
- /* ZMMWORD memory. */
+ /* ZMMWORD size. */
Zmmword,
+ /* TMMWORD size. */
+ Tmmword,
/* Unspecified memory size. */
Unspecified,
- /* Any memory size. */
- Anysize,
-
- /* Vector 4 bit immediate. */
- Vec_Imm4,
- /* Bound register. */
- RegBND,
-
- /* The last bitfield in i386_operand_type. */
- OTMax
+ /* The number of bits in i386_operand_type. */
+ OTNum
};
#define OTNumOfUints \
- (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
+ ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
#define OTNumOfBits \
(OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
/* If you get a compiler error for zero width of the unused field,
comment it out. */
-#define OTUnused (OTMax + 1)
+#define OTUnused OTNum
typedef union i386_operand_type
{
struct
{
- unsigned int reg:1;
- unsigned int regmmx:1;
- unsigned int regsimd:1;
- unsigned int regmask:1;
- unsigned int control:1;
- unsigned int debug:1;
- unsigned int test:1;
- unsigned int sreg2:1;
- unsigned int sreg3:1;
+ unsigned int class:CLASS_WIDTH;
+ unsigned int instance:INSTANCE_WIDTH;
unsigned int imm1:1;
unsigned int imm8:1;
unsigned int imm8s:1;
unsigned int disp8:1;
unsigned int disp16:1;
unsigned int disp32:1;
- unsigned int disp32s:1;
unsigned int disp64:1;
- unsigned int acc:1;
unsigned int baseindex:1;
- unsigned int inoutportreg:1;
- unsigned int shiftcount:1;
- unsigned int jumpabsolute:1;
- unsigned int esseg:1;
- unsigned int regmem:1;
- unsigned int mem:1;
unsigned int byte:1;
unsigned int word:1;
unsigned int dword:1;
unsigned int xmmword:1;
unsigned int ymmword:1;
unsigned int zmmword:1;
+ unsigned int tmmword:1;
unsigned int unspecified:1;
- unsigned int anysize:1;
- unsigned int vec_imm4:1;
- unsigned int regbnd:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
#endif
/* instruction name sans width suffix ("mov" for movl insns) */
char *name;
- /* how many operands */
- unsigned int operands;
+ /* Bitfield arrangement is such that individual fields can be easily
+ extracted (in native builds at least) - either by at most a masking
+ operation (base_opcode, operands), or by just a (signed) right shift
+ (extension_opcode). Please try to maintain this property. */
/* base_opcode is the fundamental opcode byte without optional
prefix(es). */
- unsigned int base_opcode;
+ unsigned int base_opcode:16;
#define Opcode_D 0x2 /* Direction bit:
set if Reg --> Regmem;
unset if Regmem --> Reg. */
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
+#define Opcode_ExtD 0x1 /* Direction bit for extended opcode space insns. */
+#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
+/* The next value is arbitrary, as long as it's non-zero and distinct
+ from all other values above. */
+#define Opcode_VexW 0xf /* Operand order controlled by VEX.W. */
+
+ /* how many operands */
+ unsigned int operands:3;
+
+ /* spare bits */
+ unsigned int :4;
+
+/* (Fake) base opcode value for pseudo prefixes. */
+#define PSEUDO_PREFIX 0
/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
AMD 3DNow! instructions.
If this template has no extension opcode (the usual case) use None
Instructions */
- unsigned int extension_opcode;
-#define None 0xffff /* If no extension_opcode is possible. */
-
- /* Opcode length. */
- unsigned char opcode_length;
-
- /* cpu feature flags */
- i386_cpu_flags cpu_flags;
+ signed int extension_opcode:9;
+#define None (-1) /* If no extension_opcode is possible. */
+
+/* Pseudo prefixes. */
+#define Prefix_Disp8 0 /* {disp8} */
+#define Prefix_Disp16 1 /* {disp16} */
+#define Prefix_Disp32 2 /* {disp32} */
+#define Prefix_Load 3 /* {load} */
+#define Prefix_Store 4 /* {store} */
+#define Prefix_VEX 5 /* {vex} */
+#define Prefix_VEX3 6 /* {vex3} */
+#define Prefix_EVEX 7 /* {evex} */
+#define Prefix_REX 8 /* {rex} */
+#define Prefix_NoOptimize 9 /* {nooptimize} */
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
the same instruction */
i386_opcode_modifier opcode_modifier;
+ /* cpu feature flags */
+ i386_cpu_flags cpu_flags;
+
/* operand_types[i] describes the type of operand i. This is made
by OR'ing together all of the possible type masks. (e.g.
'operand_types[i] = Reg|Imm' specifies that operand i can be
/* these are for register name --> number & type hash lookup */
typedef struct
{
- char *reg_name;
+ const char *reg_name;
i386_operand_type reg_type;
unsigned char reg_flags;
#define RegRex 0x1 /* Extended register. */
#define RegRex64 0x2 /* Extended 8 bit register. */
#define RegVRex 0x4 /* Extended vector register. */
unsigned char reg_num;
-#define RegRip ((unsigned char ) ~0)
-#define RegEip (RegRip - 1)
+#define RegIP ((unsigned char ) ~0)
/* EIZ and RIZ are fake index registers. */
-#define RegEiz (RegEip - 1)
-#define RegRiz (RegEiz - 1)
+#define RegIZ (RegIP - 1)
/* FLAT is a fake segment register (Intel mode). */
#define RegFlat ((unsigned char) ~0)
signed char dw2_regnum[2];
}
reg_entry;
-/* Entries in i386_regtab. */
-#define REGNAM_AL 1
-#define REGNAM_AX 25
-#define REGNAM_EAX 41
-
extern const reg_entry i386_regtab[];
extern const unsigned int i386_regtab_size;
-
-typedef struct
-{
- char *seg_name;
- unsigned int seg_prefix;
-}
-seg_entry;
-
-extern const seg_entry cs;
-extern const seg_entry ds;
-extern const seg_entry ss;
-extern const seg_entry es;
-extern const seg_entry fs;
-extern const seg_entry gs;
+extern const unsigned char i386_seg_prefixes[6];
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