-/* Machine-dependent code which would otherwise be in inflow.c and core.c,
- for GDB, the GNU debugger.
- Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
- This code is for the sparc cpu.
+/* Target-dependent code for the SPARC for GDB, the GNU debugger.
+ Copyright 1986, 1987, 1989, 1991, 1992 Free Software Foundation, Inc.
This file is part of GDB.
-GDB is free software; you can redistribute it and/or modify
+This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
-GDB is distributed in the hope that it will be useful,
+This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with GDB; see the file COPYING. If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+along with this program; if not, write to the Free Software
+Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
-#include <stdio.h>
#include "defs.h"
-#include "param.h"
#include "frame.h"
#include "inferior.h"
#include "obstack.h"
#include "target.h"
#include "ieee-float.h"
-#include <sys/param.h>
-#include <sys/dir.h>
-#include <sys/user.h>
-#include <signal.h>
-#include <sys/ioctl.h>
-#include <fcntl.h>
-
#include <sys/ptrace.h>
-#include <machine/reg.h>
-
-#include <sys/file.h>
-#include <sys/stat.h>
-#include <sys/core.h>
#include "gdbcore.h"
typedef enum
{
- Error, not_branch, bicc, bicca, ba, baa, ticc, ta,
+ Error, not_branch, bicc, bicca, ba, baa, ticc, ta
} branch_type;
/* Simulate single-step ptrace call for sun4. Code written by Gary
int one_stepped;
+/* single_step() is called just before we want to resume the inferior,
+ if we want to single-step it but there is no hardware or kernel single-step
+ support (as on all SPARCs). We find all the possible targets of the
+ coming instruction and breakpoint them.
+
+ single_step is also called just after the inferior stops. If we had
+ set up a simulated single-step, we undo our damage. */
+
void
-single_step (signal)
- int signal;
+single_step (pid)
+ int pid; /* ignored */
{
branch_type br, isannulled();
CORE_ADDR pc;
target_insert_breakpoint (target, break_mem[2]);
}
- /* Let it go */
- ptrace (7, inferior_pid, 1, signal);
+ /* We are ready to let it go */
one_stepped = 1;
return;
}
}
}
\f
-/*
- * Find the pc saved in frame FRAME.
- */
+#define FRAME_SAVED_L0 0 /* Byte offset from SP */
+#define FRAME_SAVED_I0 32 /* Byte offset from SP */
+
+CORE_ADDR
+sparc_frame_chain (thisframe)
+ FRAME thisframe;
+{
+ CORE_ADDR retval;
+ int err;
+ CORE_ADDR addr;
+
+ addr = thisframe->frame + FRAME_SAVED_I0 +
+ REGISTER_RAW_SIZE(FP_REGNUM) * (FP_REGNUM - I0_REGNUM);
+ err = target_read_memory (addr, (char *) &retval, sizeof (CORE_ADDR));
+ if (err)
+ return 0;
+ SWAP_TARGET_AND_HOST (&retval, sizeof (retval));
+ return retval;
+}
+
+CORE_ADDR
+sparc_extract_struct_value_address (regbuf)
+ char regbuf[REGISTER_BYTES];
+{
+ /* FIXME, handle byte swapping */
+ return read_memory_integer (((int *)(regbuf))[SP_REGNUM]+(16*4),
+ sizeof (CORE_ADDR));
+}
+
+/* Find the pc saved in frame FRAME. */
+
CORE_ADDR
frame_saved_pc (frame)
FRAME frame;
{
CORE_ADDR prev_pc;
- /* If it's at the bottom, the return value's stored in i7/rp */
- if (get_current_frame () == frame)
- prev_pc = GET_RWINDOW_REG (read_register (SP_REGNUM), rw_in[7]);
- else
- /* Wouldn't this always work? This would allow this routine to
- be completely a macro. */
- prev_pc = GET_RWINDOW_REG (frame->bottom, rw_in[7]);
-
+ if (get_current_frame () == frame) /* FIXME, debug check. Remove >=gdb-4.6 */
+ {
+ if (read_register (SP_REGNUM) != frame->bottom) abort();
+ }
+
+ read_memory ((CORE_ADDR) (frame->bottom + FRAME_SAVED_I0 +
+ REGISTER_RAW_SIZE(I7_REGNUM) * (I7_REGNUM - I0_REGNUM)),
+ (char *) &prev_pc,
+ sizeof (CORE_ADDR));
+
+ SWAP_TARGET_AND_HOST (&prev_pc, sizeof (prev_pc));
return PC_ADJUST (prev_pc);
}
fatal ("internal: create_new_frame returned invalid frame id");
fid->bottom = stack;
-
+ fid->pc = FRAME_SAVED_PC (fid);
return fid;
}
restore_inferior_status (&inf_status);
}
-/* This routine should be more specific in it's actions; making sure
- that it uses the same register in the initial prologue section.
- Also, FIXME-SOON, it should recognize leaf functions as ones without
- a SAVE in the prologue, and pass that info back to the caller so the
- PC and arguments can be properly located. */
+/* Given a pc value, skip it forward past the function prologue by
+ disassembling instructions that appear to be a prologue.
+
+ If FRAMELESS_P is set, we are only testing to see if the function
+ is frameless. This allows a quicker answer.
+
+ This routine should be more specific in its actions; making sure
+ that it uses the same register in the initial prologue section. */
CORE_ADDR
-skip_prologue (pc)
- CORE_ADDR pc;
+skip_prologue (start_pc, frameless_p)
+ CORE_ADDR start_pc;
+ int frameless_p;
{
union
{
int i;
} x;
int dest = -1;
+ CORE_ADDR pc = start_pc;
x.i = read_memory_integer (pc, 4);
/* Recognize an add immediate value to register to either %g1 or
the destination register recorded above. Actually, this might
- well recognize several different arithmetic operations. */
+ well recognize several different arithmetic operations.
+ It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
+ followed by "save %sp, %g1, %sp" is a valid prologue (Not that
+ I imagine any compiler really does that, however). */
if (x.add.op == 2 && x.add.i && (x.add.rd == 1 || x.add.rd == dest))
{
pc += 4;
if (x.add.op == 2 && (x.add.op3 ^ 32) == 28)
{
pc += 4;
+ if (frameless_p) /* If the save is all we care about, */
+ return pc; /* return before doing more work */
x.i = read_memory_integer (pc, 4);
}
+ else
+ {
+ /* Without a save instruction, it's not a prologue. */
+ return start_pc;
+ }
/* Now we need to recognize stores into the frame from the input
registers. This recognizes all non alternate stores of input
read_pc ()));
}
+/* On the Sun 4 under SunOS, the compile will leave a fake insn which
+ encodes the structure size being returned. If we detect such
+ a fake insn, step past it. */
+
+CORE_ADDR
+sparc_pc_adjust(pc)
+ CORE_ADDR pc;
+{
+ long insn;
+ int err;
+
+ err = target_read_memory (pc + 8, (char *)&insn, sizeof(long));
+ SWAP_TARGET_AND_HOST (&insn, sizeof(long));
+ if ((err == 0) && (insn & 0xfffffe00) == 0)
+ return pc+12;
+ else
+ return pc+8;
+}
+
+
/* Structure of SPARC extended floating point numbers.
This information is not currently used by GDB, since no current SPARC
implementations support extended float. */
-const struct ext_format ext_format_sparc[] = {
+const struct ext_format ext_format_sparc = {
/* tot sbyte smask expbyte manbyte */
- { 16, 0, 0x80, 0,1, 4,8 }, /* sparc */
+ 16, 0, 0x80, 0,1, 4,8, /* sparc */
};
+
+/* Figure out where the longjmp will land. We expect that we have just entered
+ longjmp and haven't yet setup the stack frame, so the args are still in the
+ output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
+ extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
+ This routine returns true on success */
+
+int
+get_longjmp_target(pc)
+ CORE_ADDR *pc;
+{
+ CORE_ADDR jb_addr;
+
+ jb_addr = read_register(O0_REGNUM);
+
+ if (target_read_memory(jb_addr + JB_PC * JB_ELEMENT_SIZE, (char *) pc,
+ sizeof(CORE_ADDR)))
+ return 0;
+
+ SWAP_TARGET_AND_HOST(pc, sizeof(CORE_ADDR));
+
+ return 1;
+}
projects / binutils.git / blobdiff