struct cmd_list_element *,
const char *);
-static void convert_from_extended (const struct floatformat *, const void *,
- void *, int);
-static void convert_to_extended (const struct floatformat *, void *,
- const void *, int);
-
static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
struct regcache *regcache,
int regnum, gdb_byte *buf);
case TYPE_CODE_SET:
case TYPE_CODE_RANGE:
case TYPE_CODE_REF:
+ case TYPE_CODE_RVALUE_REF:
case TYPE_CODE_CHAR:
case TYPE_CODE_BOOL:
return TYPE_LENGTH (t);
internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
}
-/* NOTE: cagney/2001-08-20: Both convert_from_extended() and
- convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
- It is thought that this is is the floating-point register format on
- little-endian systems. */
-
-static void
-convert_from_extended (const struct floatformat *fmt, const void *ptr,
- void *dbl, int endianess)
-{
- DOUBLEST d;
-
- if (endianess == BFD_ENDIAN_BIG)
- floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
- else
- floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
- ptr, &d);
- floatformat_from_doublest (fmt, &d, dbl);
-}
-
-static void
-convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
- int endianess)
-{
- DOUBLEST d;
-
- floatformat_to_doublest (fmt, ptr, &d);
- if (endianess == BFD_ENDIAN_BIG)
- floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
- else
- floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
- &d, dbl);
-}
-
/* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
the buffer to be NEW_LEN bytes ending at ENDADDR. Return
NULL if an error occurs. BUF is freed. */
single-step support. We find the target of the coming instructions
and breakpoint them. */
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
arm_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct arm_get_next_pcs next_pcs_ctx;
- CORE_ADDR pc;
- int i;
- VEC (CORE_ADDR) *next_pcs = NULL;
- struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
arm_get_next_pcs_ctor (&next_pcs_ctx,
&arm_get_next_pcs_ops,
0,
regcache);
- next_pcs = arm_get_next_pcs (&next_pcs_ctx);
-
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
- {
- pc = gdbarch_addr_bits_remove (gdbarch, pc);
- VEC_replace (CORE_ADDR, next_pcs, i, pc);
- }
+ std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
- discard_cleanups (old_chain);
+ for (CORE_ADDR &pc_ref : next_pcs)
+ pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref);
return next_pcs;
}
unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
unsigned int rn = bits (insn, 16, 19);
- if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
+ if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0)
return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
- else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
+ else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1)
return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
else if ((op1 & 0x60) == 0x20)
return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
else
info->symbols = NULL;
- if (info->endian == BFD_ENDIAN_BIG)
- return print_insn_big_arm (memaddr, info);
- else
- return print_insn_little_arm (memaddr, info);
+ /* GDB is able to get bfd_mach from the exe_bfd, info->mach is
+ accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise,
+ opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger
+ the assert on the mismatch of info->mach and bfd_get_mach (exec_bfd)
+ in default_print_insn. */
+ if (exec_bfd != NULL)
+ info->flags |= USER_SPECIFIED_MACHINE_TYPE;
+
+ return default_print_insn (memaddr, info);
}
/* The following define instruction sequences that will cause ARM
if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0)
{
struct arm_get_next_pcs next_pcs_ctx;
- CORE_ADDR pc;
- int i;
- VEC (CORE_ADDR) *next_pcs = NULL;
- struct cleanup *old_chain
- = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
arm_get_next_pcs_ctor (&next_pcs_ctx,
&arm_get_next_pcs_ops,
0,
regcache);
- next_pcs = arm_get_next_pcs (&next_pcs_ctx);
+ std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
/* If MEMADDR is the next instruction of current pc, do the
software single step computation, and get the thumb mode by
the destination address. */
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
+ for (CORE_ADDR pc : next_pcs)
{
if (UNMAKE_THUMB_ADDR (pc) == *pcptr)
{
- do_cleanups (old_chain);
-
if (IS_THUMB_ADDR (pc))
{
*pcptr = MAKE_THUMB_ADDR (*pcptr);
return ARM_BP_KIND_ARM;
}
}
-
- do_cleanups (old_chain);
}
return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
bfd_byte tmpbuf[FP_REGISTER_SIZE];
regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
- convert_from_extended (floatformat_from_type (type), tmpbuf,
- valbuf, gdbarch_byte_order (gdbarch));
+ convert_typed_floating (tmpbuf, arm_ext_type (gdbarch),
+ valbuf, type);
}
break;
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_PTR
- || TYPE_CODE (type) == TYPE_CODE_REF
+ || TYPE_IS_REFERENCE (type)
|| TYPE_CODE (type) == TYPE_CODE_ENUM)
{
/* If the type is a plain integer, then the access is
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
- gdb_byte buf[MAX_REGISTER_SIZE];
+ gdb_byte buf[FP_REGISTER_SIZE];
switch (gdbarch_tdep (gdbarch)->fp_model)
{
case ARM_FLOAT_FPA:
- convert_to_extended (floatformat_from_type (type), buf, valbuf,
- gdbarch_byte_order (gdbarch));
+ convert_typed_floating (valbuf, type, buf, arm_ext_type (gdbarch));
regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
break;
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_PTR
- || TYPE_CODE (type) == TYPE_CODE_REF
+ || TYPE_IS_REFERENCE (type)
|| TYPE_CODE (type) == TYPE_CODE_ENUM)
{
if (TYPE_LENGTH (type) <= 4)
{
/* Use the name suffix to determine which register contains the
target PC. */
- static char *table[15] =
+ static const char *table[15] =
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "sl", "fp", "ip", "sp", "lr"
};
char *options = get_disassembler_options (gdbarch);
const char *style = "";
int len = 0;
- char *opt;
+ const char *opt;
FOR_EACH_DISASSEMBLER_OPTION (opt, options)
if (CONST_STRNEQ (opt, "reg-names-"))
/* On ARM targets char defaults to unsigned. */
set_gdbarch_char_signed (gdbarch, 0);
+ /* wchar_t is unsigned under the AAPCS. */
+ if (tdep->arm_abi == ARM_ABI_AAPCS)
+ set_gdbarch_wchar_signed (gdbarch, 0);
+ else
+ set_gdbarch_wchar_signed (gdbarch, 1);
+
/* Note: for displaced stepping, this includes the breakpoint, and one word
of additional scratch space. This setting isn't used for anything beside
displaced stepping at present. */
(unsigned long) tdep->lowest_pc);
}
+#if GDB_SELF_TEST
namespace selftests
{
static void arm_record_test (void);
}
-
-extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
+#endif
void
_initialize_arm_tdep (void)
&setdebuglist, &showdebuglist);
#if GDB_SELF_TEST
- register_self_test (selftests::arm_record_test);
+ selftests::register_test ("arm-record", selftests::arm_record_test);
#endif
}
case 9: /* fall through */
case 11:
/* CBNZ, CBZ */
- return -1;
break;
case 2:
/* SXTH, SXTB, UXTH, UXTB */
break;
case 10:
/* REV, REV16, REVSH */
- return -1;
+ record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2);
+ thumb_insn_r->reg_rec_count = 1;
break;
case 12: /* fall through */
case 13:
return -1;
}
+namespace {
/* Abstract memory reader. */
class abstract_memory_reader
}
};
+} // namespace
+
/* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
and positive val on fauilure. */
projects / binutils.git / blobdiff