+
+ * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
+
+
+ * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
+
+
+ * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
+ register values greater than 8.
+ (IS_RESERVEDREG, allreg, mostreg): New helpers.
+ (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
+ (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
+ (decode_CC2dreg_0): Check valid CC register number.
+
+
+ * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
+
+
+ * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
+ (reg_names): Likewise.
+ (decode_statbits): Likewise; while reformatting to make manageable.
+
+
+ * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
+ (decode_pseudoOChar_0): New function.
+ (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
+
+
+ * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
+ LSHIFT instead of SHIFT.
+
+
+ * bfin-dis.c (constant_formats): Constify the whole structure.
+ (fmtconst): Add const to return value.
+ (reg_names): Mark const.
+ (decode_multfunc): Mark s0/s1 as const.
+ (decode_macfunc): Mark a/sop as const.
+
+
+ * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
+
+
+ * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
+ "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
+
+
+ * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
+ dlx_insn_type array.
+
+
+ PR binutils/11960
+ * i386-dis.c (sIv): New.
+ (dis386): Replace Iq with sIv on "pushT".
+ (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
+ (x86_64_table): Replace {T|}/{P|} with P.
+ (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
+ (OP_sI): Update v_mode. Remove w_mode.
+
+
+ * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
+ on E500 and E500MC.
+
+
+ * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
+ prefetchw.
+
+
+ * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
+ to processor flags for PENTIUMPRO processors and later.
+ * i386-opc.h (enum): Add CpuNop.
+ (i386_cpu_flags): Add cpunop bit.
+ * i386-opc.tbl: Change nop cpu_flags.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+
+ * i386-opc.h (enum): Fix typos in comments.
+
+
+ * disassemble.c: Formatting.
+ (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
+
+
+ * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
+ * i386-tbl.h: Regenerated.
+
+
+ * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
+
+ * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
+ * i386-tbl.h: Regenerated.
+
+
+ * rx-decode.opc (SRR): New.
+ (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
+ r0,r0) and NOP3 (max r0,r0) special cases.
+ * rx-decode.c: Regenerate.
+
+
+ * i386-dis.c: Add 0F to VEX opcode enums.
+
+
+ * rx-decode.opc (store_flags): Remove, replace with F_* macros.
+ (rx_decode_opcode): Likewise.
+ * rx-decode.c: Regenerate.
+
+
+ * v850-dis.c (v850_sreg_names): Updated structure for system
+ registers.
+ (float_cc_names): new structure for condition codes.
+ (print_value): Update the function that prints value.
+ (get_operand_value): New function to get the operand value.
+ (disassemble): Updated to handle the disassembly of instructions.
+ (print_insn_v850): Updated function to print instruction for different
+ families.
+ * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
+ extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
+ extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
+ insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
+ extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
+ extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
+ extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
+ insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
+ (insert_d8_7, insert_d5_4, insert_i5div): Remove.
+ (v850_operands): Update with the relocation name. Also update
+ the instructions with specific set of processors.
+
+
+ * arm-dis.c (print_insn_arm): Add cases for printing more
+ symbolic operands.
+ (print_insn_thumb32): Likewise.
+
+
+ * mips-dis.c (print_insn_mips): Correct branch instruction type
+ determination.
+
+
+ * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
+ type and delay slot determination.
+ (print_insn_mips16): Extend branch instruction type and delay
+ slot determination to cover all instructions.
+ * mips16-opc.c (BR): Remove macro.
+ (UBR, CBR): New macros.
+ (mips16_opcodes): Update branch annotation for "b", "beqz",
+ "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
+ and "jrc".
+
+
+ AVX Programming Reference (June, 2010)
+ * i386-dis.c (mod_table): Replace rdrnd with rdrand.
+ * i386-opc.tbl: Likewise.
+ * i386-tbl.h: Regenerated.
+
+
+ * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
+
+
+ * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
+ ppc_cpu_t before inverting.
+ (ppc_parse_cpu): Likewise.
+ (print_insn_powerpc): Likewise.
+
+
+ * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
+ * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
+ (PPC64, MFDEC2): Update.
+ (NON32, NO371): Define.
+ (powerpc_opcode): Update to not use old opcode flags, and avoid
+ -m601 duplicates.
+
+
+ * m32c-ibld.c: Regenerate.
+
+
+ * ppc-opc.c (PWR2COM): Define.
+ (PPCPWR2): Add PPC_OPCODE_COMMON.
+ (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
+ "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
+ "rac" from -mcom.
+
+
+ AVX Programming Reference (June, 2010)
+ * i386-dis.c (PREFIX_0FAE_REG_0): New.
+ (PREFIX_0FAE_REG_1): Likewise.
+ (PREFIX_0FAE_REG_2): Likewise.
+ (PREFIX_0FAE_REG_3): Likewise.
+ (PREFIX_VEX_3813): Likewise.
+ (PREFIX_VEX_3A1D): Likewise.
+ (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
+ PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
+ PREFIX_VEX_3A1D.
+ (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
+ (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
+ PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
+
+ * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
+ CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
+ (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
+
+ * i386-opc.h (CpuXsaveopt): New.
+ (CpuFSGSBase): Likewise.
+ (CpuRdRnd): Likewise.
+ (CpuF16C): Likewise.
+ (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
+ cpuf16c.
+
+ * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
+ wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+
+ * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
+ and mtocrf on EFS.
+
+
+ * maxq-dis.c: Delete file.
+ * Makefile.am: Remove references to maxq.
+ * configure.in: Likewise.
+ * disassemble.c: Likewise.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+
+ * mep-dis.c: Regenerate.
+
+
+ * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
+
+
+ * arc-dis.c (arc_sprintf): Delete set but unused variables.
+ (decodeInstr): Likewise.
+ * dlx-dis.c (print_insn_dlx): Likewise.
+ * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
+ * maxq-dis.c (check_move, print_insn): Likewise.
+ * mep-dis.c (mep_examine_ivc2_insns): Likewise.
+ * msp430-dis.c (msp430_branchinstr): Likewise.
+ * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
+ * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
+ * sparc-dis.c (print_insn_sparc): Likewise.
+ * fr30-asm.c: Regenerate.
+ * frv-asm.c: Regenerate.
+ * ip2k-asm.c: Regenerate.
+ * iq2000-asm.c: Regenerate.
+ * lm32-asm.c: Regenerate.
+ * m32c-asm.c: Regenerate.
+ * m32r-asm.c: Regenerate.
+ * mep-asm.c: Regenerate.
+ * mt-asm.c: Regenerate.
+ * openrisc-asm.c: Regenerate.
+ * xc16x-asm.c: Regenerate.
+ * xstormy16-asm.c: Regenerate.
+
+
+ PR gas/11673
+ * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
+
+
+ PR binutils/11676
+ * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
+
+
+ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
+ e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
+ * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
+ touch floating point regs and are enabled by COM, PPC or PPCCOM.
+ Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
+ Treat lwsync as msync on e500.
+
+
+ * arm-dis.c (thumb-opcodes): Add disassembly for movs.
+
+
+ * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
+ constants is the same on 32-bit and 64-bit hosts.
+
+
+ * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
+ .short directives so that they can be reassembled.
+
+
+ * mips-opc.c: Change membership to I1 for instructions ssnop and
+ ehb.
+
+
+ * i386-dis.c (sib): New.
+ (get_sib): Likewise.
+ (print_insn): Call get_sib.
+ OP_E_memory): Use sib.
+
+
+ * mips-dis.c (mips_arch): Remove INSN_MIPS16.
+ * mips-opc.c (I16): Remove.
+ (mips_builtin_op): Reclassify jalx.
+
+
+ * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
+ divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
+
+
+ * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
+
+
+ * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
+ format.
+ (print_insn_thumb16): Add support for new %W format.
+
+
+ * Makefile.in: Regenerate with automake 1.11.1.
+ * aclocal.m4: Ditto.
+
+
+ * po/es.po: Updated Spanish translation.
+
+
+ * po/opcodes.pot: Updated by the Translation project.
+ * po/vi.po: Updated Vietnamese translation.
+
+
+ * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
+ bits in opcode.
+
+
+ * i386-dis.c (print_insn): Remove unused variable op.
+ (OP_sI): Remove unused variable mask.
+
+
+ * configure: Regenerate.
+
+
+ * ppc-opc.c (RBOPT): New define.
+ ("dccci"): Enable for PPCA2. Make operands optional.
+ ("iccci"): Likewise. Do not deprecate for PPC476.
+
* cr16-opc.c (cr16_instruction): Fix typo in comment.
projects / binutils.git / blobdiff