+
+ * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to
+ accept WordReg.
+
+
+ * mips.h (OPCODE_IS_MEMBER): Remove extra space.
+
+
+ * mmix.h: New file.
+
+
+ * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end
+ of the expression, to make source code merging easier.
+
+
+ * mips.h: Sort coprocessor instruction argument characters
+ in comment, add a few more words of description for "H".
+
+
+ * mips.h (INSN_SB1): New cpu-specific instruction bit.
+ (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
+ if cpu is CPU_SB1.
+
+
+ * ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
+
+
+ * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New
+ opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403
+ instructions, respectively.
+
+
+ * v850.h: Remove spurious comment.
+
+
+ * h8300.h: Fix compile time warning messages
+
+
+ * alpha.h (struct alpha_operand): Pack elements into bitfields.
+
+
+ * mips.h: Remove CPU_MIPS32_4K.
+
+
+ * ppc.h (PPC_OPERAND_DS): Define.
+
+
+ * d30v.h: Fix declaration of reg_name_cnt.
+
+ * d10v.h: Fix declaration of d10v_reg_name_cnt.
+
+ * arc.h: Add prototypes from opcodes/arc-opc.c.
+
+
+ * mips.h (INSN_10000): Define.
+ (OPCODE_IS_MEMBER): Check for INSN_10000.
+
+
+ * ppc.h: Revert 2001-08-08.
+
+
+ * ppc.h (struct powerpc_operand): New field `reloc'.
+
+
+ * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
+ (cgen_cpu_desc): Ditto.
+
+
+ * m88k.h: Clean up and reformat. Remove unused code.
+
+
+ * cgen.h (cgen_keyword): Add nonalpha_chars field.
+
+
+ * mips.h (CPU_R12000): Define.
+
+
+ * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
+
* mips.h (INSN_ISA_MASK): Define.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
-
+
* mips.h: Fix formatting.
(ISA_UNKNOWN): New constant to indicate unknown ISA.
(ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
ISA_MIPS32): New constants, defined to be the mask of INSN_*
- constants available at that ISA level.
+ constants available at that ISA level.
(CPU_UNKNOWN): New constant to indicate unknown CPU.
(CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
define it with a unique value.
constant meanings.
* mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
- definitions.
+ definitions.
* mips.h (CPU_SB1): New constant.
* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
-
+
* mips.h: Use defines instead of hard-coded processor numbers.
(CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
- CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
+ CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
CPU_4KC, CPU_4KM, CPU_4KP): Define..
(OPCODE_IS_MEMBER): Use new defines.
- (OP_MASK_SEL, OP_SH_SEL): Define.
+ (OP_MASK_SEL, OP_SH_SEL): Define.
(OP_MASK_CODE20, OP_SH_CODE20): Define.
- Add 'P' to used characters.
- Use 'H' for coprocessor select field.
+ Add 'P' to used characters.
+ Use 'H' for coprocessor select field.
Use 'm' for 20 bit breakpoint code.
- Document new arg characters and add to used characters.
- (INSN_MIPS32): New define for MIPS32 extensions.
- (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
+ Document new arg characters and add to used characters.
+ (INSN_MIPS32): New define for MIPS32 extensions.
+ (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
(CGEN_CPU_TABLE): flags: new field.
Add prototypes for new functions.
-
+
* i386.h: Add some more UNIXWARE_COMPAT comments.
* hppa.h (pa_opcodes): Use 'fX' for first register operand
- in xmpyu.
+ in xmpyu.
* hppa.h (pa_opcodes): Fix mask for probe and probei.
* hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
- * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
+ * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
* hppa.h (pa_opcodes): Move integer arithmetic instructions after
- integer logical instructions.
+ integer logical instructions.
- * hppa.h (pa_opcodes): Add second entry for "comb", "comib",
+ * hppa.h (pa_opcodes): Add second entry for "comb", "comib",
"addb", and "addib" to be used by the disassembler.
(CGEN_INSN_ATTR): New type.
-
+
* i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define.
(x_FP, d_FP, dls_FP, sldx_FP): Define.
Change *Suf definitions to include x and d suffixes.
The following is part of a change made by Edith Epstein
- changes by HP; HP did not create ChangeLog entries.
+ changes by HP; HP did not create ChangeLog entries.
* hppa.h (completer_chars): list of chars to not put a space
- after.
+ after.
* i386.h (i386_optab): Permit w suffix on processor control and
- status word instructions.
+ status word instructions.
* hppa.h: Add "fid".
-
+
* mn10300.h: Add "machine" field for instructions.
(MN103, AM30): Define machine types.
-
+
* i386.h: Use FP, not sl_Suf, for fxsave and fxrstor.
* tic30.h: New file.
* cgen.h: Add prototypes for cgen_save_fixups(),
cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype
* alpha.h: Don't include "bfd.h"; private relocation types are now
- negative to minimize problems with shared libraries. Organize
- instruction subsets by AMASK extensions and PALcode
- implementation.
+ negative to minimize problems with shared libraries. Organize
+ instruction subsets by AMASK extensions and PALcode
+ implementation.
(struct alpha_operand): Move flags slot for better packing.
* v850.h (v850_operands): Add insert and extract fields, pointers
- to functions used to handle unusual operand encoding.
+ to functions used to handle unusual operand encoding.
(V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC,
- V850_OPERAND_SIGNED): Defined.
+ V850_OPERAND_SIGNED): Defined.
* mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
- OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
- OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
- OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
- OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
- Defined.
+ OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
+ OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
+ OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
+ OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
+ Defined.
* d10v.h: Add some additional defines to support the
- assembler in determining which operations can be done in parallel.
+ assembler in determining which operations can be done in parallel.
* d10v.h: Changes for divs, parallel-only instructions, and
- signed numbers.
+ signed numbers.
- * m68k.h (mcf5200): New macro.
+ * m68k.h (mcf5200): New macro.
Document names of coldfire control registers.
* mips.h: Added INSN_4100 flag to mark NEC VR4100 specific
- instructions.
+ instructions.
projects / binutils.git / blobdiff