#define COD INSN_COPROC_MOVE_DELAY
#define CLD INSN_COPROC_MEMORY_DELAY
#define CBL INSN_COND_BRANCH_LIKELY
+#define TRAP INSN_TRAP
+#define SM INSN_STORE_MEMORY
#define WR_d INSN_WRITE_GPR_D
#define WR_t INSN_WRITE_GPR_T
#define I2 INSN_ISA2
#define I3 INSN_ISA3
+#define P3 INSN_4650
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
{"li", "t,j", 0x24000000, 0xffe00000, WR_t }, /* addiu */
{"li", "t,i", 0x34000000, 0xffe00000, WR_t }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO },
-{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s }, /* addu */
-{"b", "p", 0x10000000, 0xffff0000, UBD }, /* beq 0,0 */
-{"b", "p", 0x40100000, 0xffff0000, UBD }, /* bgez 0 */
-{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31 }, /* bgezal 0 */
+/* dli is used on Irix 6 for a 64 bit load--our li can do that. */
+{"dli", "t,j", 0x24000000, 0xffe00000, WR_t }, /* addiu */
+{"dli", "t,i", 0x34000000, 0xffe00000, WR_t }, /* ori */
+{"dli", "t,I", 0, (int) M_LI, INSN_MACRO },
+{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s },/* or */
+{"b", "p", 0x10000000, 0xffff0000, UBD },/* beq 0,0 */
+{"b", "p", 0x04010000, 0xffff0000, UBD },/* bgez 0 */
+{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31 },/* bgezal 0*/
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO },
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S },
{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC },
{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC|I2 },
{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s },
-{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBD|RD_s|I2 },
+{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s|I2 },
{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t },
{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO },
{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t|I2},
{"bgeul", "s,t,p", 2, (int) M_BGEUL, INSN_MACRO },
{"bgeul", "s,I,p", 2, (int) M_BGEUL_I, INSN_MACRO },
{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s },
-{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBD|RD_s|I2 },
+{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s|I2 },
{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31 },
-{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBD|RD_s|I2 },
+{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|I2 },
{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO },
{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO },
{"bgtl", "s,t,p", 2, (int) M_BGTL, INSN_MACRO },
{"bgtul", "s,t,p", 2, (int) M_BGTUL, INSN_MACRO },
{"bgtul", "s,I,p", 2, (int) M_BGTUL_I, INSN_MACRO },
{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s },
-{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBD|RD_s|I2 },
+{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s|I2 },
{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO },
{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO },
{"blel", "s,t,p", 2, (int) M_BLEL, INSN_MACRO },
{"bleul", "s,t,p", 2, (int) M_BLEUL, INSN_MACRO },
{"bleul", "s,I,p", 2, (int) M_BLEUL_I, INSN_MACRO },
{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s },
-{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBD|RD_s|I2 },
+{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s|I2 },
{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO },
{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO },
{"bltl", "s,t,p", 2, (int) M_BLTL, INSN_MACRO },
{"bltul", "s,t,p", 2, (int) M_BLTUL, INSN_MACRO },
{"bltul", "s,I,p", 2, (int) M_BLTUL_I, INSN_MACRO },
{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s },
-{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBD|RD_s|I2 },
+{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s|I2 },
{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31 },
-{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBD|RD_s|I2 },
+{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|I2 },
{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s },
-{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBD|RD_s|I2 },
+{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s|I2 },
{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t },
{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO },
-{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBD|RD_s|RD_t },
+{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t|I2},
{"bnel", "s,I,p", 2, (int) M_BNEL_I, INSN_MACRO },
-{"break", "", 0x0000000d, 0xffffffff, INSN_TRAP },
-{"break", "c", 0x0000000d, 0xfc00003f, INSN_TRAP },
+{"break", "", 0x0000000d, 0xffffffff, TRAP },
+{"break", "c", 0x0000000d, 0xfc00003f, TRAP },
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC },
{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC },
{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC },
{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC },
{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC },
{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC },
-{"cache", "t,o(b)", 0xbc000000, 0xfc000000, RD_b|I3 },
+{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b|I3 },
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|I3 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|I3 },
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|I2 },
{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S },
{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S },
{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S },
-{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO },
+{"dabs", "d,v", 3, (int) M_DABS, INSN_MACRO },
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
{"dadd", "t,r,I", 3, (int) M_DADD_I, INSN_MACRO },
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s|I3 },
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
{"daddu", "t,r,I", 3, (int) M_DADDU_I, INSN_MACRO },
/* For ddiv, see the comments about div. */
+{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
{"ddiv", "d,v,t", 3, (int) M_DDIV_3, INSN_MACRO },
{"ddiv", "d,v,I", 3, (int) M_DDIV_3I, INSN_MACRO },
-{"ddiv", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
/* For ddivu, see the comments about div. */
+{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
{"ddivu", "d,v,t", 3, (int) M_DDIVU_3, INSN_MACRO },
{"ddivu", "d,v,I", 3, (int) M_DDIVU_3I, INSN_MACRO },
-{"ddivu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
/* The MIPS assembler treats the div opcode with two operands as
though the first operand appeared twice (the first operand is both
a source and a destination). To get the div machine instruction,
- you must use an explicit destination of $0. The final case of
- "div" is the machine instruction itself, but actually a user
- instruction will never match it (it will match d,v,t first). */
+ you must use an explicit destination of $0. */
+{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO },
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO },
-{"div", "s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T },
{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T },
/* For divu, see the comments about div. */
+{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO },
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO },
-{"divu", "s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0|I3 },
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC|I3 },
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|I3 },
{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t|I3 }, /* dsub 0 */
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t|I3 }, /* dsubu 0*/
+{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO },
{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO },
+{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
+{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t|I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsllv */
+{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t|I3 }, /* dsll32 */
{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t|I3 },
-{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t|I3 },
{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
+{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t|I3 },
{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrav */
+{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t|I3 }, /* dsra32 */
{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t|I3 },
-{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t|I3 },
{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
+{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t|I3 },
{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrlv */
+{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t|I3 }, /* dsrl32 */
{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t|I3 },
-{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t|I3 },
{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
{"dsub", "d,v,I", 3, (int) M_DSUB_I, INSN_MACRO },
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|I2 },
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|I2 },
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s },
-{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s },
+{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s }, /* jr */
+/* SVR4 PIC code requires special handling for j, so it must be a
+ macro. */
+{"j", "a", 0, (int) M_J_A, INSN_MACRO },
+/* This form of j is used by the disassembler and internally by the
+ assembler, but will never match user input (because the line above
+ will match first). */
{"j", "a", 0x08000000, 0xfc000000, UBD },
{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d },
{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d },
-{"jal", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d },/* jalr */
-{"jal", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d },/* jalr $ra*/
+/* SVR4 PIC code requires special handling for jal, so it must be a
+ macro. */
+{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO },
+{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO },
+{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO },
+/* This form of jal is used by the disassembler and internally by the
+ assembler, but will never match user input (because the line above
+ will match first). */
{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31 },
-{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO },
-{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO },
-{"la", "t,A", 0, (int) M_LA, INSN_MACRO },
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO },
{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t },
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO },
{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
{"ldc1", "T,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
{"ldc1", "E,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
+{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2}, /* ldc1 */
+{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO },
+{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO },
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
{"ldc2", "E,A(b)", 2, (int) M_LDC2_AB, INSN_MACRO },
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO },
{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
{"flush", "t,A(b)", 2, (int) M_LWR_AB, INSN_MACRO }, /* as lwr */
-{"lwu", "t,o(b)", 0xbc000000, 0xfc000000, LDD|RD_b|WR_t|I3},
+{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t|I3},
{"lwu", "t,A(b)", 3, (int) M_LWU_AB, INSN_MACRO },
+{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|P3},
+{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|P3},
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S },
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO },
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T },
+{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO|P3},
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO },
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO },
{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S },
/* nop is at the start of the table. */
{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"nor", "d,v,I", 0, (int) M_NOR_I, INSN_MACRO },
-{"not", "d,v", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t }, /* nor d,s,zero */
+{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO },
+{"not", "d,v", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t },/*nor d,s,0*/
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t },
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO },
{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s },
+{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO },
{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO },
+{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO },
{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO },
{"rfe", "", 0x42000010, 0xffffffff, INSN_RFE },
{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|I3 },
{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|I2 },
{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|I2 },
-{"sb", "t,o(b)", 0xa0000000, 0xfc000000, RD_t|RD_b },
+{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b },
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO },
-{"sc", "t,o(b)", 0xe0000000, 0xfc000000, RD_t|RD_b|I2 },
+{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b|I2 },
{"sc", "t,A(b)", 2, (int) M_SC_AB, INSN_MACRO },
-{"scd", "t,o(b)", 0xf0000000, 0xfc000000, RD_t|RD_b|I3 },
+{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b|I3 },
{"scd", "t,A(b)", 3, (int) M_SCD_AB, INSN_MACRO },
-{"sd", "t,o(b)", 0xfc000000, 0xfc000000, RD_t|RD_b|I3 },
+{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b|I3 },
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO },
-{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, RD_T|RD_b|I2 },
-{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, RD_T|RD_b|I2 },
+{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
+{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
{"sdc1", "T,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
{"sdc1", "E,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
-{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_C2|RD_b|I2 },
+{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b|I2 },
{"sdc2", "E,A(b)", 2, (int) M_SDC2_AB, INSN_MACRO },
-{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_C3|RD_b|I2 },
+{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b|I2 },
{"sdc3", "E,A(b)", 2, (int) M_SDC3_AB, INSN_MACRO },
-{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, RD_T|RD_b|I2 },
+{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO },
-{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_t|RD_b|I3 },
+{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b|I3 },
{"sdl", "t,A(b)", 3, (int) M_SDL_AB, INSN_MACRO },
-{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, RD_t|RD_b|I3 },
+{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b|I3 },
{"sdr", "t,A(b)", 3, (int) M_SDR_AB, INSN_MACRO },
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO },
{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO },
{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO },
{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO },
{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO },
-{"sh", "t,o(b)", 0xa4000000, 0xfc000000, RD_t|RD_b },
+{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b },
{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO },
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO },
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO },
{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO },
{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO },
{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|I2 },
-{"sqrt.w", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|I2 },
+{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|I2 },
{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s },
{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srav */
{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t },
{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T },
{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t },
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO },
-{"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_t|RD_b },
+{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b },
{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO },
-{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_C0|RD_b },
+{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b },
{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO },
-{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_T|RD_b },
-{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, RD_T|RD_b },
+{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b },
+{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b },
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
-{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, RD_T|RD_b }, /* swc1 */
+{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_C2|RD_b },
+{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b },
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO },
-{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_C3|RD_b },
+{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b },
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO },
-{"swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b },
+{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b },
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO },
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b|I2 }, /* same */
{"scache", "t,A(b)", 2, (int) M_SWL_AB, INSN_MACRO }, /* as swl */
-{"swr", "t,o(b)", 0xb8000000, 0xfc000000, RD_t|RD_b },
+{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b },
{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO },
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b|I2 }, /* same */
{"invalidate", "t,A(b)",2, (int) M_SWR_AB, INSN_MACRO }, /* as swr */
{"sync", "", 0x0000000f, 0xffffffff, I2 },
-{"syscall", "", 0x0000000c, 0xffffffff, INSN_TRAP },
-{"syscall", "B", 0x0000000c, 0xfc00003f, INSN_TRAP },
-{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|I2 },
-{"teq", "s,t", 0x00000034, 0xfc00003f, RD_s|RD_t|I2 },
-{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|I2 }, /* teqi */
+{"syscall", "", 0x0000000c, 0xffffffff, TRAP },
+{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP },
+{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|I2|TRAP },
+{"teq", "s,t", 0x00000034, 0xfc00003f, RD_s|RD_t|I2|TRAP },
+{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|I2|TRAP }, /* teqi */
{"teq", "s,I", 2, (int) M_TEQ_I, INSN_MACRO },
-{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|I2 },
-{"tge", "s,t", 0x00000030, 0xfc00003f, RD_s|RD_t|I2 },
-{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|I2 }, /* tgei */
+{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|I2|TRAP },
+{"tge", "s,t", 0x00000030, 0xfc00003f, RD_s|RD_t|I2|TRAP },
+{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|I2|TRAP }, /* tgei */
{"tge", "s,I", 2, (int) M_TGE_I, INSN_MACRO },
-{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|I2 },
-{"tgeu", "s,t", 0x00000031, 0xfc00003f, RD_s|RD_t|I2 },
-{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|I2 }, /* tgeiu */
+{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|I2|TRAP },
+{"tgeu", "s,t", 0x00000031, 0xfc00003f, RD_s|RD_t|I2|TRAP },
+{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|I2|TRAP }, /* tgeiu */
{"tgeu", "s,I", 2, (int) M_TGEU_I, INSN_MACRO },
{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB },
{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB },
{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB },
{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB },
-{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|I2 },
-{"tlt", "s,t", 0x00000032, 0xfc00003f, RD_s|RD_t|I2 },
-{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|I2 }, /* tlti */
+{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|I2|TRAP },
+{"tlt", "s,t", 0x00000032, 0xfc00003f, RD_s|RD_t|I2|TRAP },
+{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tlti */
{"tlt", "s,I", 2, (int) M_TLT_I, INSN_MACRO },
-{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|I2 },
-{"tltu", "s,t", 0x00000033, 0xfc00003f, RD_s|RD_t|I2 },
-{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|I2 }, /* tltiu */
+{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|I2|TRAP },
+{"tltu", "s,t", 0x00000033, 0xfc00003f, RD_s|RD_t|I2|TRAP },
+{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tltiu */
{"tltu", "s,I", 2, (int) M_TLTU_I, INSN_MACRO },
-{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|I2 },
-{"tne", "s,t", 0x00000036, 0xfc00003f, RD_s|RD_t|I2 },
-{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|I2 }, /* tnei */
+{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|I2|TRAP },
+{"tne", "s,t", 0x00000036, 0xfc00003f, RD_s|RD_t|I2|TRAP },
+{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tnei */
{"tne", "s,I", 2, (int) M_TNE_I, INSN_MACRO },
{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|I3 },
{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|I3 },
{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|I2 },
{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|I2 },
{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO },
+{"uld", "t,o(b)", 3, (int) M_ULD, INSN_MACRO },
+{"uld", "t,A", 3, (int) M_ULD_A, INSN_MACRO },
{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO },
{"ulh", "t,A", 0, (int) M_ULH_A, INSN_MACRO },
{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO },
{"ulhu", "t,A", 0, (int) M_ULHU_A, INSN_MACRO },
{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO },
{"ulw", "t,A", 0, (int) M_ULW_A, INSN_MACRO },
+{"usd", "t,o(b)", 3, (int) M_USD, INSN_MACRO },
+{"usd", "t,A", 3, (int) M_USD_A, INSN_MACRO },
{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO },
{"ush", "t,A", 0, (int) M_USH_A, INSN_MACRO },
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO },
projects / binutils.git / blobdiff