+
+ * simops.c (OP_3220): Fix trace output for illegal accumulator
+ message.
+
+
+ * simops.c: Disable setting of DM bit in PSW.
+
+
+ * simops.c (op_types): Added new memory indirect type OP_MEMREF3.
+ (trace_input_func): Added support for OP_MEMREF3.
+ (OP_32010000): New instruction ld.
+ (OP_33010000): New instruction ld2w.
+ (OP_5209): New instruction sac.
+ (OP_4209): New instruction sachi.
+ (OP_3220): New instruction slae.
+ (OP_36010000): New instruction st.
+ (OP_37010000): New instruction st2w.
+
+
+ * interp.c (old_segment_mapping): New global.
+ (xfer_mem): Change the default segment mapping to be the way
+ that Mitsubishi prefers, but use the previous mapping if
+ old_segment_mapping is true.
+ (sim_open): Add an option -oldseg to get the old mapping.
+ (sim_create_inferior): Init mapping registers based on the
+ value of old_segment_mapping.
+
+
+ * simops.c (OP_6601): Do not write back decremented address if
+ either of the destination registers was the same as the address
+ register.
+ (OP_6201): Do not write back incremented address if either of the
+ destination registers was the same as the address register.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * interp.c (ui_loop_hook_counter): New global (when NEED_UI_LOOP_HOOK
+ defined).
+ (sim_resume): If the counter has expired, call the ui_loop_hook,
+ if defined.
+ (UI_LOOP_POLL_INTERVAL): Define. Used to tweak the frequency of
+ ui_loop_hook calls.
+ * Makefile.in (SIM_EXTRA_CFLAGS): Include NEED_UI_LOOP_HOOK.
+
+
+ * simops.c: If load instruction with auto increment/decrement
+ addressing is used when the destination register is the same as
+ the address register, then ignore the auto increment/decrement.
+
+
+ * simops.c (OP_5F00): Ifdef SYS_stat case because
+ not all systems have it defined.
+
+
+ * simops.c (OP_5607): Correct saturation comparison/assignment.
+ (OP_1201, OP_1203, OP_17001200, OP_17001202,
+ OP_2A00, OP_2800, OP_2C00, OP_3200, OP_3201,
+ OP_1001, OP_1003, OP_17001000, OP_17001002): Ditto.
+
+
+ * simops.c (OP_5605): Sign extend MIN32 and MAX32 before saturation
+ comparison.
+ (OP_5607): Ditto.
+ (OP_2A00): Ditto.
+ (OP_2800): Ditto.
+
+
+ * simops.c (OP_1223): Sign extend MIN32 and MAX32 before saturation
+ comparison.
+
+
+ * simops.c (sys/syscall.h): Include targ-vals.h instead.
+ (SYS_*): Replace with TARGET_SYS_*.
+
+ * Makefile.in: Add dependency on targ-vals.h.
+ (NL_TARGET): Define as NL_TARGET_d10v.
+
+
+ * interp.c (xfer_mem): Missing break, instruction memory case
+ flowed into unified memory case.
+
+
+ * simops.c: If load instruction with auto increment/decrement
+ addressing is used when the destination register is the same as
+ the address register, then ignore the auto increment/decrement.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+
+ * acconfig.h: New file.
+ * configure.in: Reverted change of Apr 24; use sinclude again.
+
+Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+
+ * configure.in: Don't call sinclude.
+
+
+ * interp.c (struct hash_entry): OPCODE and MASK are unsigned.
+
+ * d10v_sim.h (remote-sim.h, sim-config.h): Include.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * simops.c (trace_input_func): Use move_from_cr / CREGS to obtain
+ up-to-date CR value.
+ (OP_OP_1000000, add3): Trace inputs before performing add.
+ (OP_5F00, <*>): Trace input registers before making system call.
+ (OP_5F00, <kill>): Trace R0, R1 not REGn.
+ (OP_5F00, <getpid>): Always return 47.
+
+ * d10v_sim.h (SLOT, SLOT_NR, SLOT_PEND_MASK, SLOT_PEND,
+ SLOT_DISCARD, SLOT_FLUSH): Define. An implementation of write
+ back slots.
+ (struct _state): Add struct slot slot to global state variable.
+ (struct _state): Delete fields SM, EA, DB, DM, IE, RP, MD, FX, ST,
+ F0, F1, C from global State variable.
+ (struct _state): Add struct trace to global State variable.
+ (GPR, SET_GPR): Define. SET_GPR uses SLOT_PEND.
+ (PSW*, SET_PSW*): Define. SET_PSW* uses SET_CREG.
+ (CREG, SET_CREG, SET_*): Define. SET_CREG uses func move_to_cr.
+ (INC_ADDR): Re-implement. Use SET_GPR to update registers.
+ (JMP): Re-implement. Use SET_* to update registers.
+
+ * interp.c: Use new SET_* et.al. macros to fetch / store
+ registers.
+ (get_operands): Squirrel away trace values at start of each
+ operand decode.
+ (do_2_short): Flush pending writes before issuing second
+ instruction.
+ (sim_resume): Flush pending writes at end of instruction cycle.
+ (sim_fetch_register, sim_store_register, sim_create_inferior):
+ After scheduling updates to registers using SET_*, flush updates.
+ (sim_resume): Re-order handling of RPT/repeat and IBA/hbreak so
+ that each sets pc using SET_* and last SET_* eventually winds out.
+
+ * simops.c: Use new SET_* et.al. macros to fetch / store
+ registers.
+ (move_to_cr): Add MASK argument for selective update of CREG bits.
+ Re-implement using new SET_* macros.
+ (trace_output_func, trace_output): Delete. Replace with.
+ (do_trace_output_flush, trace_output_finish, trace_output_40,
+ trace_output_32, trace_output_16, trace_output_void,
+ trace_output_flag): New functions. Handle specific trace cases.
+ (OP_*): Re-write tracing to use new trace_output_* functions.
+ (OP_*): Re-write to use new SET_* et.al. macros.
+ (FUNC, PARM[1-4], RETVAL, RETVAL32): Redo definition.
+ (RETVAL_HIGH, RETVAL_LOW): Delete, use RETVAL32.
+
+
+ * configure.in (SIM_AC_OPTION_WARNINGS): Add.
+ configure: Re-generate.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * interp.c (sim_store_register, sim_fetch_register): Pass in
+ length parameter. Return -1.
+
+
+ * (dmem_addr): If address is illegal or in I/O space, signal a bus
+ error. Allocate unified memory on demand. Fix DMEM address
+ calculations.
+
+
+ * simops.c (OP_5F20): Implement "dbt".
+ (OP_5F60): Implement "rtd".
+
+ * d10v_sim.h (DPC_CR): Define enum.
+ (DBT_VECTOR_START): Define
+ (DPSW, DPC): Define.
+
+
+ * simops.c (move_to_cr): Sync regs[SP_IDX] with State.sp according
+ to PSW:SM.
+
+ * d10v_sim.h (struct _state): Add sp, as holding area for SPI/SPU.
+ (SP_IDX): Define.
+
+
+ * simops.c (OP_5F00): Call error instead of abort for unknown
+ syscalls.
+
+ * d10v_sim.h (enum): Define DPSW_CR.
+
+ * simops.c (move_to_cr): Mask out hardwired zero bits in DPSW.
+
+
+ * interp.c (sim_write_phys): Delete.
+ (sim_load): Call sim_load_file with sim_write and LMA.
+
+
+ * interp.c: Rewrite xfer_mem so that it translates addresses as -
+ 0x00... - DMAP translated memory, 0x01... IMAP translated memory,
+ 0x10... - on-chip data, 0x11... - on-chip insn, 0x12... - unified
+ memory.
+ (pc_addr): Delete.
+ (imem_addr): New function - translate IMEM address.
+ (sim_resume): Use imem_addr to translate insn address, abort if
+ translation failed.
+ (sim_create_inferior): Write ARGV to memory using sim_write. Pass
+ argc/argv using r0/r1 not r2/r3.
+ (sim_size): Do not initialize IMAP/DMAP here.
+ (sim_open): Call sim_create_inferior and sim_size to initialize
+ the system.
+ (sim_create_inferior): Initialize IMAP/DMAP to hardware reset
+ defaults.
+ (init_system): Delete.
+ (xfer_mem, sim_fetch_register, sim_store_register): Do not call
+ init_system.
+ (decode_pc): Check prog_bfd is defined before looking up .text
+ section.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * interp.c (sim_stop_reason): Exit status is now in r0, not r2.
+
+
+ * d10v_sim.h (DEBUG_TRAP): New debug flag.
+
+ * simops.c (OP_5F00): If DEBUG_TRAP is on, turn traps 0-14 into
+ printing the registers.
+
+
+ * simops.c (op_types): New ABI, args are r0..r3, system call # is
+ in r4.
+ (trace_{in,out}put_func): Ditto.
+ (OP_4900): Ditto.
+ (OP_24800000): Ditto.
+ (OP_4D00): Ditto.
+ (OP_5F00): Ditto.
+
+
+ * interp.c (UMEM_SEGMENTS): New define, set to 128.
+ (sim_size): Use UMEM_SEGMENTS rather than hardwired constant.
+ (sim_close): Reset prog_bfd to NULL after closing it. Also
+ reset prog_bfd_was_opened_p after closing prog_bfd.
+ (sim_load): Reset prog_bfd_was_opened_p after closing prog_bfd.
+ (sim_create_inferior): Get start address from abfd not prog_bfd.
+ (xfer_mem): Do bounds checking on addresses and return zero length
+ read/write on bad addresses, rather than aborting. Prepare to
+ be able to handle xfers that cross segment boundaries, but not
+ yet implemented. Only emit debug message when d10v_debug is
+ set as well as DEBUG being defined.
+
+Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+
+ * d10v_sim.h (RPT_S): Index cregs with RPT_S_CR not RPT_E_CR.
+ (BPSW): Ditto for BPSW_CR and not PSW_CR.
+
+ * simops.c (OP_5F40): JMP to BPC instead of assigning PC directly.
+
+
+ reserved trap from 0 to 15. Add trap emulation code for 0-14.
+
+ IBA for SDBT.
+
+ * d10v_sim.h (AE_VECTOR_START, RIE_VECTOR_START,
+ SDBT_VECTOR_START, TRAP_VECTOR_START): Define.
+
+ * simops.c (OP_5F00): For "trap", mask out all but SM bit in PSW,
+ use move_to_cr.
+ (OP_5F00): For "trap", update BPSW with move_to_cr.
+
+
+ * d10v_sim.h (enum): Enumerate CR register names.
+ (enum): Enumerate PSW bit values.
+ (PSW): Obtain value uing move_from_cr.
+ (MOD_S, MOD_E, BPSW): Make r-values.
+ (move_from_cr, move_to_cr): Declare functions.
+
+ * interp.c (sim_fetch_register, sim_store_register): Use
+ move_from_cr and move_to_cr for CR register transfers.
+
+ * simops.c (move_from_cr, move_to_cr): New functions.
+ (OP_5F40): Move BPSW to PSW using move_to_cr and move_from_cr.
+ (OP_5600): For "mvtc", use function move_to_cr.
+ (OP_5200): For "mvfc", use function move_from_cr.
+
+
+ * simops.c (OP_5600): For "mvtc" MOD_E and MOD_S, ensure that the
+ LSbit is zero.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * d10v_sim.h (struct _state): Add DM - PSW debug mask.
+
+ * simops.c (OP_5600): For "mvtc", save PSW.DM.
+ (OP_5200): Ditto for "mvfc".
+
+
+ * d10v_sim.h (SEXT56): Define.
+
+ * simops.c (OP_4201): For "rac", sign extend 56 bit value before
+ it is shifted.
+
+ * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using
+ SIGNED64 macro.
+
+
+ * interp.c (sim_resume): Call do_2_short with LEFT_FIRST or
+ RIGHT_FIRST, as appropriate, instead of hardcoded ints that
+ don't match enum values.
+
+
+ * simops.c (OP_3A00): For "macu", perform multiply stage using 32
+ bit rather than 16 bit precision.
+ (OP_3C00): For "mulxu", store unsigned product in ACC.
+ (OP_3800): For "msbu", subtract unsigned product from ACC,
+ (OP_0): For "sub", compute carry by comparing inputs.
+
+
+ * simops.c (OP_1000): For "sub2w", compute carry by comparing
+ inputs.
+
+
+ * simops.c (OP_1): Use 32 bit unsigned arithmetic for subtract,
+ carry indicated by value > 0xffff.
+
+
+ * interp.c (sim_resume): Don't set up SIGINT handler using signal,
+ handled by client.
+ (sim_resume): Fix race condition of a direct assignment to
+ stop_simulator, conditionally call sim_stop.
+ (sim_stop_reason): Check stop_simulator returning SIGINT. Clear
+ stop_simulator ready for next sim_resume call.
+ (sim_ctrl_c): Delete function.
+
+
+ * interp.c (sim_resume): For "REP", only check/update the PC when
+ a branch instruction has not been executed.
+
+
+ * simops.c (OP_4201): "rachi". Sign extend bit 40 of ACC. Sign
+ extend bit 44 all constants.
+ (OP_4201): Replace GCC specific 0x..LL with SIGNED64 macro.
+
+
+ * d10v_sim.h: Include sim-types.h.
+ (uint8, in816, uiny16, int32, uint32, int64, uint64): Typedef
+ using unsigned8 et.al. from sim-types.h.
+ (SEXT32, SEXT40, SEXT44, SEXT60): Replace GCC specific 0x..LL with
+ SIGNED64 macro.
+
+
+ * interp.c (sim_write_phys): New function, write to physical
+ instead of virtual memory.
+
+ * interp.c (sim_load): Pass lma_p and sim_write_phys to
+ sim_load_file.
+
+Mon Oct 13 10:55:07 1997 Fred Fish <cygnus.com>
+
+ * simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and move
+ exception generation code to OP_6E01.
+ (OP_6E01): Change OP_POSTINC to OP_POSTDEC and insert exception
+ generation code.
+
+
+ * simops.c (OP_6401): postdecrement on r15 is OK, remove exception.
+ (OP_6601): Ditto.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * interp.c (pc_addr): Discard upper bit(s) of PC in case
+ IMAP1 selects unified memory.
+ * d10v_sim.h (INC_ADDR): Align MOD_E to increment before testing
+ for end condition.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * interp.c (sim_resume): Increment PC at end of rep
+ loop.
+
+ * simops.c (OP_4201): Fix rachi instruction.
+
+Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+
+ * interp.c (sim_kill): Delete.
+ (sim_create_inferior): Add ABFD argument.
+ (sim_load): Move setting of PC from here.
+ (sim_create_inferior): To here.
+ (start_address): Delete variable.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+
+ * interp.c (sim_open): Add ABFD argument.
+
+
+ * interp.c (sim_open): Add callback argument.
+ (sim_set_callbacks): Remove SIM_DESC argument.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * interp.c (sim_open): Undo patch to add -E support.
+
+
+ * interp.c (sim_stop): New function.
+
+
+ * Makefile.in (SIM_OBJS): Add sim-load.o.
+ * d10v_sim.h (exec_bfd): Rename to prog_bfd.
+ * interp.c: #include bfd.h.
+ (myname, sim_kind, start_address): New static locals.
+ (prog_bfd_was_opened_p, prog_bfd): New static locals.
+ (decode_pc): Update to use prog_bfd.
+ (sim_open): Set sim_kind, myname. Ignore -E arg.
+ (sim_close): Close prog_bfd if simulator opened it.
+ (sim_create_inferior): Return SIM_RC. Delete arg start_address.
+ (sim_load): Return SIM_RC. New arg abfd. Set start address from bfd.
+ Call sim_load_file to load file into simulator.
+ * simops.c (trace_input_func): exec_bfd renamed to prog_bfd.
+
+
+ * simops.c (OP_5F00): Only provide system calls SYS_execv,
+ SYS_wait, SYS_wait, SYS_utime, SYS_time if defined by the host.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+
+ * interp.c (sim_open): New arg `kind'.
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
* configure: Regenerated to track ../common/aclocal.m4 changes.
projects / binutils.git / blobdiff