* interp.c (sim_open): Add support for bfd_arch_v850_rh850
architecture type. Add support for bfd_mach_v850e2 and
bfd_mach_v850e2v3 machine numbers.
* interp.c (sim_open): Add support for bfd_arch_v850_rh850
architecture type. Add support for bfd_mach_v850e2 and
bfd_mach_v850e2v3 machine numbers.
- * v850.igen (dbtrap): Add support for SIM_OPEN_DEBUG.
- (cmpf.d): Correct order of operands.
- (cmpf.s): Likewise.
- (trncf.dul): New pattern.
- (trncf.duw): New pattern.
- (trncf.sul): New pattern.
- (trncf.suw): New pattern.
- * v850-dc: Correct bitfield selection for TRNCF.SW and CVTF.SW.
+ * v850.igen (dbtrap): Add support for SIM_OPEN_DEBUG.
+ (cmpf.d): Correct order of operands.
+ (cmpf.s): Likewise.
+ (trncf.dul): New pattern.
+ (trncf.duw): New pattern.
+ (trncf.sul): New pattern.
+ (trncf.suw): New pattern.
+ * v850-dc: Correct bitfield selection for TRNCF.SW and CVTF.SW.
(OP_28007E0): Likewise, for divh. Also, sign-extend the correct
operand.
* v850.igen (divh): Likewise, for 2-op divh.
(OP_28007E0): Likewise, for divh. Also, sign-extend the correct
operand.
* v850.igen (divh): Likewise, for 2-op divh.
Only generate a trap if the target is not the v850e1.
Otherwise treat it as a special kind of branch.
(break): Mark as v850/v850e specific.
Only generate a trap if the target is not the v850e1.
Otherwise treat it as a special kind of branch.
(break): Mark as v850/v850e specific.
* sim-main.h (trace_module): Change variable decl to integer type.
(TRACE_BRANCH*, TRACE_LD, TRACE_ST): Update.
* sim-main.h (trace_module): Change variable decl to integer type.
(TRACE_BRANCH*, TRACE_LD, TRACE_ST): Update.
* v850.igen (BREAK), simops.c (OP_12007E0): Rename SIGTRAP to
SIM_SIGTRAP.
(illegal): Rename SIGILL to SIM_SIGILL.
* v850.igen (BREAK), simops.c (OP_12007E0): Rename SIGTRAP to
SIM_SIGTRAP.
(illegal): Rename SIGILL to SIM_SIGILL.
* sim-main.h, simops.c, interp.c: Do not include signal.h.
* sim-main.h: Include sim-signal.h instead of signal.h.
* sim-main.h, simops.c, interp.c: Do not include signal.h.
* sim-main.h: Include sim-signal.h instead of signal.h.
* Makefile.in (SIM_WARNINGS, SIM_ALIGNMENT, SIM_ENDIAN,
SIM_HOSTENDIAN, SIM_RESERVED_BITS): Delete, moved to common.
(SIM_EXTRA_CFLAGS): Update.
* Makefile.in (SIM_WARNINGS, SIM_ALIGNMENT, SIM_ENDIAN,
SIM_HOSTENDIAN, SIM_RESERVED_BITS): Delete, moved to common.
(SIM_EXTRA_CFLAGS): Update.
(trace_module): Global, save component/module name across insn.
* simops.c: Move "bsh" to v850.igen, fix.
(trace_module): Global, save component/module name across insn.
* simops.c: Move "bsh" to v850.igen, fix.
* v850.igen (callt): Load correct number of bytes. Fix tracing.
(stsr, ldsr): Correct src, dest fields. Fix tracing.
(ctret): Force alignment. Fix tracing.
* v850.igen (callt): Load correct number of bytes. Fix tracing.
(stsr, ldsr): Correct src, dest fields. Fix tracing.
(ctret): Force alignment. Fix tracing.
(trace_values, trace_name, trace_pc, trace_num_values): Make
global.
(GR, SR): Define.
(trace_values, trace_name, trace_pc, trace_num_values): Make
global.
(GR, SR): Define.
v850.insn (movea, stsr): Use.
(sxb, sxh, zxb, zxh): Ditto.
v850.insn (movea, stsr): Use.
(sxb, sxh, zxb, zxh): Ditto.
* v850.igen (simm16): Define, sign extend imm16.
(uimm16): Define, no sign extension.
(addi, andi, movea, movhi, mulhi, ori, satsubi, xori): Use.
* v850.igen (simm16): Define, sign extend imm16.
(uimm16): Define, no sign extension.
(addi, andi, movea, movhi, mulhi, ori, satsubi, xori): Use.
* simops.c: Move "sxh", "switch", "sxb", "callt", "dispose",
"mov32" from here.
* v850.igen: To here.
(switch): Fix off by two error in NIA calc.
* simops.c: Move "sxh", "switch", "sxb", "callt", "dispose",
"mov32" from here.
* v850.igen: To here.
(switch): Fix off by two error in NIA calc.
(trace_output): Write trace values to a buffer. Use
trace_one_insn to print trace info and buffer.
(SIZE_OPERANDS, SIZE_LOCATION): Delete.
(trace_output): Write trace values to a buffer. Use
trace_one_insn to print trace info and buffer.
(SIZE_OPERANDS, SIZE_LOCATION): Delete.
* simops.c: Move "divun", "sld.bu", "divhn", "divhun", "divn",
"divun", "pushml" code from here to v850.igen.
(divun): Make global.
(type3_regs): Make global
* simops.c: Move "divun", "sld.bu", "divhn", "divhun", "divn",
"divun", "pushml" code from here to v850.igen.
(divun): Make global.
(type3_regs): Make global
* v850.igen (prepare, ...): Add to v850eq architecture.
* interp.c (sim_open): Default to v850eq.
* v850.igen (prepare, ...): Add to v850eq architecture.
* interp.c (sim_open): Default to v850eq.
(SEXT32): Delete, used?
(SEXT40, SEXT44, SEXT64): Use UNSIGNED64 for constants, not ...LL.
(WITH_TARGET_WORD_MSB): Define as 31. v850 little bit endian.
(SEXT32): Delete, used?
(SEXT40, SEXT44, SEXT64): Use UNSIGNED64 for constants, not ...LL.
(WITH_TARGET_WORD_MSB): Define as 31. v850 little bit endian.
* simops.c: Use EXTEND15 from sim-bits instead of SEXT16.
* sim-main.h (DEBUG_TRACE, DEBUG_VALUES, v850_debug): Delete,
* simops.c: Use EXTEND15 from sim-bits instead of SEXT16.
* sim-main.h (DEBUG_TRACE, DEBUG_VALUES, v850_debug): Delete,
* Makefile.in (SIM_OBJS): Add sim-resume, sim-watch, sim-stop,
sim-reason.
* Makefile.in (SIM_OBJS): Add sim-resume, sim-watch, sim-stop,
sim-reason.
(AC_CHECK_FUNCS): Add utime.
(AC_CHECK_HEADERS): Add stdlib.h, string.h, strings.h, utime.h
configure: Regenerate.
(AC_CHECK_FUNCS): Add utime.
(AC_CHECK_HEADERS): Add stdlib.h, string.h, strings.h, utime.h
configure: Regenerate.
* Makefile.in (SIM_RUN_OBJS): Use nrun.o.
(SIM_OBJS): Add sim-io.o, sim-hload.o, sim-utils.o, sim-options.o,
* Makefile.in (SIM_RUN_OBJS): Use nrun.o.
(SIM_OBJS): Add sim-io.o, sim-hload.o, sim-utils.o, sim-options.o,
* interp.c (prog_bfd, prog_bfd_was_opened_p): Delete.
(v850_callback): Ditto.
(sim_kind, myname): Ditto.
* interp.c (prog_bfd, prog_bfd_was_opened_p): Delete.
(v850_callback): Ditto.
(sim_kind, myname): Ditto.
(sim_set_callbacks): Delete.
(sim_set_interrupt): Pass in SD, use.
(start_time): Delete.
(sim_set_callbacks): Delete.
(sim_set_interrupt): Pass in SD, use.
(start_time): Delete.
* v850_sim.h: Remove everything except `struct simops' from here.
* sim-main.h: Move most to here.
* gencode.c: Move #includes to here.
* v850_sim.h: Remove everything except `struct simops' from here.
* sim-main.h: Move most to here.
* gencode.c: Move #includes to here.
* configure.in: Check for time, chmod.
* configure: Regenerate.
* simops.c (SYS_time, SYS_chmod): Use HAVE_TIME, HAVE_CHMOD.
* configure.in: Check for time, chmod.
* configure: Regenerate.
* simops.c (SYS_time, SYS_chmod): Use HAVE_TIME, HAVE_CHMOD.
* simops.c (../../libgloss/v850/sys/syscall.h): Include instead of
sys/syscall.h.
(OP_10007E0): Check the existance each SYS_* macro independantly.
* simops.c (../../libgloss/v850/sys/syscall.h): Include instead of
sys/syscall.h.
(OP_10007E0): Check the existance each SYS_* macro independantly.
* simops.c (prepare, dispose): Lower numbered
registers go to higher numbered address.
* simops.c (unsigned divide instructions): S bit set if result has
top bit set.
* simops.c (prepare, dispose): Lower numbered
registers go to higher numbered address.
* simops.c (unsigned divide instructions): S bit set if result has
top bit set.
* simops.c (pushml, pushmh, popml, popmh): Lower numbered
registers go to higher numbered address.
* simops.c (pushml, pushmh, popml, popmh): Lower numbered
registers go to higher numbered address.
* interp.c (sim_resume): Opcode functions return amount to be
added to PC and all opcodes take a standard format in the OP[]
array.
* interp.c (sim_resume): Opcode functions return amount to be
added to PC and all opcodes take a standard format in the OP[]
array.
(do_format_*): Functions removed.
* v850_sim.h (SP, EP): New register mnemonics.
(do_format_*): Functions removed.
* v850_sim.h (SP, EP): New register mnemonics.
* gencode.c (write_header): Functions prototypes return an
integer.
* simops.c: Opcode functions return amount to be added to PC.
* gencode.c (write_header): Functions prototypes return an
integer.
* simops.c: Opcode functions return amount to be added to PC.
* interp.c: Add support for variable-size allocation of memory,
via simulator command "sim memory-map".
(map): Issue SIGSEGV for references to invalid memory regions.
* interp.c: Add support for variable-size allocation of memory,
via simulator command "sim memory-map".
(map): Issue SIGSEGV for references to invalid memory regions.
-
- * simops.c (trace_input): Swapped order of operands for output
- output of OP_IMM_REG. Changed the fetching of the operands for
- OP_LOAD32, and OP_STORE32 to work like op-function.
-
+
+ * simops.c (trace_input): Swapped order of operands for output
+ output of OP_IMM_REG. Changed the fetching of the operands for
+ OP_LOAD32, and OP_STORE32 to work like op-function.
+
- * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
+ * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
projects / binutils.git / blobdiff