Support Intel AVX-IFMA

[binutils.git] / gas / doc / c-i386.texi

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index faefb396cc20ebbe4ba745169841af9ca0e468f8..7bdbd26538ba31172d5b93e8fe81c55e0f422eed 100644 (file)
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -110,8 +110,6 @@ processor names are recognized:
 @code{core},
 @code{core2},
 @code{corei7},
-@code{l1om},
-@code{k1om},
 @code{iamcu},
 @code{k6},
 @code{k6_2},
@@ -139,16 +137,9 @@ accept various extension mnemonics.  For example,
 @code{287},
 @code{387},
 @code{687},
-@code{no87},
-@code{no287},
-@code{no387},
-@code{no687},
 @code{cmov},
-@code{nocmov},
 @code{fxsr},
-@code{nofxsr},
 @code{mmx},
-@code{nommx},
 @code{sse},
 @code{sse2},
 @code{sse3},
@@ -157,18 +148,8 @@ accept various extension mnemonics.  For example,
 @code{sse4.1},
 @code{sse4.2},
 @code{sse4},
-@code{nosse},
-@code{nosse2},
-@code{nosse3},
-@code{nosse4a},
-@code{nossse3},
-@code{nosse4.1},
-@code{nosse4.2},
-@code{nosse4},
 @code{avx},
 @code{avx2},
-@code{noavx},
-@code{noavx2},
 @code{adx},
 @code{rdseed},
 @code{prfchw},
@@ -191,9 +172,7 @@ accept various extension mnemonics.  For example,
 @code{serialize},
 @code{tsxldtrk},
 @code{kl},
-@code{nokl},
 @code{widekl},
-@code{nowidekl},
 @code{hreset},
 @code{avx512f},
 @code{avx512cd},
@@ -215,37 +194,12 @@ accept various extension mnemonics.  For example,
 @code{avx512_bf16},
 @code{avx_vnni},
 @code{avx512_fp16},
-@code{noavx512f},
-@code{noavx512cd},
-@code{noavx512er},
-@code{noavx512pf},
-@code{noavx512vl},
-@code{noavx512bw},
-@code{noavx512dq},
-@code{noavx512ifma},
-@code{noavx512vbmi},
-@code{noavx512_4fmaps},
-@code{noavx512_4vnniw},
-@code{noavx512_vpopcntdq},
-@code{noavx512_vbmi2},
-@code{noavx512_vnni},
-@code{noavx512_bitalg},
-@code{noavx512_vp2intersect},
-@code{notdx},
-@code{noavx512_bf16},
-@code{noavx_vnni},
-@code{noavx512_fp16},
-@code{noenqcmd},
-@code{noserialize},
-@code{notsxldtrk},
+@code{prefetchi},
+@code{avx_ifma},
 @code{amx_int8},
-@code{noamx_int8},
 @code{amx_bf16},
-@code{noamx_bf16},
+@code{amx_fp16},
 @code{amx_tile},
-@code{noamx_tile},
-@code{nouintr},
-@code{nohreset},
 @code{vmx},
 @code{vmfunc},
 @code{smx},
@@ -293,8 +247,8 @@ accept various extension mnemonics.  For example,
 @code{tlbsync},
 @code{svme} and
 @code{padlock}.
-Note that rather than extending a basic instruction set, the extension
-mnemonics starting with @code{no} revoke the respective functionality.
+Note that these extension mnemonics can be prefixed with @code{no} to revoke
+the respective (and any dependent) functionality.
 
 When the @code{.arch} directive is used with @option{-march}, the
 @code{.arch} directive will take precedent.
@@ -875,9 +829,9 @@ prefix which generates REX prefix unconditionally.
 @samp{@{nooptimize@}} -- disable instruction size optimization.
 @end itemize
 
-Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix
+Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix
 by default.  The pseudo @samp{@{vex@}} prefix can be used to encode
-mnemonics of Intel VNNI instructions with the VEX prefix.
+mnemonics of Intel VNNI/IFMA instructions with the VEX prefix.
 
 @cindex conversion instructions, i386
 @cindex i386 conversion instructions
@@ -1506,11 +1460,12 @@ directive enables a warning when gas detects an instruction that is not
 supported on the CPU specified.  The choices for @var{cpu_type} are:
 
 @multitable @columnfractions .20 .20 .20 .20
+@item @samp{default} @tab @samp{push} @tab @samp{pop}
 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
-@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
+@item @samp{corei7} @tab @samp{iamcu}
 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
@@ -1533,11 +1488,12 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
 @item @samp{.tdx} @tab @samp{.avx_vnni}  @tab @samp{.avx512_fp16}
-@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
+@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
+@item @samp{.prefetchi} @tab @samp{.avx_ifma}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
-@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_tile}
+@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16} @tab @samp{.amx_tile}
 @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
@@ -1560,6 +1516,9 @@ conditional jumps will be promoted when necessary to a two instruction
 sequence consisting of a conditional jump of the opposite sense around
 an unconditional jump to the target.
 
+Note that the sub-architecture specifiers (starting with a dot) can be prefixed
+with @code{no} to revoke the respective (and any dependent) functionality.
+
 Following the CPU architecture (but not a sub-architecture, which are those
 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
 control automatic promotion of conditional jumps. @samp{jumps} is the