+
+ Contribute support for Intel's iWMMXt chip - an ARM variant:
+
+ * arm-dis.c (regnames): Add iWMMXt register names.
+ (set_iwmmxt_regnames): New function.
+ (print_insn_arm): Handle iWMMXt formatters.
+ * arm-opc.h: Document iWMMXt formatters.
+ (arm_opcod): Add iWMMXt instructions.
+
+
+ * i386-dis.c (dis386): Recognize icebp (0xf1).
+
+
+ * s390-dis.c (init_disasm): Rename S390_OPCODE_ESAME to
+ S390_OPCODE_ZARCH.
+ (print_insn_s390): Use new modes field of s390_opcodes.
+ * s390-mkopc.c (ARCHBITS_ESAONLY, ARCHBITS_ESA, ARCHBITS_ESAME): Remove.
+ (s390_opcode_mode_val, s390_opcode_cpu_val): New enums.
+ (struct op_struct): Remove archbits. Add mode_bits and min_cpu.
+ (insertOpcode): Replace archbits by min_cpu and mode_bits.
+ (dumpTable): Write mode_bits and min_cpu instead of archbits.
+ (main): Adapt to new format in s390-opcode.txt.
+ * s390-opc.c (s390_opformats): Replace archbits by min_cpu and
+ mode_bits.
+ * s390-opc.txt: Replace archbits by min_cpu and mode_bits.
+
+
+ * ppc-opc.c: Fix formatting. Update copyright date.
+
+
+ * ppc-opc.c (powerpc_opcodes): Readd tlbre for PPC403.
+
+
+ * hppa-dis.c: Formatting.
+
+
+ * hppa-dis.c (print_insn_hppa): Implement fcnv instruction modifiers.
+
+ * hppa-dis.c (print_insn_hppa <2 bit space register>): Do not print
+ the space register when the value is zero.
+
+
+ * mips-dis.c (print_mips_disassembler_options): Make 'i' unsigned,
+ use ARRAY_SIZE in loops.
+
+
+ * fr30-desc.c: Regenerate.
+
+
+ * i386-dis.c (dq_mode, Edq): Define.
+ (dis386_twobyte): Correct movd operands.
+ (OP_E): Handle dq_mode case.
+
+
+ * sparc-dis.c (print_insn_sparc): When examining values added in
+ to rs1, make sure that there are previous instructions.
+
+
+ * Add sh2e support:
+
+
+ * sh-dis.c (print_insn_shx): Handle bfd_mach_sh2e.
+ * sh-opc.h (arch_sh2e, arch_sh2e_up): New.
+ (arch_sh2_up): Added sh2e.
+ (sh_table): Replaced all occurrences of arch_sh3e_up with
+ arch_sh2e_up, except in fsqrt.
+
+
+ * sh64-dis.c: Include elf32-sh64.h.
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+
+
+ * alpha-opc.c (alpha_opcodes): Add bugchk, rduniq, wruniq, gentrap
+ PAL entry points.
+
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+
+ * Makefile.am (ALL_MACHINES): Add msp430-dis.lo.
+ * Makefile.in: Regenerate.
+
+
+ * ppc-opc.c (powerpc_macros <extrwi>): Accept a shift of 32.
+
+
+ * iq2000-asm.c: New file.
+ * iq2000-desc.c: Likewise.
+ * iq2000-desc.h: Likewise.
+ * iq2000-dis.c: Likewise.
+ * iq2000-ibld.c: Likewise.
+ * iq2000-opc.c: Likewise.
+ * iq2000-opc.h: Likewise.
+ * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h.
+ (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c,
+ iq2000-ibld.c, iq2000-opc.c.
+ (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo,
+ iq2000-ibld.lo, iq2000-opc.lo.
+ (CLEANFILES): Add stamp-iq2000.
+ (IQ2000_DEPS): New macro.
+ (stamp-iq2000): New target.
+ * Makefile.in: Regenerate.
+ * configure.in: Handle bfd_iq2000_arch.
+ * configure: Regenerate.
+
+
+ * mips-dis.c (print_insn_args): Use position extracted by "+A"
+ to calculate size for "+B". Redo code for "+C" so it shares
+ the same style as "+A" and "+B" now do.
+
+
+ * mips-dis.c: Update copyright years.
+ (print_insn_arg): Rename to...
+ (print_insn_args): This, returning void. Process the whole
+ string of args rather than a single one. Reindent.
+ (print_insn_mips): Update to match the above.
+
+
+ * mips-opc.c (mips_builtin_opcodes): Move "di" into the
+ right order alphabetically, and make all hex constants use
+ lower-case letters.
+
+
+ * mips-dis.c (mips_cp0sel_name): New structure.
+ (mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
+ (mips_cp0sel_names_sb1): New arrays.
+ (mips_arch_choice): New structure members "cp0sel_names" and
+ "cp0sel_names_len".
+ (mips_arch_choices): Add references to new cp0sel_names arrays
+ as appropriate, and make all existing entries reference
+ appropriate mips_XXX_names_numeric arrays rather than simply
+ using NULL.
+ (mips_cp0sel_names, mips_cp0sel_names_len): New variables.
+ (lookup_mips_cp0sel_name): New function.
+ (set_default_mips_dis_options): Set mips_cp0sel_names and
+ mips_cp0sel_names_len as appropriate. Remove now-unnecessary
+ checks for NULL register name arrays.
+ (parse_mips_dis_option): Likewise.
+ (print_insn_arg): Handle "+D" operand type.
+ * mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
+ of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
+ names symbolically.
+
+
+ * mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
+ (mips_hwr_names_mips3264r2): New arrays.
+ (mips_arch_choice): New "hwr_names" member.
+ (mips_arch_choices): Adjust for structure change, and add a new
+ entry for "mips32r2" ISA.
+ (mips_hwr_names): New variable.
+ (set_default_mips_dis_options): Set mips_hwr_names.
+ (parse_mips_dis_option): New "hwr-names" option which sets
+ mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
+ (print_insn_arg): Change return type to "int"
+ and use that to indicate number of characters consumed.
+ Add support for "+" operand extension character, "+A", "+B",
+ "+C", and "K" operands.
+ (print_insn_mips): Adjust for changes to print_insn_arg.
+ (print_mips_disassembler_options): Adjust for "hwr-names"
+ addition and "reg-names" change.
+ * mips-opc (I33): New define (shorthand for INSN_ISA32R2).
+ (mips_builtin_opcodes): Note that "nop" and "ssnop" are special
+ forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
+ di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
+ rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
+ Note that hardware rotate instructions (ror, rorv) can be
+ used on MIPS32 Release 2, and add the official mnemonics
+ for them (rotr, rotrv) and the similar "rotl" mnemonic for
+ left-rotate.
+
+
+ * configure.in: Add msp430 target.
+ * configure: Regenerate.
+ * disassemble.c: Add entry for msp430 disassembly.
+ * msp430-dis.c: New file: msp430 disassembler.
+
+
+ * disassemble.c (disassembler_usage): Add invocation of
+ print_mips_disassembler_options.
+ * mips-dis.c: Include libiberty.h.
+ (print_mips_disassembler_options, set_default_mips_dis_options)
+ (parse_mips_dis_option, parse_mips_dis_options, choose_abi_by_name)
+ (choose_arch_by_name, choose_arch_by_number): New functions.
+ (mips_abi_choice, mips_arch_choice): New structures.
+ (mips32_reg_names, mips64_reg_names, reg_names): Remove.
+ (mips_gpr_names_numeric, mips_gpr_names_oldabi)
+ (mips_gpr_names_newabi, mips_fpr_names_numeric)
+ (mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64)
+ (mips_cp0_names_numeric, mips_cp0_names_mips3264)
+ (mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices)
+ (mips_processor, mips_isa, mips_gpr_names, mips_fpr_names)
+ (mips_cp0_names): New variables.
+ (print_insn_args): Use new variables to print GPR, FPR, and CP0
+ register names.
+ (mips_isa_type): Remove.
+ (print_insn_mips): Remove ISA and CPU setup since it is now done...
+ (_print_insn_mips): Here. Remove register setup code, and
+ call set_default_mips_dis_options and parse_mips_dis_options
+ instead.
+ (print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names.
+
+
+ * Makefile.in: Regenerate.
+
+
+ * cgen-asm.c (cgen_parse_keyword): Added underscore to symbol character
+ check to fix false keyword trigger with names such as <keyword>_foo.
+
+
+ * Makefile.am (CGEN_CPUS): New variable.
+ (run-cgen-all): New rule.
+ * Makefile.in: Regenerate.
+
+
+ * mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
+ "dror" entries, and reorder the remaining "dror" and "ror" entries.
+
+
+ * xstormy16-asm.c (parse_immediate16): Add prototype.
+
+
+ * xstormy16-asm.c: Regenerate.
+
+
+ * ns32k-dis.c (print_insn_ns32k): Constify "d", remove register
+ keyword.
+
* h8500-opc.h (h8500_table): Add missing initializers to quiet
projects / binutils.git / blobdiff