THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
- Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
+ 2008 Free Software Foundation, Inc.
- This file is part of the GNU Binutils and GDB, the GNU debugger.
+ This file is part of libopcodes.
- This program is free software; you can redistribute it and/or modify
+ This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
print_regset (cd, dis_info, value, attrs, pc, length, PUSH);
}
+static void
+print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ signed long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = dis_info;
+
+ (*info->fprintf_func) (info->stream, "%ld", -value);
+}
+
void m32c_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
case M32C_OPERAND_BIT16RN :
print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0);
break;
+ case M32C_OPERAND_BIT3_S :
+ print_normal (cd, info, fields->f_imm3_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case M32C_OPERAND_BIT32ANPREFIXED :
print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0);
break;
case M32C_OPERAND_DSP_40_U16 :
print_normal (cd, info, fields->f_dsp_40_u16, 0, pc, length);
break;
+ case M32C_OPERAND_DSP_40_U20 :
+ print_normal (cd, info, fields->f_dsp_40_u20, 0, pc, length);
+ break;
case M32C_OPERAND_DSP_40_U24 :
print_normal (cd, info, fields->f_dsp_40_u24, 0, pc, length);
break;
case M32C_OPERAND_DSP_48_U16 :
print_normal (cd, info, fields->f_dsp_48_u16, 0, pc, length);
break;
+ case M32C_OPERAND_DSP_48_U20 :
+ print_normal (cd, info, fields->f_dsp_48_u20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case M32C_OPERAND_DSP_48_U24 :
print_normal (cd, info, fields->f_dsp_48_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
case M32C_OPERAND_DSP_48_U8 :
print_normal (cd, info, fields->f_dsp_48_u8, 0, pc, length);
break;
+ case M32C_OPERAND_DSP_8_S24 :
+ print_normal (cd, info, fields->f_dsp_8_s24, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
case M32C_OPERAND_DSP_8_S8 :
print_normal (cd, info, fields->f_dsp_8_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_IMM_12_S4 :
print_normal (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
+ case M32C_OPERAND_IMM_12_S4N :
+ print_signed4n (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
case M32C_OPERAND_IMM_13_U3 :
print_normal (cd, info, fields->f_imm_13_u3, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_IMM_8_S4 :
print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
+ case M32C_OPERAND_IMM_8_S4N :
+ print_signed4n (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
case M32C_OPERAND_IMM_SH_12_S4 :
print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_12_s4, 0);
break;
print_address (cd, info, fields->f_lab_16_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_24_8 :
- print_address (cd, info, fields->f_lab_24_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_24_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_32_8 :
- print_address (cd, info, fields->f_lab_32_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_32_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_40_8 :
- print_address (cd, info, fields->f_lab_40_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_40_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_5_3 :
print_address (cd, info, fields->f_lab_5_3, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
print_address (cd, info, fields->f_lab_8_16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_8_24 :
- print_address (cd, info, fields->f_lab_8_24, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_8_24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_8_8 :
print_address (cd, info, fields->f_lab_8_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
- int isa;
+ CGEN_BITSET *isa;
int mach;
int endian;
CGEN_CPU_DESC cd;
static cpu_desc_list *cd_list = 0;
cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
- static int prev_isa;
+ static CGEN_BITSET *prev_isa;
static int prev_mach;
static int prev_endian;
int length;
- int isa,mach;
+ CGEN_BITSET *isa;
+ int mach;
int endian = (info->endian == BFD_ENDIAN_BIG
? CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE);
#endif
#ifdef CGEN_COMPUTE_ISA
- isa = CGEN_COMPUTE_ISA (info);
+ {
+ static CGEN_BITSET *permanent_isa;
+
+ if (!permanent_isa)
+ permanent_isa = cgen_bitset_create (MAX_ISAS);
+ isa = permanent_isa;
+ cgen_bitset_clear (isa);
+ cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+ }
#else
isa = info->insn_sets;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
if (cd
- && (isa != prev_isa
+ && (cgen_bitset_compare (isa, prev_isa) != 0
|| mach != prev_mach
|| endian != prev_endian))
{
cd = 0;
for (cl = cd_list; cl; cl = cl->next)
{
- if (cl->isa == isa &&
+ if (cgen_bitset_compare (cl->isa, isa) == 0 &&
cl->mach == mach &&
cl->endian == endian)
{
cd = cl->cd;
+ prev_isa = cd->isas;
break;
}
}
abort ();
mach_name = arch_type->printable_name;
- prev_isa = isa;
+ prev_isa = cgen_bitset_copy (isa);
prev_mach = mach;
prev_endian = endian;
cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
- cl->isa = isa;
+ cl->isa = prev_isa;
cl->mach = mach;
cl->endian = endian;
cl->next = cd_list;
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