+
+ * mips-opc.c: Add r4650 mul instruction.
+
+
+ * mips-opc.c: Add uld and usd macros for unaligned double load and
+ store.
+
+
+ * ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci,
+ mfdcr, mtdcr, icbt, iccci.
+
+start-sanitize-arc
+
+ * arc-dis.c (print_insn): Handle ARC_OPERAND_ADDRESS.
+ * arc-opc.c (arc_operands): New operand 'J' for jump addresses.
+ ('L' operand): Mark as ARC_OPERAND_ADDRESS.
+ (arc_opcodes, j insn): Use 'J' operand type, not 'L'.
+ (arc_opcodes, ld/st insns): Fix address writeback operand letter.
+ (insert_absaddr): New function.
+
+
+ * arc-dis.c (print_insn_arc): Rename to print_insn and make static.
+ New argument `cpu', pass it to arc_opcode_init_tables.
+ Document byte order dependencies. Ignore unsupported insns.
+ (arc_get_disassembler): New function.
+ (print_insn_arc_base, print_insn_arc_host, print_insn_arc_graphics,
+ print_insn_arc_audio): New functions.
+ * arc-opc.c (MULTSHIFT operand): Delete.
+ (UNSIGNED, SATURATION): New operands.
+ (mac, mul, mul64, mulu64): New insns.
+ (ext. asl, asr, lsr, ror): Only available on host and graphics cpus.
+ (padc, padd, pmov, pand, psbc, psub, swap): New insns.
+ (host,graphics,audio extended and auxiliary regs): Define.
+ (ss, sc, mh, ml): New suffixes.
+ (arc_opcode_supported, arc_opval_supported): New functions.
+ (insert_multshift, extract_multshift): Deleted.
+ * disassemble.c (disassembler, case bfd_arch_arc): Call
+ arc_get_disassembler to get disassembler routine.
+end-sanitize-arc
+
+
+ * i960-dis.c (struct tabent, struct sparse_tabent): Change the
+ signed char fields to shorts, more portable.
+
+
+ * i960-dis.c (struct tabent, struct sparse_tabent): Declare the
+ char fields as signed chars, since they may have negative values.
+
+
+ * i386-dis.c (dis386_twobyte): Add cpuid, From Charles Hannum
+
+
+ * ppc-opc.c (extract_bdm): Correct parenthezisation.
+ * ppc-dis.c (print_insn_powerpc): Print .long before unrecognized
+ value.
+
+
+ * ppc-opc.c: Changes based on patch from David Edelsohn
+ (powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of
+ SPR.
+ (FXM_MASK): Define.
+ (insert_tbr): New static function.
+ (extract_tbr): New static function.
+ (XFXFXM_MASK, XFXM): Define.
+ (XSPRBAT_MASK, XSPRG_MASK): Define.
+ (powerpc_opcodes): Add instructions to access special registers by
+ name. Add mtcr and mftbu.
+
+
+ * mips-opc.c (P3): Define.
+ (mips_opcodes): Add mad and madu.
+
+Sun Jan 15 16:32:59 1995 Steve Chamberlain <sac@splat>
+
+ * configure.in: Add W65 support.
+ * disassemble.c: Likewise.
+ * w65-opc.h, w65-dis.c: New files.
+
+
+ * h8300-dis.c (bfd_h8_disassemble): Add support for 2 bit
+ immediates.
+
+start-sanitize-arc
+
+ * arc-dis.c (print_insn_arc): Branch offsets are relative to delay
+ slot.
+ * arc-opc.c (extract_reladdr): New function.
+ (insert_reladdr): Store address right-shifted by 2.
+end-sanitize-arc
+
+
+ * mips-opc.c: Add dli as a synonym for li.
+
+start-sanitize-arc
+
+ * arc-opc.c (insertion fns): Pass pointer to value's table entry.
+ All uses changed.
+ (extraction fns): Insn argument now array of two words. Return pointer
+ to value's table entry. All uses changed.
+ (arc_opcode_lookup_suffix): Exported for arc-dis.c.
+ (insert_multshift, extract_multshift): New fns.
+ (arc_operands): Add support for cache bypass suffix. Add support for
+ predefined aux regs. Modifier bits moved to flags field.
+ (arc_opcodes): Likewise.
+ Add mul/mulu/shift insns. Syntax of zero/sign extension insns changed.
+ New insn rlc. Update to syntax in programmer's manual.
+ (arc_reg_names): Fix typo in lp_count. Add predefined aux regs.
+ (arc_suffixes): New synonyms lo,hs for cs,cc. New suffix for cache
+ bypass.
+ (arc_opcode_init_tables): New argument to indicate cpu type.
+ (insert_reg): Handle predefined aux regs.
+ (extract_reg): Likewise.
+ (lookup_register): New fn.
+ * arc-dis.c (arc_condition_codes): Deleted.
+ (print_insn_arc): Handle insns with 32 bit immediate constants better.
+ Clean up modifier handling. Handle predefined aux regs.
+end-sanitize-arc
+
+
+ * alpha-dis.c (print_insn_alpha): Handle call_pal instruction, and
+ print something for reserved opcode values, even if it won't
+ assemble again.
+
+ * mips-dis.c (_print_insn_mips): When initializing, shift right
+ and mask, to avoid sign extension problems on the Alpha.
+
+ * m68k-dis.c (print_insn_arg, case 'J'): Handle buscr and pcr
+ control registers.
+
+start-sanitize-arc
+
+ * configure.in: Add ARC support.
+ * disassemble.c: Likewise.
+ * arc-dis.c, arc-opc.c: New files.
+end-sanitize-arc
+
+
+ * sh-opc.h (mov.l gbr): Get direction right.
+ * sh-dis.c (print_insn_shx): New function.
+ (print_insn_shl, print_insn_sh): Call print_insn_shx to
+ print opcodes with right byte order.
+
+
+ * ns32k-dis.c (struct ns32k_option): Renamed from struct option,
+ to avoid conflicts with getopt.
+
+
+ * hppa-dis.c (print_insn_hppa): Read the instruction using
+ bfd_getb32, so that it works on a little endian or 64 bit host.
+ Remove unused local variable op.
+
+
+ * mips-opc.c: Use or instead of addu for pseudo-op move, since
+ addu does not work correctly if -mips3.
+
+
+ * a29k-dis.c (print_special): Add special register names defined
+ on 29030, 29040 and 29050.
+ (print_insn): Handle new operand type 'I'.
+
+
+ * Makefile.in (INSTALL): Use top level install.sh script.
+
+
+ * sparc-dis.c: Rewrite to use bitfields, rather than a union, so
+ that it works on a little endian host.
+
+
+ * configure.in: Use ${config_shell} when running config.bfd.
+
+
+ * mips-opc.c (mips_opcodes): "dabs" is only available with -mips3.
+
+
+ * a29k-dis.c (print_insn): Print the opcode.
+
+
+ * mips-opc.c (mips_opcodes): Set WR_t for sc and scd.
+
+
+ * hppa-dis.c (reg_names): Use r26-r23 for arg0-arg3.
+
+
+ * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions
+ which store a value into memory.
+
+
+ * configure.in, Makefile.in, disassemble.c: Add support for the ARM.
+ * arm-dis.c, arm-opc.h: New files.
+
+
+ * Makefile.in (ns32k-dis.o): Add dependency.
+ * ns32k-dis.c (print_insn_arg): Declare initialized local as
+ string, not as array of chars.
+
+
+ * sparc-dis.c (print_insn_sparc): Handle new operand type 'x'.
+
+ * sparc-opc.c: Added sparclite extended FP operations, and
+ versions of v9 impdep* instructions permitting specification of
+ the OPF field.
+
+
+ * i960-dis.c (reg_names): Now const.
+ (struct sparse_tabent): New type, copied from array type in mem
+ function.
+ (ctrl): Local static array ctrl_tab now const.
+ (cobr): Local static array cobr_tab now const.
+ (mem): Local variables reg1, reg2, reg3 now point to const. Local
+ static variable mem_tab no longer explicitly initialized. Changed
+ mem_init to const array of struct sparse_tabent.
+ (reg): Local static variable reg_tab no longer explicitly
+ initialized. Changed reg_init to const array of struct
+ sparse_tabent.
+ (ea): Local static array scale_tab now const.
+
+ start-sanitize-i960xl
+ * i960-dis.c (reg): Added i960XL instructions to reg_init table.
+ (REG_MAX): Updated.
+ end-sanitize-i960xl
+
+
+ * configure.bat: the disassember needs to be enabled for
+ "objdump -d" to work in djgpp.
+
+
+ * ns32k-dis.c: Deleted all code in "#ifdef GDB".
+ (invalid_float): Enabled general version, doesn't require running
+ on ns32k host. Changed to take char* argument, and test for
+ explicitly specified sizes, instead of using sizeof() on host CPU
+ types.
+ (INVALID_FLOAT): Cast first argument.
+ (opt_u, opt_U, opt_O, opt_C, opt_S, list_P532, list_M532,
+ list_P032, list_M032): Now const.
+ (optlist, list_search): Made appropriate arguments now point to
+ const.
+ (print_insn_arg): Changed static array of one-character-string
+ pointers into a static const array of characters; fixed sprintf
+ statement accordingly.
+
+
+ * opcodes/ns32k-dis.c: Semi-new file. Had apparently been dropped
+ from distribution. A ns32k-dis.c from a previous distribution has
+ been brought up to date and supports the new interface.
+
+ * disassemble.c: define ARCH_ns32k and add case bfd_arch_ns32k.
+
+ * configure.in: add bfd_ns32k_arch target support.
+
+ * Makefile.in: add ns32k-dis.o to ALL_MACHINES.
+ Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o.
+
+
+ * h8300-dis.c (bfd_h8_disassemble): Get 16bit branch
+ disassembly right.
+
+
+ * h8300-dis.c, mips-dis.c: Don't use true and false.
+
+
+ * configure.in: Change --with-targets to --enable-targets.
+
+
+ * mips-dis.c (_print_insn_mips): Build a static hash table mapping
+ opcodes to the first instruction with that opcode, to speed
+ Campbell).
+
+
+ * Makefile.in (mostlyclean): Fix typo (was mostyclean).
+
+
+ * configure.bat: update to latest makefile.in
+
+
+ * a29k-dis.c (print_insn): Print 'x' type operand in hex.
+ * h8300-dis.c (bfd_h8_disassemble): Print 16bit rels correctly.
+ * sh-dis.c (print_insn_sh): Don't recur endlessly if delay
+ slot insn is in a delay slot.
+ * z8k-opc.h: (resflg): Fix patterns.
+ * h8500-opc.h Fix CR insn patterns.
+
+
+ * ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and
+ "cmpl" before POWER versions, so that gas -many uses them.
+
+
+ * disassemble.c: New file.
+ * Makefile.in (OFILES): Add disassemble.o.
+ (disassemble.o): Provide dependencies; compile with $(ARCHDEFS).
+ * configure.in: Define ARCHDEFS in Makefile. Code taken from
+ binutils/configure.in.
+
+ * m68k-dis.c (print_insn_m68k): If F_ALIAS flag is set, skip the
+ opcode being examined.
+
+
+ * ppc-opc.c (powerpc_operands): Added RAL, RAM and RAS.
+ (insert_ral, insert_ram, insert_ras): New functions.
+ (powerpc_opcodes): Use RAL for load with update, RAM for lmw, and
+ RAS for store with update.
+
* ppc-opc.c (powerpc_opcodes): Correct fcir. From David Edelsohn
projects / binutils.git / blobdiff