+start-sanitize-d10v
+
+ * d10v-dis.c (dis_long): Handle unknown opcodes.
+
+
+ * d10v-opc.c: Changes to support signed and unsigned numbers.
+ All instructions with the same name that have long and short forms
+ now end in ".l" or ".s". Divs added.
+ * d10v-dis.c: Changes to support signed and unsigned numbers.
+
+
+ * d10v-dis.c: Change all functions to use info->print_address_func.
+
+end-sanitize-d10v
+
+ * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
+ move ccr/sr insns more strict so that the disassembler only
+ selects them when the addressing mode is data register.
+
+start-sanitize-d10v
+ * d10v-opc.c (pre_defined_registers): Declare.
+ * d10v-dis.c (print_operand): Now uses pre_defined_registers
+ to pick a better name for the registers.
+
+end-sanitize-d10v
+
+ * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix
+ operands for fexpand and fpmerge. From Christian Kuehnke
+
+
+ * alpha-dis.c (print_insn_alpha): No longer the user-visible
+ print routine. Take new regnames and cpumask arguments.
+ Kill the environment variable nonsense.
+ (print_insn_alpha_osf): New function. Do OSF/1 style regnames.
+ (print_insn_alpha_vms): New function. Do VMS style regnames.
+ * disassemble.c (disassembler): Test bfd flavour to pick
+ between OSF and VMS routines. Default to OSF.
+
+
+ * configure.in: Call AC_SUBST (INSTALL_SHLIB).
+ * configure: Rebuild.
+ * Makefile.in (install): Use @INSTALL_SHLIB@.
+
+start-sanitize-d10v
+
+ * configure: (bfd_d10v_arch) Add new case.
+ * configure.in: (bfd_d10v_arch) Add new case.
+ * d10v-dis.c: New file.
+ * d10v-opc.c: New file.
+ * disassemble.c (disassembler) Add entry for d10v.
+
+end-sanitize-d10v
+
+ * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
+ to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
+
+
+ * i386-dis.c: Get rid of print_insn_i8086. Use info.mach to
+ distinguish between variants of the instruction set.
+ * sparc-dis.c: Get rid of print_insn_sparclite. Use info.mach to
+ distinguish between variants of the instruction set.
+
+
+ * i386-dis.c (print_insn_i8086): New routine to disassemble using
+ the 8086 instruction set.
+ * i386-dis.c: General cleanups. Make most things static. Add
+ prototypes. Get rid of static variables aflags and dflags. Pass
+ them as args (to almost everything).
+
+
+ * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns.
+
+ * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l".
+
+ * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two
+ if the next arg is marked with SRC_IN_DST. Gross.
+
+ * h8300-dis.c (bfd_h8_disassemble): Print "exr" when
+ we're looking for and find EXR.
+
+ * h8300-dis.c (bfd_h8_disassemble): We don't have a match
+ if we're looking for KBIT and we don't find it.
+
+ * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits
+ for L_3 and L_2.
+
+ * h8300-dis.c (bfd_h8_disassemble): Don't set plen for
+ 3bit immediate operands.
+
+
+ * Released binutils 2.7.
+
+ * alpha-opc.c: Add new case of "mov". From Klaus Kaempf
+
+
+ * alpha-opc.c: Correct second case of "mov" to use OPRL.
+
+
+ * sparc-dis.c (print_insn_sparclite): New routine to print
+ sparclite instructions.
+
+
+ * m68k-opc.c (m68k_opcodes): Add coldfire support.
+
+
+ * sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS,
+ #ASI_NUCLEUS_LITTLE. Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L
+ to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE.
+
+
+ * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir):
+ Use autoconf-set values.
+ (docdir, oldincludedir): Removed.
+ * configure.in (AC_PREREQ): autoconf 2.5 or higher.
+
+
+ * alpha-opc.c: New file.
+ * alpha-opc.h: Remove.
+ * alpha-dis.c: Complete rewrite to use new opcode table.
+ * configure.in: For bfd_alpha_arch, use alpha-opc.o.
+ * configure: Rebuild with autoconf 2.10.
+ * Makefile.in (ALL_MACHINES): Add alpha-opc.o.
+ (alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not
+ alpha-opc.h.
+ (alpha-opc.o): New target.
+
+
+ * sparc-dis.c (print_insn_sparc): Remove unused local variable i.
+ Set imm_added_to_rs1 even if the source and destination register
+ are not the same.
+
+ * sparc-opc.c: Add some two operand forms of the wr instruction.
+
+
+ * h8300-dis.c (bfd_h8_disassemble): Rename "hmode" argument
+ to just "mode".
+
+ * disassemble.c (disassembler): Handle H8/S.
+ * h8300-dis.c (print_insn_h8300s): New function for H8/S.
+
+
+ * sparc-opc.c: Add beq/teq as aliases for be/te.
+
+ * ppc-opc.c: Fix fcmpo opcode. From Sergei Steshenko
+
+
+ * makefile.vms: New file.
+
+ * alpha-dis.c (print_insn_alpha): Print lda ra,lit(rz) as mov.
+
+
+ * h8300-dis.c (bfd_h8_disassemble): Always print ABS8MEM with :8,
+ regardless of plen.
+
+
+ * i386-dis.c (OP_OFF): Call append_prefix.
+
+
+ * ppc-opc.c (instruction encoding macros): Add explicit casts to
+ unsigned long to silence a warning from the Solaris PowerPC
+ compiler.
+
+
+ * sparc-opc.c (sparc_opcodes): Add ultrasparc vis extensions.
+
+
+ * sparc-dis.c (X_IMM,X_SIMM): New macros.
+ (X_IMM13): Delete.
+ (print_insn_sparc): Merge cases i,I,j together. New cases X,Y.
+ * sparc-opc.c (sparc_opcodes): Use X for 5 bit shift constants,
+ Y for 6 bit shift constants. Rewrite entries for crdcxt, cwrcxt,
+ cpush, cpusha, cpull sparclet insns.
+
+
+ * sparc-dis.c (compute_arch_mask): Replace ANSI style def with K&R.
+
+
+ * sparc-opc.c: Set F_FBR on floating point branch instructions.
+ Set F_FLOAT on other floating point instructions.
+
+
+ * ppc-opc.c (PPC860): Macro for 860/821 specific instructions and
+ registers.
+ (powerpc_opcodes): Add 860/821 specific SPRs.
+
+
+ * configure.in: Permit --enable-shared to specify a list of
+ directories. Set and substitute BFD_PICLIST.
+ * configure: Rebuild.
+ * Makefile.in (BFD_PICLIST): Rename from BFD_LIST. Change all
+ uses. Set to @BFD_PICLIST@.
+
+
+ * h8300-dis.c (bfd_h8_disassemble): Use "bit" for L_3 immediates,
+ not "abs", which may be needed for the absolute in something
+ like btst #0,@10:8. Print L_3 immediates separately from other
+ immediates. Change ABSMOV reference to ABS8MEM.
+
+
+ * sparc-dis.c (opcodes_initialized): Move inside print_insn_sparc.
+ (current_arch_mask): New static global.
+ (compute_arch_mask): New static function.
+ (print_insn_sparc): Delete sparc_v9_p. New static local
+ current_mach. Resort opcode table if current_mach changes.
+ Generalize "insn not supported" test.
+ (compare_opcodes): Prefer supported opcodes to nonsupported ones.
+ Delete test for v9/!v9.
+ * sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK.
+ (v6notlet): Define.
+ (brfc): Split into CBR and FBR for coprocessor/fp branches.
+ (brfcx): Renamed to FBRX.
+ (condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard
+ coprocessor mnemonics are not supported on the sparclet).
+ (condf): Renamed to CONDF.
+ (SLCBCC2): Delete F_ALIAS flag.
+
+
+ * sparc-opc.c (sparc_opcodes): rd must be 0 for
+ mov foo,{%y,%psr,%wim,%tbr}. Support mov foo,%asrX.
+
+
+ * Makefile.in (config.status): Depend upon BFD VERSION file, so
+ that the shared library version number is set correctly.
+
+
+ * configure.in: Use AC_CHECK_TOOL to find ar and ranlib. From
+ * configure: Rebuild.
+
+
+ * z8kgen.c (internal, gas): Call xmalloc rather than unchecked
+ malloc.
+
+
+ * configure: Rebuild with autoconf 2.8.
+
+
+ * sparc-dis.c (print_insn_sparc): Handle 'O' operand char like 'r'.
+ * sparc-opc.c (sparc_opcodes): Use 'O' operand char for `neg reg'.
+
+
+ * configure.in: Don't set SHLIB or SHLINK to an empty string,
+ since they appear as targets in Makefile.in.
+ * configure: Rebuild.
+
+
+ * mpw-make.sed: Edit out shared library support bits.
+
+
+ * sparc-opc.c (v8,v6notv9): Add MASK_SPARCLET.
+ (sparc_opcode_archs): Add MASK_V8 to sparclet entry.
+ (sparc_opcodes): Add sparclet insns.
+ (sparclet_cpreg_table): New static local.
+ (sparc_{encode,decode}_sparclet_cpreg): New functions.
+ * sparc-dis.c (print_insn_sparc): Handle sparclet cpregs.
+
+
+ * i386-dis.c (index16): New static variable.
+ (putop): Print jecxz for 32 bit case, jcxz for 16 bit, not the
+ other way around.
+ (OP_indirE): Return result of OP_E.
+ (OP_E): Check for 16 bit addressing mode, and disassemble
+ correctly. Optimised 32 bit case a little. Don't print
+ "(base,index,scale)" when sib specifies only an offset.
+
+
+ * configure.in: Set and substitute SHLIB_DEP.
+ * configure: Rebuild.
+ * Makefile.in (SHLIB_DEP): New variable.
+ (LIBIBERTY_LISTS, BFD_LIST): New variables.
+ (stamp-piclist): Depend upon LIBIBERTY_LISTS and BFD_LIST. If
+ COMMON_SHLIB, add them to piclist with appropriate modifications.
+ ($(SHLIB)): Depend upon $(SHLIB_DEP). Don't check COMMON_SHLIB
+ here: just use piclist.
+
+
+ * sparc-dis.c (MASK_V9,V9_ONLY_P,V9_P): Define.
+ (print_insn_sparc): Rewrite v9/not-v9 tests.
+ (compare_opcodes): Likewise.
+ * sparc-opc.c (MASK_<ARCH>): Define.
+ (v6,v7,v8,sparclite,v9,v9a): Redefine.
+ (sparclet,v6notv9): Define.
+ (sparc_opcode_archs): Delete member `conflicts'. Add `supported'.
+ (sparc_opcodes): Delete F_NOTV9, use v6notv9 instead.
+
+
+ * configure.in: Call AC_PROG_CC before configure.host.
+ * configure: Rebuild.
+
+ * Makefile.in (SONAME): Remove leading ../bfd/ from $(SHLIB).
+
+
+ * i386-dis.c (onebyte_has_modrm): New static array.
+ (twobyte_has_modrm): New static array.
+ (print_insn_i386): Only fetch the mod/reg/rm byte if it is needed.
+
+
+ * Makefile.in ($(SHLINK)): Check ts against $(SHLIB), not
+ $(SHLINK).
+
+
+ * ppc-opc.c (PPC): Undef, so default defination on Windows NT
+ doesn't conflict.
+
+
+ * m68k-opc.c (m68k_opcodes): The bkpt instruction is supported on
+ m68010up, not just m68020up | cpu32.
+
+ * Makefile.in (SONAME): New variable.
+ ($(SHLINK)): Make a link to the transformed name, as well.
+ (stamp-tshlink): New target.
+ (install): Skip stamp-tshlink during install.
+
+
+ * configure.in: Call AC_ARG_PROGRAM.
+ * configure: Rebuild.
+ * Makefile.in (program_transform_name): New variable.
+ (install): Transform library name before installing it.
+
+
+ * i960-dis.c (mem): Add HX dcinva instruction.
+
+ Support for building as a shared library, based on patches from
+ * configure.in: Add AC_ARG_ENABLE for shared and commonbfdlib.
+ New substitutions: ALLLIBS, PICFLAG, SHLIB, SHLIB_CC,
+ SHLIB_CFLAGS, COMMON_SHLIB, SHLINK.
+ * configure: Rebuild.
+ * Makefile.in (ALLLIBS): New variable.
+ (PICFLAG, SHLIB, SHLIB_CC, SHLIB_CFLAGS): New variables.
+ (COMMON_SHLIB, SHLINK): New variables.
+ (.c.o): If PICFLAG is set, compile twice, once PIC, once normal.
+ (STAGESTUFF): Remove variable.
+ (all): Depend upon $(ALLLIBS) rather than $(TARGETLIB).
+ (stamp-piclist, piclist): New targets.
+ ($(SHLIB), $(SHLINK)): New targets.
+ ($(OFILES)): Depend upon stamp-picdir.
+ (disassemble.o): Build twice if PICFLAG is set.
+ (MOSTLYCLEAN): Add pic/*.o.
+ (clean): Remove $(SHLIB), $(SHLINK), piclist, and stamp-piclist.
+ (distclean): Remove pic and stamp-picdir.
+ (install): Install shared libraries.
+ (stamp-picdir): New target.
+
+
+ * sparc-dis.c (print_insn_sparc): Delete DISASM_RAW_INSN support.
+ Print unknown instruction as "unknown", rather than in hex.
+
+
+ * dis-buf.c: Include "sysdep.h" before "dis-asm.h".
+
+
+ * sparc-opc.c (sparc_opcode_archs): Mark v8/sparclite as conflicting.
+
+
+ * i386-dis.c (print_insn_i386): Only fetch the mod/reg/rm byte
+ when necessary. From Ulrich Drepper
+
+
+ * sparc-dis.c (print_insn_sparc): NUMOPCODES replaced with
+ sparc_num_opcodes. Update architecture enum values.
+ * sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname.
+ (sparc_opcode_lookup_arch): New function.
+ (sparc_num_opcodes): Renamed from bfd_sparc_num_opcodes.
+ (sparc_opcodes): Add v9a shutdown insn.
+
+
+ * sparc-dis.c (print_insn_sparc): Renamed from print_insn.
+ If DISASM_RAW_INSN, print insn in hex. Handle v9a as opcode
+ architecture.
+ (print_insn_sparc64): Deleted.
+ * disassemble.c (disassembler, case bfd_arch_sparc): Always use
+ print_insn_sparc.
+
+ * sparc-opc.c (architecture_pname): Add v9a.
+
+
+ * alpha-opc.h (alpha_insn_set): VAX floating point opcode was
+ incorrectly defined as 0x16 when it should be 0x15.
+ (FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits!
+ (alpha_insn_set): added cvtst and cvttq float ops. Also added
+ excb (exception barrier) which is defined in the Alpha
+ Architecture Handbook version 2.
+ * alpha-dis.c (print_insn_alpha): Fixed special-case decoding for
+ OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be
+ disassembled as or, for example.
+
+
+ * mips-dis.c (print_insn_arg): Print cases 'i' and 'u' in hex.
+ (_print_insn_mips): Change i from int to unsigned int.
+
+
+ * ppc-opc.c (powerpc_opcodes): tlbi POWER opcode form different
+ from tlbie PowerPC opcode. Add PPC603 tlbld and tlbli.
+
+
+ * i386-dis.c: Added Pentium Pro instructions.
+
+
+ * ppc-opc.c (fsqrt{,.}): Duplicate for PowerPC in addition to
+ being for Power2.
+
+
+ * sh-opc.h (sh_nibble_type): Added REG_B.
+ (sh_arg_type): Added A_REG_B.
+ (sh_table): Added pref and bank reg versions of ldc, ldc.l, stc
+ and stc.l opcodes.
+ * sh-dis.c (print_insn_shx): Added cases for REG_B and A_REG_B.
+
+
+ * disassemble.c (disassembler): Use new bfd_big_endian macro.
+
+
+ * Makefile.in (distclean): Remove stamp-h. From Ronald
+
+
+ * alpha-dis.c (print_insn_alpha): fixed decoding of cpys
+ instruction.
+
+
+ * sh-opc.h (sh_arg_type): Added A_SSR and A_SPC.
+ (sh_table): Added many SH3 opcodes.
+ * sh-dis.c (print_insn_shx): Added cases for A_SSR and A_SPC.
+
+
+ * ppc-opc.c (subfc., subfco): Mark this PPCCOM, not PPC.
+ (subco,subco.): Mark this PPC, not PPCCOM.
+
+
+ * configure: Rebuild with autoconf 2.7.
+
+
+ * configure: Rebuild with autoconf 2.6.
+
+
+ * configure.in: Sort list of architectures. Accept but do nothing
+ for alliant, convex, pyramid, romp, and tahoe.
+
+
+ * a29k-dis.c (print_special): Change num to unsigned int.
+
+
+ * a29k-dis.c (print_insn): Cast insn24 to unsigned long when
+ shifting it.
+
+
+ * configure.in: Call AC_CHECK_PROG to find and cache AR.
+ * configure: Rebuilt.
+
+
+ * configure.in: Add case for bfd_i860_arch.
+ * configure: Rebuild.
+
+
+ * m68k-opc.c (m68k_opcodes): Correct fmoveml operands.
+ * m68k-dis.c (NEXTSINGLE): Change i to unsigned int.
+ (NEXTDOUBLE): Likewise.
+ (print_insn_m68k): Don't match fmoveml if there is more than one
+ register in the list.
+ (print_insn_arg): Handle a place of '8' for a type of 'L'.
+
+
+ * m68k-opc.c: Use #W rather than #w.
+ * m68k-dis.c (print_insn_arg): Handle new 'W' place.
+
+
+ * m68k-opc.c (m68k_opcode_aliases): Add dbfw as an alias for dbf,
+ and likewise for all the dbxx opcodes.
+
+
+ * arc-dis.c: Include elf-bfd.h rather than libelf.h.
+
+
+ * mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added
+ the VR4100 specific instructions to the mips_opcodes structure.
+
+
+ * mpw-config.in, mpw-make.sed: Remove ugly workaround for
+ ugly Metrowerks bug in CW6, is fixed in CW7.
+
+
+ * ppc-opc.c (whole file): Add flags for common/any support.
+
+
+ * Makefile.in (BISON): Remove macro.
+ (FLAGS_TO_PASS): Remove BISON.
+
+
+
+ * m68k-dis.c (print_insn_m68k): Recognize all two-word
+ instructions that take no args by looking at the match mask.
+ (print_insn_arg): Always print "%" before register names.
+ [case 'c']: Use "nc" for the no-cache case, as recognized by gas.
+ [case '_']: Don't print "@#" before address.
+ [case 'J']: Use "%s" as format string, not register name.
+ [case 'B']: Treat place == 'C' like 'l' and 'L'.
+
+
+ * i386-dis.c: Describe cmpxchg8b operand, and spell the opcode
+ name correctly.
+
+
+
+ * alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added.
+ (alpha_insn_set): added definitions for VAX floating point
+ instructions (Unix compilers don't generate these, but handcoded
+ assembly might still use them).
+
+ * alpha-dis.c (print_insn_alpha): added support for disassembling
+ the miscellaneous instructions in the Alpha instruction set.
+
+
+ * mpw-config.in: Add m68k-opc.c.o to BFD_MACHINES for m68k,
+ no longer create sysdep.h, sed ppc-opc.c to work around a
+ serious Metrowerks C bug.
+ * mpw-make.in: Remove.
+ * mpw-make.sed: New file, used by mpw-configure to edit
+ Makefile.in into an MPW makefile.
+
+
+ * Makefile.in (maintainer-clean): New synonym for realclean.
+
+
+ * m68k-opc.c: Split pmove patterns which use 'P' into patterns
+ which use '0', '1', and '2' instead. Specify the proper size for
+ a pmove immediate operand. Correct the pmovefd patterns to be
+ moves to a register, not from a register.
+ * m68k-dis.c (print_insn_arg): Replace 'P' with '0', '1', '2'.
+
+
+ * sparc-opc.c (sparc_opcodes): Mark all insns that reference
+ %psr, %wim, %tbr as F_NOTV9.
+
+
+ * Makefile.in (Makefile): Just rebuild Makefile when running
+ config.status.
+ (config.h, stamp-h): New targets.
+ * configure.in: Call AC_CONFIG_HEADER and AC_CANONICAL_SYSTEM
+ earlier. Don't bother to call AC_ARG_PROGRAM. Touch stamp-h when
+ rebuilding config.h.
+ * configure: Rebuild.
+
+ * mips-opc.c: Change unaligned loads and stores with "t,A"
+ operands to use "t,A(b)".
+
+
+ * sh-dis.c (print_insn_shx): Add F_FR0 support.
+
+
+ * sh-dis.c (print_insn_shx): Change loop over op->arg[n] to iterate
+ until 3 instead of until 2.
+
+
+ * Makefile.in (ALL_CFLAGS): Define.
+ (.c.o, disassemble.o): Use $(ALL_CFLAGS).
+ (MOSTLYCLEAN): Add config.log.
+ (distclean): Don't remove config.log.
+ * configure.in: Substitute HDEFINES.
+ * configure: Rebuild.
+
+
+ * sh-opc.h (sh_arg_type): Add F_FR0.
+ (sh_table, case fmac): Add F_FR0 as first argument.
+
+
+ * sh-opc.h (sh_opcode_info): Increase arg array size to 4.
+
+
+ * sparc-dis.c: Remove all references to NO_V9.
+
+
+ * aclocal.m4: Just include ../bfd/aclocal.m4.
+ * configure: Rebuild.
+
+
+ * sparc-dis.c (X_DISP19): Define.
+ (print_insn, case 'G'): Use it.
+ (print_insn, case 'L'): Sign extend displacement.
+
+
+ * configure.in: Run ../bfd/configure.host before AC_PROG_CC.
+ Subsitute CFLAGS and AR. Call AC_PROG_INSTALL. Don't substitute
+ host_makefile_frag or frags.
+ * aclocal.m4: New file.
+ * configure: Rebuild.
+ * Makefile.in (INSTALL): Set to @INSTALL@.
+ (INSTALL_PROGRAM): Set to @INSTALL_PROGRAM@.
+ (INSTALL_DATA): Set to @INSTALL_DATA@.
+ (AR): Set to @AR@.
+ (AR_FLAGS): Set to rc rather than qc.
+ (CC): Define as @CC@.
+ (CFLAGS): Set to @CFLAGS@.
+ (@host_makefile_frag@): Remove.
+ (config.status): Remove dependency upon @frags@.
+
+ * configure.in: ../bfd/config.bfd now just sets shell variables.
+ Use them rather than looking through target Makefile fragments.
+ * configure: Rebuild.
+
+
+ * sh-opc.h (ftrc): Change FPUL_N to FPUL_M.
+
+
+ * sparc-opc.c (sparc_opcodes): Delete duplicate wr %y insn.
+ Add clrx, iprefetch, signx, clruw, cas, casl, casx, casxl synthetic
+ sparc64 insns.
+
+ * sparc-opc.c (sparc_opcodes): Fix prefetcha insn.
+ (lookup_{name,value}): New functions.
+ (prefetch_table): New static local.
+ (sparc_{encode,decode}_prefetch): New functions.
+ * sparc-dis.c (print_insn): Handle '*' arg (prefetch function).
+
+
+ * sh-opc.h: Add blank lines to improve readabililty of sh3e
+ instructions.
+
+
+ * sh-dis.c: Correct comment on first line of file.
+
+
+ * disassemble.c (disassembler): Handle bfd_mach_sparc64.
+
+ * sparc-opc.c (asi, membar): New static locals.
+ (sparc_{encode,decode}_{asi,membar}): New functions.
+ (sparc_opcodes, membar insn): Fix.
+ * sparc-dis.c (print_insn): Call sparc_decode_asi.
+ Support decoding of membar masks.
+ (X_MEMBAR): Define.
+
+
+ * m68k-opc.c (m68k_opcode_aliases): Add br, brs, brb, brw, brl.
+
+
+ * m68k-opc.c (m68k_opcode_aliases): Add bhib as an alias for bhis,
+ and likewise for the other branches. Add bhs as an alias for bcc,
+ and likewise for the size variants. Add dbhs as an alias for
+ dbcc.
+
+
+ * sh-opc.h (FP sts instructions): Update to match reality.
+
+
+ * m68k-dis.c: (fpcr_names): Add % before all register names.
+ (reg_names): Likewise.
+ (print_insn_arg): Don't explicitly print % before register names.
+ Add % before register names in static array names. In case 'r',
+ print data registers as `@(Dn)', not `Dn@'. When printing a
+ memory address, don't print @# before it.
+ (print_indexed): Change base_disp and outer_disp from int to
+ bfd_vma. Print using MIT syntax, not mutant invalid Motorola
+ syntax. Sign extend 8 byte displacement correctly.
+ (print_base): Print using MIT syntax. Print zpc when appropriate.
+ Change parameter disp from int to bfd_vma.
+
+ * m68k-opc.c (m68k_opcode_aliases): Add jsrl and jsrs as aliases
+ for jsr.
+
+
+ * sh-dis.c (print_insn_shx): Handle new operand types F_REG_N,
+ F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N.
+ * sh-opc.h (sh_arg_type): Add new operand types.
+ (sh_table): Add new opcodes from SH3E Floating Point ISA.
+
+
+ * Makefile.in (distclean): Remove generated file config.h.
+
+
+ * Makefile.in (distclean): Remove generated file config.h.
+
+
+ * m68k-opc.c: New file, holding tables from include/opcode/m68k.h.
+ Clean up tables.
+ * m68k-dis.c: Remove BREAK_UP_BIG_DECL stuff.
+ (opcode): Remove.
+ (print_insn_m68k): Change d to be const. Use m68k_numopcodes
+ rather than numopcodes. Use m68k_opcodes rather than removed
+ opcode function. Don't check F_ALIAS.
+ (print_insn_arg): Change first parameter to be const char *.
+ * Makefile.in (ALL_MACHINES): Add m68k-opc.o.
+ (m68k-opc.o): New target.
+ * configure.in: Build m68k-opc.o for bfd_m68k_arch.
+ * configure: Rebuild.
+
+
+ * sparc-dis.c (HASH_SIZE, HASH_INSN): Define.
+ (opcode_bits, opcode_hash_table): New variables.
+ (opcodes_initialized): Renamed from opcodes_sorted.
+ (build_hash_table): New function.
+ (is_delayed_branch): Use hash table.
+ (print_insn): Renamed from print_insn_sparc, made static.
+ Build and use hash table. If !sparc64, ignore sparc64 insns,
+ and vice-versa if sparc64.
+ (print_insn_sparc, print_insn_sparc64): New functions.
+ (compare_opcodes): Move sparc64 opcodes to end.
+ Print commutative insns with constant second.
+ * sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS.
+
+
+ * sh-dis.c (print_insn_shx): Remove unused local dslot. Use
+ print_address_func for A_BDISP12 and A_BDISP8. Correct test which
+ avoids printing a delay slot in a delay slot.
+ * sh-opc.h (sh_table): Fully bracket last entry.
+
+
+ * sparc-opc.c (sllx, srax, srlx): Fix disassembly.
+
+
+ * configure.in: Get host_makefile_frag from ${srcdir}.
+
+ * configure.in: Autoconfiscated. Check for string[s].h. Create
+ config.h from config.in. Don't set up sysdep.h link.
+ * sysdep.h: New file.
+ * configure, config.in: New files, generated from configure.in.
+ * Makefile.in: Updated to be processed autoconf-style.
+ (distclean): Keep sysdep.h. Remove config.log and config.cache.
+ (Makefile): Depend on config.status.
+ (config.status): New rule.
+ * configure.bat: Update Makefile substitutions.
+
+
+ * mips-opc.c (L1): Define.
+ (mips_opcodes): Add R4010 instructions: flushi, flushd, flushid,
+ addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti,
+ and wb.
+
+
+ * mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu
+ if ISA 3 and addu otherwise, replacing or, since some MIPS chips
+ have multiple add units but only a single logical unit.
+
+ * ppc-opc.c (powerpc_operands): Change CR to use a bitsize of 3,
+ shifted by 18, without any insertion or extraction function.
+ (insert_cr, extract_cr): Remove.
+
+start-sanitize-arc
+
+ * Makefile.in (ALL_MACHINES): Add arc-dis.o and arc-opc.o.
+
+end-sanitize-arc
+
+ * m68k-dis.c (print_insn_arg, print_indexed): Print "%" before
+ register names.
+
+
+ * mpw-config.in: Add sh and i386 configs, remove sparc config.
+ * sh-opc.h: Add copyright.
+
+
+ * Makefile.in (crunch-m68k): Delete extra target accidentally
+ checked in a while ago.
+
+
+ * sh-opc.h (sh_table): Add SH3 support.
+
+
+ * sh-opc.h: Added bsrf and braf.
+
+
+ * arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete
+ bogus [ls]fm{ea,fd} patterns.
+
+ * arm-opc.h (arm_opcodes): Correct typos in stm, ldm, std, and ldc.
+ * arm-dis.c (print_insn_arm): Make GIVEN a parameter, don't try and
+ initialize it from memory. Make function static.
+ (print_insn_{big,little}_arm): New functions.
+ * disassemble.c (disassembler, case bfd_arch_arm): Disassemble for
+ the correct endianness.
+
+start-sanitize-arc
+
+ * arc-opc.c (arc_opcodes): Add ARC_OPCODE_CONDITIONAL_BRANCH flag.
+ (arc_suffixes): Use ARC_DELAY_{NONE,NORMAL,JUMP}.
+end-sanitize-arc
+
+
+ * sh-opc.h (sh_nibble_type, sh_arg_type): remove trailing , from
+ enum list.
+
+
+ * m68k-dis.c (opcode): Finish change made by Kung Hsu on April
+ 17th, so that it builds again using GCC as the compiler.
+
+
+ * mips-dis.c (print_insn_little_mips): Cast return value from
+ bfd_getl32 from bfd_vma to unsigned long, because _print_insn_mips
+ expects an unsigned long, and that might be fewer words of
+ argument storage (e.g., if bfd_vma is long long on a 32-bit
+ machine).
+ (print_insn_big_mips): Likewise with bfd_getb32 value.
+ (_print_insn_mips): Now static.
+
+
+ * m68k-dis.c: Take out #define BREAK_UP_BIG_DECL kludge, because
+ gcc memory hog problem with initializer is fixed.
+
+start-sanitize-arc
+
+ * arc-opc.c (NULL): Define.
+ (arc_operands, insn fields u,s): Delete.
+ (arc_operands, insn fields a,b,c): Mark as signed.
+ (arc_opcodes): No longer const, links computed at run-time.
+ (arc_opcodes, mac/mul insns): Breakout suffixes as we don't handle
+ suffixes that affect the insn code.
+ (arc_opcodes): Resort table to macros are first.
+ (arc_opcodes, ld [b,c] entry): Add %Q to prevent shimms.
+ (arc_opcodes, st [b] entry): Likewise.
+ (arc_opcodes, st [b,d] entry): Fix mask, value.
+ (arc_reg_names): Add entries for r29, r30, r31, r60.
+ (opcode_map, icode_map): New static globals.
+ (arc_opcode_init_tables): Initialize them.
+ (arc_opcode_lookup_asm, arc_opcode_lookup_dis): New functions.
+ (insert_shimmoffset): Signal error if register present.
+ Validate constant.
+ * arc-dis.c (print_insn): Call arc_opcode_lookup_dis.
+end-sanitize-arc
+
+
+ Merge in support for Mac MPW as a host.
+ (Old change descriptions retained for informational value.)
+
+ * mpw-config.in (archname): Compute from the config.
+ (BFD_MACHINES, ARCHDEFS): Put into mk.tmp.
+
+ * mpw-config.in (target_arch): Compute from canonical target.
+ (m68k, mips, powerpc, sparc): Add architectures.
+ * mpw-make.in (disassemble.c.o): Add.
+ (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far).
+
+ * mpw-config.in (BFD_MACHINES): Set to a default value.
+ * mpw-make.in (BFD_MACHINES): Remove wired-in value.
+
+ * mpw-make.in (CSEARCH): Add extra-include to search path.
+
+ * mpw-config.in (varargs.h): Don't create.
+ (sysdep.h): Create using forward-include.
+ * mpw-make.in (CSEARCH): Add include/mpw to search path.
+
+ * mpw-config.in: New file, MPW version of configure.in.
+ * mpw-make.in: New file, MPW version of Makefile.in.
+
+start-sanitize-arc
+
+ * arc-dis.c (print_insn): New parameter `big_p'. Callers updated.
+ Call arc_get_opcode_mach to map bfd mach number to opcode value.
+ (print_insn_*): Pass bfd mach number, not opcode version.
+ * arc-opc.c (arc_get_opcode_mach): New function.
+end-sanitize-arc
+
+
+ * alpha-dis.c (print_insn_alpha): Put empty statement after
+ default label.
+
+
+ * hppa-dis.c (sign_extend): Delete, redundant with libhppa.h version.
+ (low_sign_extend): Likewise.
+ (get_field): Delete unused function.
+ (set_field, deposit_14, deposit_21): Likewise.
+
+
+ * i386-dis.c: Support for more pentium opcodes. From Guy Harris
+
+
+
+ * alpha-opc.h (OSF_ASMCODE): define
+ print pal-code names as defined in App C of the
+ Alpha Architecture Reference Manual
+
+ * alpha-dis.c: cleaned up output
+ print stylized code forms as defined in App A.4.3 of the
+ Alpha Architecture Reference Manual
+
+
+ * mips-opc.c: Add new mips4 instructions. Don't set INSN_RFE for
+ `rfe'.
+ * mips-dis.c (print_insn_arg): Handle new argument types 'h', 'R',
+ 'N', and 'M'.
+
+
+ * m68k-dis.c (opcode): New function. Returns address of opcode
+ table entry given index, even if the opcode table was split to
+ work around gcc bugs.
+ (print_insn_m68k): Call opcode instead of referencing m68k_opcodes
+ directly.
+ (BREAK_UP_BIG_DECL): Make secondary array static and const.
+ (reg_names): Now const.
+ (print_insn_arg): Arrays cacheFieldName and names now const.
+ (print_indexed): Array scales now const.
+
+start-sanitize-arc
+
+ * arc-dis.c (print_insn_arc_base): Split into big and little fns.
+ (print_insn_arc_{host,graphics,audio}): Likewise.
+ (print_insn): Add prototype.
+ (arc_get_disassembler): New arg `big_p'. Return little or big
+ print fn accordingly.
+ * arc-opc.c (arc_opcode_init_tables): Init arc_operand_map once.
+ (arc_opcode_supported): Use ARC_OPCODE_CPU to ignore byte order.
+ (arc_opval_supported): Likewise.
+ * disassemble.c (disassembler): Pass big endian flag to
+ arc_get_disassembler.
+end-sanitize-arc
+
+
+ * ppc-opc.c: Sort recently added instructions by minor opcode
+ number within major opcode number.
+
+
+ * hppa-dis.c: Include libhppa.h.
+
+
+ * mips-opc.c: Change dli to use M_DLI, and add dla.
+
+
+ * Makefile.in (ALL_MACHINES): Add w65-dis.o.
+
+start-sanitize-arc
+
+ * arc-dis.c (arc_get_disassembler): Change argument to int,
+ one of bfd_mach_arc_xxx. All callers updated.
+end-sanitize-arc
+
+
+ * mips-opc.c: Add r4650 mul instruction.
+
+
+ * mips-opc.c: Add uld and usd macros for unaligned double load and
+ store.
+
+
+ * ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci,
+ mfdcr, mtdcr, icbt, iccci.
+
+start-sanitize-arc
+
+ * arc-dis.c (print_insn): Handle ARC_OPERAND_ADDRESS.
+ * arc-opc.c (arc_operands): New operand 'J' for jump addresses.
+ ('L' operand): Mark as ARC_OPERAND_ADDRESS.
+ (arc_opcodes, j insn): Use 'J' operand type, not 'L'.
+ (arc_opcodes, ld/st insns): Fix address writeback operand letter.
+ (insert_absaddr): New function.
+
+
+ * arc-dis.c (print_insn_arc): Rename to print_insn and make static.
+ New argument `cpu', pass it to arc_opcode_init_tables.
+ Document byte order dependencies. Ignore unsupported insns.
+ (arc_get_disassembler): New function.
+ (print_insn_arc_base, print_insn_arc_host, print_insn_arc_graphics,
+ print_insn_arc_audio): New functions.
+ * arc-opc.c (MULTSHIFT operand): Delete.
+ (UNSIGNED, SATURATION): New operands.
+ (mac, mul, mul64, mulu64): New insns.
+ (ext. asl, asr, lsr, ror): Only available on host and graphics cpus.
+ (padc, padd, pmov, pand, psbc, psub, swap): New insns.
+ (host,graphics,audio extended and auxiliary regs): Define.
+ (ss, sc, mh, ml): New suffixes.
+ (arc_opcode_supported, arc_opval_supported): New functions.
+ (insert_multshift, extract_multshift): Deleted.
+ * disassemble.c (disassembler, case bfd_arch_arc): Call
+ arc_get_disassembler to get disassembler routine.
+end-sanitize-arc
+
+
+ * i960-dis.c (struct tabent, struct sparse_tabent): Change the
+ signed char fields to shorts, more portable.
+
+
+ * i960-dis.c (struct tabent, struct sparse_tabent): Declare the
+ char fields as signed chars, since they may have negative values.
+
+
+ * i386-dis.c (dis386_twobyte): Add cpuid, From Charles Hannum
+
+
+ * ppc-opc.c (extract_bdm): Correct parenthezisation.
+ * ppc-dis.c (print_insn_powerpc): Print .long before unrecognized
+ value.
+
+
+ * ppc-opc.c: Changes based on patch from David Edelsohn
+ (powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of
+ SPR.
+ (FXM_MASK): Define.
+ (insert_tbr): New static function.
+ (extract_tbr): New static function.
+ (XFXFXM_MASK, XFXM): Define.
+ (XSPRBAT_MASK, XSPRG_MASK): Define.
+ (powerpc_opcodes): Add instructions to access special registers by
+ name. Add mtcr and mftbu.
+
+
+ * mips-opc.c (P3): Define.
+ (mips_opcodes): Add mad and madu.
+
+Sun Jan 15 16:32:59 1995 Steve Chamberlain <sac@splat>
+
+ * configure.in: Add W65 support.
+ * disassemble.c: Likewise.
+ * w65-opc.h, w65-dis.c: New files.
+
+
+ * h8300-dis.c (bfd_h8_disassemble): Add support for 2 bit
+ immediates.
+
+start-sanitize-arc
+
+ * arc-dis.c (print_insn_arc): Branch offsets are relative to delay
+ slot.
+ * arc-opc.c (extract_reladdr): New function.
+ (insert_reladdr): Store address right-shifted by 2.
+end-sanitize-arc
+
+
+ * mips-opc.c: Add dli as a synonym for li.
+
+start-sanitize-arc
+
+ * arc-opc.c (insertion fns): Pass pointer to value's table entry.
+ All uses changed.
+ (extraction fns): Insn argument now array of two words. Return pointer
+ to value's table entry. All uses changed.
+ (arc_opcode_lookup_suffix): Exported for arc-dis.c.
+ (insert_multshift, extract_multshift): New fns.
+ (arc_operands): Add support for cache bypass suffix. Add support for
+ predefined aux regs. Modifier bits moved to flags field.
+ (arc_opcodes): Likewise.
+ Add mul/mulu/shift insns. Syntax of zero/sign extension insns changed.
+ New insn rlc. Update to syntax in programmer's manual.
+ (arc_reg_names): Fix typo in lp_count. Add predefined aux regs.
+ (arc_suffixes): New synonyms lo,hs for cs,cc. New suffix for cache
+ bypass.
+ (arc_opcode_init_tables): New argument to indicate cpu type.
+ (insert_reg): Handle predefined aux regs.
+ (extract_reg): Likewise.
+ (lookup_register): New fn.
+ * arc-dis.c (arc_condition_codes): Deleted.
+ (print_insn_arc): Handle insns with 32 bit immediate constants better.
+ Clean up modifier handling. Handle predefined aux regs.
+end-sanitize-arc
+
+
+ * alpha-dis.c (print_insn_alpha): Handle call_pal instruction, and
+ print something for reserved opcode values, even if it won't
+ assemble again.
+
+ * mips-dis.c (_print_insn_mips): When initializing, shift right
+ and mask, to avoid sign extension problems on the Alpha.
+
+ * m68k-dis.c (print_insn_arg, case 'J'): Handle buscr and pcr
+ control registers.
+
+start-sanitize-arc
+
+ * configure.in: Add ARC support.
+ * disassemble.c: Likewise.
+ * arc-dis.c, arc-opc.c: New files.
+end-sanitize-arc
+
+
+ * sh-opc.h (mov.l gbr): Get direction right.
+ * sh-dis.c (print_insn_shx): New function.
+ (print_insn_shl, print_insn_sh): Call print_insn_shx to
+ print opcodes with right byte order.
+
+
+ * ns32k-dis.c (struct ns32k_option): Renamed from struct option,
+ to avoid conflicts with getopt.
+
+
+ * hppa-dis.c (print_insn_hppa): Read the instruction using
+ bfd_getb32, so that it works on a little endian or 64 bit host.
+ Remove unused local variable op.
+
+
+ * mips-opc.c: Use or instead of addu for pseudo-op move, since
+ addu does not work correctly if -mips3.
+
+
+ * a29k-dis.c (print_special): Add special register names defined
+ on 29030, 29040 and 29050.
+ (print_insn): Handle new operand type 'I'.
+
+
+ * Makefile.in (INSTALL): Use top level install.sh script.
+
+
+ * sparc-dis.c: Rewrite to use bitfields, rather than a union, so
+ that it works on a little endian host.
+
+
+ * configure.in: Use ${config_shell} when running config.bfd.
+
+
+ * mips-opc.c (mips_opcodes): "dabs" is only available with -mips3.
+
+
+ * a29k-dis.c (print_insn): Print the opcode.
+
+
+ * mips-opc.c (mips_opcodes): Set WR_t for sc and scd.
+
+
+ * hppa-dis.c (reg_names): Use r26-r23 for arg0-arg3.
+
+
+ * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions
+ which store a value into memory.
+
+
+ * configure.in, Makefile.in, disassemble.c: Add support for the ARM.
+ * arm-dis.c, arm-opc.h: New files.
+
+
+ * Makefile.in (ns32k-dis.o): Add dependency.
+ * ns32k-dis.c (print_insn_arg): Declare initialized local as
+ string, not as array of chars.
+
+
+ * sparc-dis.c (print_insn_sparc): Handle new operand type 'x'.
+
+ * sparc-opc.c: Added sparclite extended FP operations, and
+ versions of v9 impdep* instructions permitting specification of
+ the OPF field.
+
+
+ * i960-dis.c (reg_names): Now const.
+ (struct sparse_tabent): New type, copied from array type in mem
+ function.
+ (ctrl): Local static array ctrl_tab now const.
+ (cobr): Local static array cobr_tab now const.
+ (mem): Local variables reg1, reg2, reg3 now point to const. Local
+ static variable mem_tab no longer explicitly initialized. Changed
+ mem_init to const array of struct sparse_tabent.
+ (reg): Local static variable reg_tab no longer explicitly
+ initialized. Changed reg_init to const array of struct
+ sparse_tabent.
+ (ea): Local static array scale_tab now const.
+
+ * i960-dis.c (reg): Added i960JX instructions to reg_init table.
+ (REG_MAX): Updated.
+
+
+ * configure.bat: the disassember needs to be enabled for
+ "objdump -d" to work in djgpp.
+
+
+ * ns32k-dis.c: Deleted all code in "#ifdef GDB".
+ (invalid_float): Enabled general version, doesn't require running
+ on ns32k host. Changed to take char* argument, and test for
+ explicitly specified sizes, instead of using sizeof() on host CPU
+ types.
+ (INVALID_FLOAT): Cast first argument.
+ (opt_u, opt_U, opt_O, opt_C, opt_S, list_P532, list_M532,
+ list_P032, list_M032): Now const.
+ (optlist, list_search): Made appropriate arguments now point to
+ const.
+ (print_insn_arg): Changed static array of one-character-string
+ pointers into a static const array of characters; fixed sprintf
+ statement accordingly.
+
+
+ * opcodes/ns32k-dis.c: Semi-new file. Had apparently been dropped
+ from distribution. A ns32k-dis.c from a previous distribution has
+ been brought up to date and supports the new interface.
+
+ * disassemble.c: define ARCH_ns32k and add case bfd_arch_ns32k.
+
+ * configure.in: add bfd_ns32k_arch target support.
+
+ * Makefile.in: add ns32k-dis.o to ALL_MACHINES.
+ Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o.
+
+
+ * h8300-dis.c (bfd_h8_disassemble): Get 16bit branch
+ disassembly right.
+
+
+ * h8300-dis.c, mips-dis.c: Don't use true and false.
+
+
+ * configure.in: Change --with-targets to --enable-targets.
+
+
+ * mips-dis.c (_print_insn_mips): Build a static hash table mapping
+ opcodes to the first instruction with that opcode, to speed
+ Campbell).
+
+
+ * Makefile.in (mostlyclean): Fix typo (was mostyclean).
+
+
+ * configure.bat: update to latest makefile.in
+
+
+ * a29k-dis.c (print_insn): Print 'x' type operand in hex.
+ * h8300-dis.c (bfd_h8_disassemble): Print 16bit rels correctly.
+ * sh-dis.c (print_insn_sh): Don't recur endlessly if delay
+ slot insn is in a delay slot.
+ * z8k-opc.h: (resflg): Fix patterns.
+ * h8500-opc.h Fix CR insn patterns.
+
+
+ * ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and
+ "cmpl" before POWER versions, so that gas -many uses them.
+
+
+ * disassemble.c: New file.
+ * Makefile.in (OFILES): Add disassemble.o.
+ (disassemble.o): Provide dependencies; compile with $(ARCHDEFS).
+ * configure.in: Define ARCHDEFS in Makefile. Code taken from
+ binutils/configure.in.
+
+ * m68k-dis.c (print_insn_m68k): If F_ALIAS flag is set, skip the
+ opcode being examined.
+
+
+ * ppc-opc.c (powerpc_operands): Added RAL, RAM and RAS.
+ (insert_ral, insert_ram, insert_ras): New functions.
+ (powerpc_opcodes): Use RAL for load with update, RAM for lmw, and
+ RAS for store with update.
+
* ppc-opc.c (powerpc_opcodes): Correct fcir. From David Edelsohn
projects / binutils.git / blobdiff