+
+ PR gas/11600
+ * obj-elf.c (obj_elf_change_section): Handle SHF_EXCLUDE.
+ (obj_elf_parse_section_letters): Likewise.
+ (obj_elf_section_word): Likewise.
+
+ * config/tc-ppc.c (ppc_section_letter): Removed.
+ (ppc_section_word): Likewise.
+ * config/tc-ppc.h (ppc_section_letter): Likewise.
+ (ppc_section_word): Likewise.
+ (md_elf_section_letter): Likewise.
+ (md_elf_section_word): Likewise.
+
+ * doc/as.texinfo: Document `e' and `#exclude'.
+
+
+ * config/tc-arm.c (md_assemble): Clarify current mode in error
+ messages about unsupported instructions.
+ (UT): Delete #define.
+ (insns): Adjust cbnz, cbz appropriately.
+
+
+ * config/tc-arm.c (aeabi_set_public_attributes): Set Tag_DIV_use.
+
+
+ * config/tc-arm.c (aeabi_set_public_attributes): Set
+ Tag_ABI_HardFP_use to 1 if a single precision FPU is selected.
+
+
+ * Makefile.in: Regenerate with automake 1.11.1.
+ * aclocal.m4: Ditto.
+ * doc/Makefile.in: Ditto.
+
+
+ * po/es.po: Updated Spanish translation.
+
+
+ * read.c (cons_worker): Detect and reject unexpected string argument.
+
+
+ * write.c (fixup_segment): Revert previous delta.
+ * config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Also force the
+ generation of relocations for fixups against weak symbols.
+
+
+ * write.c (fixup_segment): Do not assume we know the section a
+ defined weak symbol is in.
+ * config/tc-arm.c (relax_adr, relax_branch, md_apply_fix): Treat
+ weak symbols as not known to be in the same section, even if they
+ are defined.
+
+
+ * config/tc-tic6x.h (tic6x_label_list): New.
+ (tic6x_segment_info_type): Keep a list of labels and a current
+ frag instead of a boolean for whether labels seen and a count of
+ instructions.
+ (tic6x_frag_info, TC_FRAG_TYPE, TC_FRAG_INIT, tic6x_frag_init,
+ md_do_align, tic6x_do_align, md_end, tic6x_end): New.
+ * config/tc-tic6x.c (tic6x_frob_label): Put label on list.
+ (tic6x_cleanup): Correct comment.
+ (tic6x_free_label_list): New.
+ (tic6x_cons_align): Free label list and update for
+ tic6x_segment_info_type changes.
+ (tic6x_do_align): New.
+ (md_assemble): Handle list of labels and saved frag for execute
+ packet. Create machine-dependent frag for new execute packet and
+ adjust labels accordingly.
+ (tic6x_adjust_section, tic6x_frag_init, tic6x_end): New.
+ (md_convert_frag, md_estimate_size_before_relax): Update comments.
+
+
+ PR gas/11535
+ * config/tc-i386-intel.c (intel_state): Add is_indirect.
+ (i386_intel_operand): Initialize intel_state.is_indirect. Check
+ intel_state.is_indirect for "call|jmp [symbol]".
+
+
+ * po/gas.pot: Updated by the Translation project.
+
+
+ * config/tc-i386.c (i386_is_register): Removed.
+ (x86_cons): Don't use i386_is_register.
+ (parse_register): Likewise.
+ * config/tc-i386-intel.c (i386_intel_simplify): Likewise.
+ (i386_intel_operand): Likewise.
+
+
+ * config/tc-i386.c (tc_x86_parse_to_dw2regnum): Don't use
+ i386_is_register.
+
+
+ * config/tc-i386.c (i386_is_register): Remove is_intel_syntax.
+ (x86_cons): Updated.
+ (parse_register): Likewise.
+ (tc_x86_parse_to_dw2regnum): Likewise.
+ * config/tc-i386-intel.c (i386_intel_simplify): Likewise.
+ (i386_intel_operand): Likewise.
+
+
+ PR gas/11509
+ * config/tc-i386-intel.c (i386_intel_simplify_register): New.
+ (i386_intel_simplify): Use i386_is_register and
+ i386_intel_simplify_register. Set X_md for O_register and
+ check X_md for O_constant.
+ (i386_intel_operand): Use i386_is_register.
+
+ * config/tc-i386.c (i386_is_register): New.
+ (x86_cons): Initialize the X_md field. Use i386_is_register.
+ (parse_register): Use i386_is_register.
+ (tc_x86_parse_to_dw2regnum): Likewise.
+
+
+ * expr.c (expr): Initialize the X_md field.
+
+
+ * config/tc-tic6x.c (OPTION_MGENERATE_REL): New.
+ (md_longopts): Add -mgenerate-rel.
+ (tic6x_generate_rela): New.
+ (md_parse_option): Handle -mgenerate-rel.
+ (md_show_usage): Add comment that -mgenerate-rel is undocumented.
+ (tic6x_init_after_args): New.
+ (md_apply_fix): Correct shift calculations for SB-relative
+ relocations.
+ (md_pcrel_from): Change to tic6x_pcrel_from_section. Do not
+ adjust addresses for relocations referencing symbols in other
+ sections.
+ (tc_gen_reloc): Adjust addend calculations for REL relocations.
+ * config/tc-tic6x.h (MD_PCREL_FROM_SECTION,
+ tic6x_pcrel_from_section, tc_init_after_args,
+ tic6x_init_after_args): New.
+
+
+ PR gas/11507
+ * macro.c (macro_expand_body): Do not treat LOCAL as a keyword in
+ altmacro mode if found inside a quoted string.
+
+
+ * config/bfin-lex.l (parse_int): Change index() to strchr().
+
+
+ PR gas/11395
+ * config/tc-hppa.c (pa_ip): Do not allow 64-bit add condition
+ matcher to accept and unconditional 32-bit add instruction.
+ (pa_build_unwind_subspace): Cope with error conditions not
+ allowing the start symbol to be set.
+
+
+ * config/tc-arm.c (arm_convert_symbolic_attribute): Add support for
+ new tag names in v2.08 of ARM ABI.
+ * doc/c-arm.texi: Document new tag names in ABI.
+
+
+ * config/tc-alpha.c: Includes vms/egps.h on EVAX.
+ (s_alpha_comm): Used new EGPS macros from egps.h
+ (RGPS__V_NO_SHIFT, EGPS__V_MASK): New local macros.
+ (s_alpha_section_word): Add comments. Use new EGPS macros.
+ Adjust for modified bfd_vms_set_section_flags function.
+
+
+ PR gas/11486
+ * config/tc-ppc.c (ppc_elf_cons): Clear frag contents.
+
+
+ * as.c (create_obj_attrs_section): Remove unused variable addr.
+ * listing.c (listing_listing): Remove unused variable message.
+ * read.c: Remove unnecessary register type qualifiers.
+ (s_mri): Only define/use old_flag variable if MRI_MODE_CHANGE is
+ defined.
+
+
+ * config/tc-avr.c (mcu_types): Add support for atmega16a, atmega168a,
+ atmega164a, atmega165a, atmega169a, atmega169pa, atmega16hva2,
+ atmega324a, atmega324pa, atmega325a, atmega3250a, atmega328,
+ atmega329a, atmega329pa, atmega3290a, atmega48a, atmega644a,
+ atmega645a, atmega645p, atmega6450a, atmega6450p, atmega649a,
+ atmega649p, atmega6490a, atmega6490p, atmega64hve, atmega88a,
+ atmega88pa, attiny461a, attiny84a, m3000.
+ Remove support for atmega8m1, atmega8c1, atmega16c1, atmega4hvd,
+ atmega8hvd, attiny327, m3000f, m3000s, m3001b.
+ * doc/c-avr.texi: Same.
+
+
+ * config/tc-arm.c (make_mapping_symbol): Handle the case
+ that multiple mapping symbols have the same value 0.
+
+
+ * configure: Regenerate.
+
+
+ * po/ru.po: New Russian translation.
+ * configure.in (ALL_LINGUAS): Add ru.
+ * configure: Regenerate.
+
+
+ PR gas/11456
+ * input-scrub.c (input_scrub_next_buffer): Use memmove instead
+ of memcpy to copy overlap memory.
+
+
+ * Makefile.am (TARGET_CPU_CFILES): Add config/tc-tic6x.c.
+ (TARGET_CPU_HFILES): Add config/tc-tic6x.h.
+ * Makefile.in: Regenerate.
+ * NEWS: Add news entry for TI C6X support.
+ * app.c (do_scrub_chars): Handle "||^" for TI C6X. Handle
+ TC_PREDICATE_START_CHAR and TC_PREDICATE_END_CHAR. Keep spaces in
+ operands if TC_KEEP_OPERAND_SPACES.
+ * configure.tgt (tic6x-*-*): New.
+ * config/tc-ia64.h (TC_PREDICATE_START_CHAR,
+ TC_PREDICATE_END_CHAR): Define.
+ * config/tc-tic6x.c, config/tc-tic6x.h: New.
+ * doc/Makefile.am (CPU_DOCS): Add c-tic6x.texi.
+ * doc/Makefile.in: Regenerate.
+ * doc/all.texi (TIC6X): Define.
+ * doc/as.texinfo: Add TI C6X documentation. Include c-tic6x.texi.
+ * doc/c-tic6x.texi: New.
+
+
+ * config/tc-i386.c (lex_got): Use STRING_COMMA_LEN on gotrel.
+
+
+ * config/tc-i386.c (i386_error): Replace oprand_size_mismatch
+ with operand_size_mismatch.
+ (operand_size_match): Updated.
+ (match_template): Likewise.
+
+
+ * config/tc-i386.c (i386_error): New.
+ (_i386_insn): Replace err_msg with error.
+ (operand_size_match): Set error instead of err_msg on failure.
+ (operand_type_match): Likewise.
+ (operand_type_register_match): Likewise.
+ (VEX_check_operands): Likewise.
+ (match_template): Likewise. Use error instead of err_msg with
+ as_bad.
+
+
+ * config/tc-arm.c (make_mapping_symbol): Hanle the case
+ that two mapping symbols have the same value.
+
+
+ * doc/c-arm.texi (.setfp): Correct example.
+
+
+ PR gas/11323
+ * config/tc-arm.c (reloc_names): New relocation names.
+ (md_apply_fix): New case for BFD_RELOC_ARM_GOT_PREL.
+ (tc_gen_reloc): New case for BFD_RELOC_ARM_GOT_PREL.
+ * doc/c-arm.texi (ARM-Relocations): Document the new relocation.
+
+
+ * dw2gencfi.c (output_cie): Consider emitting the S augmentation in all
+ cases, and not only for .eh_frame.
+
+ * dw2gencfi.c (output_cie): Make it more explicit which code paths
+ belong to .eh_frame only.
+
+
+ * config/tc-v850.c (v850_insert_operand): Handle out-of-range
+ assembler constants on 64-bit hosts.
+
+
+ * bfin-defs.h, bfin-lex.l, bfin-parse.y, tc-bfin.c, tc-bfin.h:
+ Strip trailing whitespace.
+
+
+ * doc/c-bfin.texi (-mcpu): Add bf504 and bf506.
+ * config/tc-bfin.c (bfin_cpu_type): Add BFIN_CPU_BF504 and
+ BFIN_CPU_BF506.
+ (bfin_cpus[]): Add 0.0 for bf504 and bf506.
+
+
+ * doc/as.texinfo: Add Blackfin options.
+ * doc/c-bfin.texi: Document -mfdpic, -mno-fdpic and -mnopic.
+ * config/tc-bfin.c (md_show_usage): Show usage for all
+ Blackfin specific options.
+
+
+ PR gas/11356
+ * listing.c (listing_newline): Correct backslash quote logic.
+
+
+ * config/tc-i386.h [TE_SOLARIS] (ELF_TARGET_FORMAT): Define.
+ (ELF_TARGET_FORMAT64): Define.
+
+
+ * config/tc-arm.c (arm_cpu_option_table): Add cortex-m4.
+
+
+ * config/tc-sh.c (get_specific): Move overflow checking code to avoid
+ reading uninitialized data.
+
+
+ * config/tc-score7.c (s7_frag_check): Add ATTRIBUTE_UNUSED.
+
+
+ * configure.tgt: Fix mep cpu case.
+
+
+ * config/tc-arm.c (do_t_strexd): Remove
+ operand[1] != operand[2] contraint.
+
+
+ * config/tc-arm.c (neon_select_shape): No need to match
+ the remaining operands in the shape when one operand does
+ not match.
+
+
+ * config/tc-arm.c (do_neon_ld_st_interleave): Reject bad
+ alignment.
+
+
+ * cgen.c: Whitespace fixes.
+ (weak_operand_overflow_check): Formatting fix.
+
+
+ * config/tc-i386.c (match_template): Update error messages.
+
+
+ * config/tc-i386.c (_i386_insn): Add err_msg.
+ (operand_size_match): Set err_msg on failure.
+ (operand_type_match): Likewise.
+ (operand_type_register_match): Likewise.
+ (VEX_check_operands): Likewise.
+ (match_template): Likewise. Use i.err_msg with as_bad.
+
+
+ * config/tc-mips.c (mips_fix_loongson2f, mips_fix_loongson2f_nop,
+ mips_fix_loongson2f_jump): New variables.
+ (md_longopts): Add New options -mfix-loongson2f-nop/jump,
+ -mno-fix-loongson2f-nop/jump.
+ (md_parse_option): Initialize variables via above options.
+ (options): New enums for the above options.
+ (md_begin): Initialize nop_insn from LOONGSON2F_NOP_INSN.
+ (fix_loongson2f, fix_loongson2f_nop, fix_loongson2f_jump):
+ New functions.
+ (append_insn): call fix_loongson2f().
+ (mips_handle_align): Replace the implicit nops.
+ * config/tc-mips.h (MAX_MEM_FOR_RS_ALIGN_CODE): Modified
+ for the new mips_handle_align().
+ * doc/c-mips.texi: Document the new options.
+
+
+ * config/tc-arm.c (do_rd_rm_rn): Added warning
+ for obsolete insns.
+
+
+ PR binutils/11297
+ * config/tc-avr.c (md_apply_fix): Handle BFD_RELOC_8.
+ (avr_cons_fix_new): Handle fixups of a single byte.
+
+
+ PR 9861
+ * config/tc-arm.c (CPU_DEFAULT): Do not define based upon build
+ compiler's predefines.
+
+
+ * configure.tgt: Whiltespace. Sort moxie entry.
+
+
+ * config/tc-arm.c (arm_convert_symbolic_attribute): Add Tag_DIV_use.
+ * doc/c-arm.texi: Likewise.
+
+
+ * config/tc-arm.c (asm_opcode): operands type
+ change.
+ (BAD_PC_ADDRESSING): New macro message.
+ (BAD_PC_WRITEBACK): Likewise.
+ (MIX_ARM_THUMB_OPERANDS): New macro.
+ (operand_parse_code): Added enum values.
+ (parse_operands): Added thumb/arm distinction,
+ plus new enum values handling.
+ (encode_arm_addr_mode_2): Validations enhanced.
+ (encode_arm_addr_mode_3): Likewise.
+ (do_rm_rd_rn): Likewise.
+ (encode_thumb32_addr_mode): Likewise.
+ (do_t_ldrex): Likewise.
+ (do_t_ldst): Likewise.
+ (do_t_strex): Likewise.
+ (md_assemble): Call parse_operands with
+ a new parameter.
+ (OPS_1): New macro.
+ (OPS_2): Likewise.
+ (OPS_3): Likewise.
+ (OPS_4): Likewise.
+ (OPS_5): Likewise.
+ (OPS_6): Likewise.
+ (insns): Updated insns operands.
+
+
+ * config/tc-ia64.c (enum reloc_func): Add FUNC_SLOTCOUNT_RELOC.
+ (DUMMY_RELOC_IA64_SLOTCOUNT): Added.
+ (pseudo_func): Add an entry for slotcount.
+ (md_begin): Initialize slotcount pseudo symbol.
+ (ia64_parse_name): Handle @slotcount parameter.
+ (ia64_gen_real_reloc_type): Handle slotcount.
+ (md_apply_fix): Ditto.
+ * doc/c-ia64.texi (IA-64-Relocs): Document @slotcount.
+
+
+ * config/tc-xtensa.c (istack_init): Don't call memset.
+
+
+ * config/tc-xtensa.c (cache_literal_section): Handle prefixes as
+ well as suffixes.
+
+
+ * config/tc-xtensa.c (xtensa_find_unaligned_loops): Rewrite.
+
+
+ * config/tc-i386.c (build_modrm_byte): Reformat.
+
+
+ * config/tc-i386.c: Update copyright.
+
+
+ * config/tc-i386.c (vec_imm4) New operand type.
+ (fits_in_imm4): New.
+ (VEX_check_operands): New.
+ (check_reverse): Call VEX_check_operands.
+ (build_modrm_byte): Reintroduce code for 5
+ operand insns. Fix whitespace.
+
+
+ * config/tc-ppc.c (md_show_usage): Add -mpwr4, -mpwr5, -mpwr5x,
+ -mpwr6 and -mpwr7.
+
+
+ * config/tc-xtensa.c (RELAXED_LOOP_INSN_BYTES): New.
+ (next_frag_pre_opcode_bytes): Use RELAXED_LOOP_INSN_BYTES.
+ (xtensa_mark_zcl_first_insns): Rewrite to handle corner case.
+
+
+ * config/tc-arm.c (md_pcrel_from_section): Keep base to zero for
+ non-local branches (BFD_RELOC_THUMB_PCREL_BRANCH23,
+ BFD_RELOC_THUMB_PCREL_BLX, BFD_RELOC_ARM_PCREL_BLX,
+ BFD_RELOC_ARM_PCREL_CALL)
+
+
+ * config/tc-xtensa.c (frag_format_size): Generalize logic to
+ handle more instruction sizes and fetch widths.
+ (branch_align_power): Likewise.
+ (text_align_power): Likewise.
+ (bytes_to_stretch): Likewise.
+
+
+ * config/tc-ppc.c (md_show_usage): Mention -mtitan. Don't use tabs.
+ (ppc_mach): Handle titan.
+ * doc/c-ppc.texi: Mention -mtitan.
+
+
+ * config/tc-xtensa.c (UNREACHABLE_MAX_WIDTH): Delete and
+ replace with...
+ (xtensa_fetch_width) ...this.
+
+
+ * Makefile.am (CPU_TYPES, OBJ_FORMATS, CPU_OBJ_VALID,
+ MULTI_CPU_TYPES, MULTI_CPU_OBJ_VALID): Remove.
+ * Makefile.in: Regenerate.
+
+
+ * config/tc-i386.c (cpu_arch): Change amdfam15 to bdver1.
+ (i386_align_code): Rename PROCESSOR_AMDFAM15 to PROCESSOR_BDVER1.
+ * config/tc-i386.h (processor_type): Same.
+ * doc/c-i386.texi: Change amdfam15 to bdver1.
+
+
+ PR 11136
+ * config/tc-arm.c (neon_check_type): Handle a neon_shape value of
+ NS_NULL.
+
+
+ * NEWS: Mention new feature.
+ * config/obj-coff.c (obj_coff_section): Accept digits and use
+ to override default section alignment power if specified.
+ * doc/as.texinfo (.section directive): Update documentation.
+
+
+ * config/tc-i386.c (avxscalar): New.
+ (OPTION_MAVXSCALAR): Likewise.
+ (build_vex_prefix): Select vector_length for scalar instructions
+ based on avxscalar.
+ (md_longopts): Add OPTION_MAVXSCALAR.
+ (md_parse_option): Handle OPTION_MAVXSCALAR.
+ (md_show_usage): Add -mavxscalar=.
+
+ * doc/c-i386.texi: Document -mavxscalar=.
+
* config/tc-i386.c (build_vex_prefix): Set i.vex.bytes[0] to
Include obj-format.h earlier.
-
+
* config/tc-s390.c (s390_elf_final_processing): New function.
* config/tc-s390.h (elf_tc_final_processing): New macro definition.
(s390_elf_final_processing): Added prototype.
projects / binutils.git / blobdiff