/* Common target dependent code for GDB on ARM systems.
- Copyright (C) 1988-2016 Free Software Foundation, Inc.
+ Copyright (C) 1988-2017 Free Software Foundation, Inc.
This file is part of GDB.
#include "gdbcmd.h"
#include "gdbcore.h"
#include "dis-asm.h" /* For register styles. */
+#include "disasm.h"
#include "regcache.h"
#include "reggroups.h"
#include "doublest.h"
#include "features/arm/arm-with-vfpv3.c"
#include "features/arm/arm-with-neon.c"
+#if GDB_SELF_TEST
+#include "selftest.h"
+#endif
+
static int arm_debug;
/* Macros for setting and testing a bit in a minimal symbol that marks
static const char *arm_fallback_mode_string = "auto";
static const char *arm_force_mode_string = "auto";
-/* Number of different reg name sets (options). */
-static int num_disassembly_options;
-
/* The standard register names, and all the valid aliases for them. Note
that `fp', `sp' and `pc' are not added in this alias list, because they
have been added as builtin user registers in
"f4", "f5", "f6", "f7", /* 20 21 22 23 */
"fps", "cpsr" }; /* 24 25 */
+/* Holds the current set of options to be passed to the disassembler. */
+static char *arm_disassembler_options;
+
/* Valid register name styles. */
static const char **valid_disassembly_styles;
style. */
static void set_disassembly_style_sfunc(char *, int,
struct cmd_list_element *);
-static void set_disassembly_style (void);
-
-static void convert_from_extended (const struct floatformat *, const void *,
- void *, int);
-static void convert_to_extended (const struct floatformat *, void *,
- const void *, int);
+static void show_disassembly_style_sfunc (struct ui_file *, int,
+ struct cmd_list_element *,
+ const char *);
static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
struct regcache *regcache,
implementation (this is hand-written ARM assembler in glibc). */
if (!is_thumb
- && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
+ && read_code_unsigned_integer (pc, 4, byte_order_for_code)
== 0xe3e00a0f /* mov r0, #0xffff0fff */
- && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
+ && read_code_unsigned_integer (pc + 4, 4, byte_order_for_code)
== 0xe240f01f) /* sub pc, r0, #31 */
return 1;
}
{
unsigned short insn;
- insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
+ insn = read_code_unsigned_integer (start, 2, byte_order_for_code);
if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
{
{
unsigned short inst2;
- inst2 = read_memory_unsigned_integer (start + 2, 2,
- byte_order_for_code);
+ inst2 = read_code_unsigned_integer (start + 2, 2,
+ byte_order_for_code);
if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
{
if (is_thumb)
{
unsigned short insn1
- = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
+ = read_code_unsigned_integer (pc, 2, byte_order_for_code);
if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
{
else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
{
unsigned short insn2
- = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
+ = read_code_unsigned_integer (pc + 2, 2, byte_order_for_code);
low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
insn1
- = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
+ = read_code_unsigned_integer (pc + 4, 2, byte_order_for_code);
insn2
- = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
+ = read_code_unsigned_integer (pc + 6, 2, byte_order_for_code);
/* movt Rd, #const */
if ((insn1 & 0xfbc0) == 0xf2c0)
else
{
unsigned int insn
- = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
+ = read_code_unsigned_integer (pc, 4, byte_order_for_code);
if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
{
low = EXTRACT_MOVW_MOVT_IMM_A (insn);
insn
- = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
+ = read_code_unsigned_integer (pc + 4, 4, byte_order_for_code);
if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
{
{
unsigned int destreg;
unsigned short insn
- = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
+ = read_code_unsigned_integer (pc + offset, 2, byte_order_for_code);
/* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
if ((insn & 0xf800) != 0x6800)
return pc;
destreg = bits (insn, 0, 2);
- insn = read_memory_unsigned_integer (pc + offset + 2, 2,
- byte_order_for_code);
+ insn = read_code_unsigned_integer (pc + offset + 2, 2,
+ byte_order_for_code);
/* Step 3: str Rd, [Rn, #immed], encoding T1. */
if ((insn & 0xf800) != 0x6000)
return pc;
{
unsigned int destreg;
unsigned int insn
- = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
+ = read_code_unsigned_integer (pc + offset, 4, byte_order_for_code);
/* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
if ((insn & 0x0e500000) != 0x04100000)
return pc;
destreg = bits (insn, 12, 15);
/* Step 3: str Rd, [Rn, #immed], encoding A1. */
- insn = read_memory_unsigned_integer (pc + offset + 4,
+ insn = read_code_unsigned_integer (pc + offset + 4,
4, byte_order_for_code);
if ((insn & 0x0e500000) != 0x04000000)
return pc;
current_pc += 4)
{
unsigned int insn
- = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
+ = read_code_unsigned_integer (current_pc, 4, byte_order_for_code);
if (insn == 0xe1a0c00d) /* mov ip, sp */
{
case TYPE_CODE_SET:
case TYPE_CODE_RANGE:
case TYPE_CODE_REF:
+ case TYPE_CODE_RVALUE_REF:
case TYPE_CODE_CHAR:
case TYPE_CODE_BOOL:
return TYPE_LENGTH (t);
internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
}
-/* NOTE: cagney/2001-08-20: Both convert_from_extended() and
- convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
- It is thought that this is is the floating-point register format on
- little-endian systems. */
-
-static void
-convert_from_extended (const struct floatformat *fmt, const void *ptr,
- void *dbl, int endianess)
-{
- DOUBLEST d;
-
- if (endianess == BFD_ENDIAN_BIG)
- floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
- else
- floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
- ptr, &d);
- floatformat_from_doublest (fmt, &d, dbl);
-}
-
-static void
-convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
- int endianess)
-{
- DOUBLEST d;
-
- floatformat_to_doublest (fmt, ptr, &d);
- if (endianess == BFD_ENDIAN_BIG)
- floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
- else
- floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
- &d, dbl);
-}
-
/* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
the buffer to be NEW_LEN bytes ending at ENDADDR. Return
NULL if an error occurs. BUF is freed. */
new_buf = (gdb_byte *) xmalloc (new_len);
memcpy (new_buf + bytes_to_read, buf, old_len);
xfree (buf);
- if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
+ if (target_read_code (endaddr - new_len, new_buf, bytes_to_read) != 0)
{
xfree (new_buf);
return NULL;
return bpaddr;
buf = (gdb_byte *) xmalloc (buf_len);
- if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
+ if (target_read_code (bpaddr - buf_len, buf, buf_len) != 0)
return bpaddr;
any = 0;
for (i = 0; i < buf_len; i += 2)
single-step support. We find the target of the coming instructions
and breakpoint them. */
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
arm_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct arm_get_next_pcs next_pcs_ctx;
- CORE_ADDR pc;
- int i;
- VEC (CORE_ADDR) *next_pcs = NULL;
- struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
arm_get_next_pcs_ctor (&next_pcs_ctx,
&arm_get_next_pcs_ops,
0,
regcache);
- next_pcs = arm_get_next_pcs (&next_pcs_ctx);
+ std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
- {
- pc = gdbarch_addr_bits_remove (gdbarch, pc);
- VEC_replace (CORE_ADDR, next_pcs, i, pc);
- }
-
- discard_cleanups (old_chain);
+ for (CORE_ADDR &pc_ref : next_pcs)
+ pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref);
return next_pcs;
}
unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
unsigned int rn = bits (insn, 16, 19);
- if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
+ if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0)
return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
- else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
+ else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1)
return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
else if ((op1 & 0x60) == 0x20)
return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
static int
gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
{
- struct gdbarch *gdbarch = (struct gdbarch *) info->application_data;
+ gdb_disassembler *di
+ = static_cast<gdb_disassembler *>(info->application_data);
+ struct gdbarch *gdbarch = di->arch ();
if (arm_pc_is_thumb (gdbarch, memaddr))
{
else
info->symbols = NULL;
- if (info->endian == BFD_ENDIAN_BIG)
- return print_insn_big_arm (memaddr, info);
- else
- return print_insn_little_arm (memaddr, info);
+ /* GDB is able to get bfd_mach from the exe_bfd, info->mach is
+ accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise,
+ opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger
+ the assert on the mismatch of info->mach and bfd_get_mach (exec_bfd)
+ in default_print_insn. */
+ if (exec_bfd != NULL)
+ info->flags |= USER_SPECIFIED_MACHINE_TYPE;
+
+ return default_print_insn (memaddr, info);
}
/* The following define instruction sequences that will cause ARM
if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0)
{
struct arm_get_next_pcs next_pcs_ctx;
- CORE_ADDR pc;
- int i;
- VEC (CORE_ADDR) *next_pcs = NULL;
- struct cleanup *old_chain
- = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
arm_get_next_pcs_ctor (&next_pcs_ctx,
&arm_get_next_pcs_ops,
0,
regcache);
- next_pcs = arm_get_next_pcs (&next_pcs_ctx);
+ std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
/* If MEMADDR is the next instruction of current pc, do the
software single step computation, and get the thumb mode by
the destination address. */
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
+ for (CORE_ADDR pc : next_pcs)
{
if (UNMAKE_THUMB_ADDR (pc) == *pcptr)
{
- do_cleanups (old_chain);
-
if (IS_THUMB_ADDR (pc))
{
*pcptr = MAKE_THUMB_ADDR (*pcptr);
return ARM_BP_KIND_ARM;
}
}
-
- do_cleanups (old_chain);
}
return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
bfd_byte tmpbuf[FP_REGISTER_SIZE];
regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
- convert_from_extended (floatformat_from_type (type), tmpbuf,
- valbuf, gdbarch_byte_order (gdbarch));
+ convert_typed_floating (tmpbuf, arm_ext_type (gdbarch),
+ valbuf, type);
}
break;
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_PTR
- || TYPE_CODE (type) == TYPE_CODE_REF
+ || TYPE_IS_REFERENCE (type)
|| TYPE_CODE (type) == TYPE_CODE_ENUM)
{
/* If the type is a plain integer, then the access is
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
- gdb_byte buf[MAX_REGISTER_SIZE];
+ gdb_byte buf[FP_REGISTER_SIZE];
switch (gdbarch_tdep (gdbarch)->fp_model)
{
case ARM_FLOAT_FPA:
- convert_to_extended (floatformat_from_type (type), buf, valbuf,
- gdbarch_byte_order (gdbarch));
+ convert_typed_floating (valbuf, type, buf, arm_ext_type (gdbarch));
regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
break;
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_PTR
- || TYPE_CODE (type) == TYPE_CODE_REF
+ || TYPE_IS_REFERENCE (type)
|| TYPE_CODE (type) == TYPE_CODE_ENUM)
{
if (TYPE_LENGTH (type) <= 4)
{
/* Use the name suffix to determine which register contains the
target PC. */
- static char *table[15] =
+ static const char *table[15] =
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "sl", "fp", "ip", "sp", "lr"
};
static void
set_disassembly_style_sfunc (char *args, int from_tty,
- struct cmd_list_element *c)
+ struct cmd_list_element *c)
{
- set_disassembly_style ();
+ /* Convert the short style name into the long style name (eg, reg-names-*)
+ before calling the generic set_disassembler_options() function. */
+ std::string long_name = std::string ("reg-names-") + disassembly_style;
+ set_disassembler_options (&long_name[0]);
+}
+
+static void
+show_disassembly_style_sfunc (struct ui_file *file, int from_tty,
+ struct cmd_list_element *c, const char *value)
+{
+ struct gdbarch *gdbarch = get_current_arch ();
+ char *options = get_disassembler_options (gdbarch);
+ const char *style = "";
+ int len = 0;
+ const char *opt;
+
+ FOR_EACH_DISASSEMBLER_OPTION (opt, options)
+ if (CONST_STRNEQ (opt, "reg-names-"))
+ {
+ style = &opt[strlen ("reg-names-")];
+ len = strcspn (style, ",");
+ }
+
+ fprintf_unfiltered (file, "The disassembly style is \"%.*s\".\n", len, style);
}
\f
/* Return the ARM register name corresponding to register I. */
return arm_register_names[i];
}
-static void
-set_disassembly_style (void)
-{
- int current;
-
- /* Find the style that the user wants. */
- for (current = 0; current < num_disassembly_options; current++)
- if (disassembly_style == valid_disassembly_styles[current])
- break;
- gdb_assert (current < num_disassembly_options);
-
- /* Synchronize the disassembler. */
- set_arm_regname_option (current);
-}
-
/* Test whether the coff symbol specific value corresponds to a Thumb
function. */
switch (bfd_get_flavour (info.abfd))
{
- case bfd_target_aout_flavour:
- /* Assume it's an old APCS-style ABI. */
- arm_abi = ARM_ABI_APCS;
- break;
-
case bfd_target_coff_flavour:
/* Assume it's an old APCS-style ABI. */
/* XXX WinCE? */
/* On ARM targets char defaults to unsigned. */
set_gdbarch_char_signed (gdbarch, 0);
+ /* wchar_t is unsigned under the AAPCS. */
+ if (tdep->arm_abi == ARM_ABI_AAPCS)
+ set_gdbarch_wchar_signed (gdbarch, 0);
+ else
+ set_gdbarch_wchar_signed (gdbarch, 1);
+
/* Note: for displaced stepping, this includes the breakpoint, and one word
of additional scratch space. This setting isn't used for anything beside
displaced stepping at present. */
user_reg_add (gdbarch, arm_register_aliases[i].name,
value_of_arm_user_reg, &arm_register_aliases[i].regnum);
+ set_gdbarch_disassembler_options (gdbarch, &arm_disassembler_options);
+ set_gdbarch_valid_disassembler_options (gdbarch, disassembler_options_arm ());
+
return gdbarch;
}
(unsigned long) tdep->lowest_pc);
}
-extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
+#if GDB_SELF_TEST
+namespace selftests
+{
+static void arm_record_test (void);
+}
+#endif
void
_initialize_arm_tdep (void)
{
- struct ui_file *stb;
long length;
const char *setname;
const char *setdesc;
- const char *const *regnames;
- int i;
- static std::string helptext;
+ int i, j;
char regdesc[1024], *rdptr = regdesc;
size_t rest = sizeof (regdesc);
initialize_tdesc_arm_with_vfpv3 ();
initialize_tdesc_arm_with_neon ();
- /* Get the number of possible sets of register names defined in opcodes. */
- num_disassembly_options = get_arm_regname_num_options ();
-
/* Add root prefix command for all "set arm"/"show arm" commands. */
add_prefix_cmd ("arm", no_class, set_arm_command,
_("Various ARM-specific commands."),
_("Various ARM-specific commands."),
&showarmcmdlist, "show arm ", 0, &showlist);
- /* Sync the opcode insn printer with our register viewer. */
- parse_arm_disassembler_option ("reg-names-std");
- /* Initialize the array that will be passed to
- add_setshow_enum_cmd(). */
+ arm_disassembler_options = xstrdup ("reg-names-std");
+ const disasm_options_t *disasm_options = disassembler_options_arm ();
+ int num_disassembly_styles = 0;
+ for (i = 0; disasm_options->name[i] != NULL; i++)
+ if (CONST_STRNEQ (disasm_options->name[i], "reg-names-"))
+ num_disassembly_styles++;
+
+ /* Initialize the array that will be passed to add_setshow_enum_cmd(). */
valid_disassembly_styles = XNEWVEC (const char *,
- num_disassembly_options + 1);
- for (i = 0; i < num_disassembly_options; i++)
- {
- get_arm_regnames (i, &setname, &setdesc, ®names);
- valid_disassembly_styles[i] = setname;
- length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
- rdptr += length;
- rest -= length;
- /* When we find the default names, tell the disassembler to use
- them. */
- if (!strcmp (setname, "std"))
- {
- disassembly_style = setname;
- set_arm_regname_option (i);
- }
- }
+ num_disassembly_styles + 1);
+ for (i = j = 0; disasm_options->name[i] != NULL; i++)
+ if (CONST_STRNEQ (disasm_options->name[i], "reg-names-"))
+ {
+ size_t offset = strlen ("reg-names-");
+ const char *style = disasm_options->name[i];
+ valid_disassembly_styles[j++] = &style[offset];
+ length = snprintf (rdptr, rest, "%s - %s\n", &style[offset],
+ disasm_options->description[i]);
+ rdptr += length;
+ rest -= length;
+ }
/* Mark the end of valid options. */
- valid_disassembly_styles[num_disassembly_options] = NULL;
+ valid_disassembly_styles[num_disassembly_styles] = NULL;
/* Create the help text. */
- stb = mem_fileopen ();
- fprintf_unfiltered (stb, "%s%s%s",
- _("The valid values are:\n"),
- regdesc,
- _("The default is \"std\"."));
- helptext = ui_file_as_string (stb);
- ui_file_delete (stb);
+ std::string helptext = string_printf ("%s%s%s",
+ _("The valid values are:\n"),
+ regdesc,
+ _("The default is \"std\"."));
add_setshow_enum_cmd("disassembler", no_class,
valid_disassembly_styles, &disassembly_style,
_("Show the disassembly style."),
helptext.c_str (),
set_disassembly_style_sfunc,
- NULL, /* FIXME: i18n: The disassembly style is
- \"%s\". */
+ show_disassembly_style_sfunc,
&setarmcmdlist, &showarmcmdlist);
add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
NULL,
NULL, /* FIXME: i18n: "ARM debugging is %s. */
&setdebuglist, &showdebuglist);
+
+#if GDB_SELF_TEST
+ selftests::register_test ("arm-record", selftests::arm_record_test);
+#endif
+
}
/* ARM-reversible process record data structures. */
if (bit (thumb_insn_r->arm_insn, 12))
{
/* Handle load/store register offset. */
- opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
- if (opcode2 >= 12 && opcode2 <= 15)
+ uint32_t opB = bits (thumb_insn_r->arm_insn, 9, 11);
+
+ if (opB >= 4 && opB <= 7)
{
/* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
record_buf[0] = reg_src1;
thumb_insn_r->reg_rec_count = 1;
}
- else if (opcode2 >= 8 && opcode2 <= 10)
+ else if (opB >= 0 && opB <= 2)
{
/* STR(2), STRB(2), STRH(2) . */
reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
- if (8 == opcode2)
+ if (0 == opB)
record_buf_mem[0] = 4; /* STR (2). */
- else if (10 == opcode2)
+ else if (2 == opB)
record_buf_mem[0] = 1; /* STRB (2). */
- else if (9 == opcode2)
+ else if (1 == opB)
record_buf_mem[0] = 2; /* STRH (2). */
record_buf_mem[1] = u_regval[0] + u_regval[1];
thumb_insn_r->mem_rec_count = 1;
}
else if (opcode1)
{
+ /* Special data instructions and branch and exchange */
opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
if ((3 == opcode2) && (!opcode3))
{
struct regcache *reg_cache = thumb_insn_r->regcache;
- uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
+ uint32_t opcode = 0;
uint32_t register_bits = 0, register_count = 0;
uint32_t index = 0, start_address = 0;
uint32_t record_buf[24], record_buf_mem[48];
ULONGEST u_regval = 0;
opcode = bits (thumb_insn_r->arm_insn, 11, 12);
- opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
- opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
- if (14 == opcode2)
- {
- /* POP. */
- register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
- while (register_bits)
- {
- if (register_bits & 0x00000001)
- record_buf[index++] = register_count;
- register_bits = register_bits >> 1;
- register_count++;
- }
- record_buf[index++] = ARM_PS_REGNUM;
- record_buf[index++] = ARM_SP_REGNUM;
- thumb_insn_r->reg_rec_count = index;
- }
- else if (10 == opcode2)
- {
- /* PUSH. */
- register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
- regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
- while (register_bits)
- {
- if (register_bits & 0x00000001)
- register_count++;
- register_bits = register_bits >> 1;
- }
- start_address = u_regval - \
- (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
- thumb_insn_r->mem_rec_count = register_count;
- while (register_count)
- {
- record_buf_mem[(register_count * 2) - 1] = start_address;
- record_buf_mem[(register_count * 2) - 2] = 4;
- start_address = start_address + 4;
- register_count--;
- }
- record_buf[0] = ARM_SP_REGNUM;
- thumb_insn_r->reg_rec_count = 1;
- }
- else if (0x1E == opcode1)
- {
- /* BKPT insn. */
- /* Handle enhanced software breakpoint insn, BKPT. */
- /* CPSR is changed to be executed in ARM state, disabling normal
- interrupts, entering abort mode. */
- /* According to high vector configuration PC is set. */
- /* User hits breakpoint and type reverse, in that case, we need to go back with
- previous CPSR and Program Counter. */
- record_buf[0] = ARM_PS_REGNUM;
- record_buf[1] = ARM_LR_REGNUM;
- thumb_insn_r->reg_rec_count = 2;
- /* We need to save SPSR value, which is not yet done. */
- printf_unfiltered (_("Process record does not support instruction "
- "0x%0x at address %s.\n"),
- thumb_insn_r->arm_insn,
- paddress (thumb_insn_r->gdbarch,
- thumb_insn_r->this_addr));
- return -1;
- }
- else if ((0 == opcode) || (1 == opcode))
+ if (opcode == 0 || opcode == 1)
{
- /* ADD(5), ADD(6). */
+ /* ADR and ADD (SP plus immediate) */
+
reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
record_buf[0] = reg_src1;
thumb_insn_r->reg_rec_count = 1;
}
- else if (2 == opcode)
+ else
{
- /* ADD(7), SUB(4). */
- reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
- record_buf[0] = ARM_SP_REGNUM;
- thumb_insn_r->reg_rec_count = 1;
+ /* Miscellaneous 16-bit instructions */
+ uint32_t opcode2 = bits (thumb_insn_r->arm_insn, 8, 11);
+
+ switch (opcode2)
+ {
+ case 6:
+ /* SETEND and CPS */
+ break;
+ case 0:
+ /* ADD/SUB (SP plus immediate) */
+ reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
+ record_buf[0] = ARM_SP_REGNUM;
+ thumb_insn_r->reg_rec_count = 1;
+ break;
+ case 1: /* fall through */
+ case 3: /* fall through */
+ case 9: /* fall through */
+ case 11:
+ /* CBNZ, CBZ */
+ break;
+ case 2:
+ /* SXTH, SXTB, UXTH, UXTB */
+ record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2);
+ thumb_insn_r->reg_rec_count = 1;
+ break;
+ case 4: /* fall through */
+ case 5:
+ /* PUSH. */
+ register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
+ regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
+ while (register_bits)
+ {
+ if (register_bits & 0x00000001)
+ register_count++;
+ register_bits = register_bits >> 1;
+ }
+ start_address = u_regval - \
+ (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
+ thumb_insn_r->mem_rec_count = register_count;
+ while (register_count)
+ {
+ record_buf_mem[(register_count * 2) - 1] = start_address;
+ record_buf_mem[(register_count * 2) - 2] = 4;
+ start_address = start_address + 4;
+ register_count--;
+ }
+ record_buf[0] = ARM_SP_REGNUM;
+ thumb_insn_r->reg_rec_count = 1;
+ break;
+ case 10:
+ /* REV, REV16, REVSH */
+ record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2);
+ thumb_insn_r->reg_rec_count = 1;
+ break;
+ case 12: /* fall through */
+ case 13:
+ /* POP. */
+ register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
+ while (register_bits)
+ {
+ if (register_bits & 0x00000001)
+ record_buf[index++] = register_count;
+ register_bits = register_bits >> 1;
+ register_count++;
+ }
+ record_buf[index++] = ARM_PS_REGNUM;
+ record_buf[index++] = ARM_SP_REGNUM;
+ thumb_insn_r->reg_rec_count = index;
+ break;
+ case 0xe:
+ /* BKPT insn. */
+ /* Handle enhanced software breakpoint insn, BKPT. */
+ /* CPSR is changed to be executed in ARM state, disabling normal
+ interrupts, entering abort mode. */
+ /* According to high vector configuration PC is set. */
+ /* User hits breakpoint and type reverse, in that case, we need to go back with
+ previous CPSR and Program Counter. */
+ record_buf[0] = ARM_PS_REGNUM;
+ record_buf[1] = ARM_LR_REGNUM;
+ thumb_insn_r->reg_rec_count = 2;
+ /* We need to save SPSR value, which is not yet done. */
+ printf_unfiltered (_("Process record does not support instruction "
+ "0x%0x at address %s.\n"),
+ thumb_insn_r->arm_insn,
+ paddress (thumb_insn_r->gdbarch,
+ thumb_insn_r->this_addr));
+ return -1;
+
+ case 0xf:
+ /* If-Then, and hints */
+ break;
+ default:
+ return -1;
+ };
}
REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
/* Load/store multiple instruction. */
return thumb2_record_ld_st_multiple (thumb2_insn_r);
}
- else if (!((op2 & 0x64) ^ 0x04))
+ else if ((op2 & 0x64) == 0x4)
{
/* Load/store (dual/exclusive) and table branch instruction. */
return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
}
- else if (!((op2 & 0x20) ^ 0x20))
+ else if ((op2 & 0x60) == 0x20)
{
/* Data-processing (shifted register). */
return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
return -1;
}
+namespace {
+/* Abstract memory reader. */
+
+class abstract_memory_reader
+{
+public:
+ /* Read LEN bytes of target memory at address MEMADDR, placing the
+ results in GDB's memory at BUF. Return true on success. */
+
+ virtual bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) = 0;
+};
+
+/* Instruction reader from real target. */
+
+class instruction_reader : public abstract_memory_reader
+{
+ public:
+ bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len)
+ {
+ if (target_read_memory (memaddr, buf, len))
+ return false;
+ else
+ return true;
+ }
+};
+
+} // namespace
+
/* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
and positive val on fauilure. */
static int
-extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
+extract_arm_insn (abstract_memory_reader& reader,
+ insn_decode_record *insn_record, uint32_t insn_size)
{
gdb_byte buf[insn_size];
memset (&buf[0], 0, insn_size);
- if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
+ if (!reader.read (insn_record->this_addr, buf, insn_size))
return 1;
insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
insn_size,
dispatch it. */
static int
-decode_insn (insn_decode_record *arm_record, record_type_t record_type,
- uint32_t insn_size)
+decode_insn (abstract_memory_reader &reader, insn_decode_record *arm_record,
+ record_type_t record_type, uint32_t insn_size)
{
/* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
uint32_t ret = 0; /* return value: negative:failure 0:success. */
uint32_t insn_id = 0;
- if (extract_arm_insn (arm_record, insn_size))
+ if (extract_arm_insn (reader, arm_record, insn_size))
{
if (record_debug)
{
return ret;
}
+#if GDB_SELF_TEST
+namespace selftests {
+
+/* Provide both 16-bit and 32-bit thumb instructions. */
+
+class instruction_reader_thumb : public abstract_memory_reader
+{
+public:
+ template<size_t SIZE>
+ instruction_reader_thumb (enum bfd_endian endian,
+ const uint16_t (&insns)[SIZE])
+ : m_endian (endian), m_insns (insns), m_insns_size (SIZE)
+ {}
+
+ bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len)
+ {
+ SELF_CHECK (len == 4 || len == 2);
+ SELF_CHECK (memaddr % 2 == 0);
+ SELF_CHECK ((memaddr / 2) < m_insns_size);
+
+ store_unsigned_integer (buf, 2, m_endian, m_insns[memaddr / 2]);
+ if (len == 4)
+ {
+ store_unsigned_integer (&buf[2], 2, m_endian,
+ m_insns[memaddr / 2 + 1]);
+ }
+ return true;
+ }
+
+private:
+ enum bfd_endian m_endian;
+ const uint16_t *m_insns;
+ size_t m_insns_size;
+};
+
+static void
+arm_record_test (void)
+{
+ struct gdbarch_info info;
+ gdbarch_info_init (&info);
+ info.bfd_arch_info = bfd_scan_arch ("arm");
+
+ struct gdbarch *gdbarch = gdbarch_find_by_info (info);
+
+ SELF_CHECK (gdbarch != NULL);
+
+ /* 16-bit Thumb instructions. */
+ {
+ insn_decode_record arm_record;
+
+ memset (&arm_record, 0, sizeof (insn_decode_record));
+ arm_record.gdbarch = gdbarch;
+
+ static const uint16_t insns[] = {
+ /* db b2 uxtb r3, r3 */
+ 0xb2db,
+ /* cd 58 ldr r5, [r1, r3] */
+ 0x58cd,
+ };
+
+ enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch);
+ instruction_reader_thumb reader (endian, insns);
+ int ret = decode_insn (reader, &arm_record, THUMB_RECORD,
+ THUMB_INSN_SIZE_BYTES);
+
+ SELF_CHECK (ret == 0);
+ SELF_CHECK (arm_record.mem_rec_count == 0);
+ SELF_CHECK (arm_record.reg_rec_count == 1);
+ SELF_CHECK (arm_record.arm_regs[0] == 3);
+
+ arm_record.this_addr += 2;
+ ret = decode_insn (reader, &arm_record, THUMB_RECORD,
+ THUMB_INSN_SIZE_BYTES);
+
+ SELF_CHECK (ret == 0);
+ SELF_CHECK (arm_record.mem_rec_count == 0);
+ SELF_CHECK (arm_record.reg_rec_count == 1);
+ SELF_CHECK (arm_record.arm_regs[0] == 5);
+ }
+
+ /* 32-bit Thumb-2 instructions. */
+ {
+ insn_decode_record arm_record;
+
+ memset (&arm_record, 0, sizeof (insn_decode_record));
+ arm_record.gdbarch = gdbarch;
+
+ static const uint16_t insns[] = {
+ /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */
+ 0xee1d, 0x7f70,
+ };
+
+ enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch);
+ instruction_reader_thumb reader (endian, insns);
+ int ret = decode_insn (reader, &arm_record, THUMB2_RECORD,
+ THUMB2_INSN_SIZE_BYTES);
+
+ SELF_CHECK (ret == 0);
+ SELF_CHECK (arm_record.mem_rec_count == 0);
+ SELF_CHECK (arm_record.reg_rec_count == 1);
+ SELF_CHECK (arm_record.arm_regs[0] == 7);
+ }
+}
+} // namespace selftests
+#endif /* GDB_SELF_TEST */
/* Cleans up local record registers and memory allocations. */
paddress (gdbarch, arm_record.this_addr));
}
- if (extract_arm_insn (&arm_record, 2))
+ instruction_reader reader;
+ if (extract_arm_insn (reader, &arm_record, 2))
{
if (record_debug)
{
if (!(u_regval & t_bit))
{
/* We are decoding arm insn. */
- ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
+ ret = decode_insn (reader, &arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
}
else
{
/* is it thumb2 insn? */
if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
{
- ret = decode_insn (&arm_record, THUMB2_RECORD,
+ ret = decode_insn (reader, &arm_record, THUMB2_RECORD,
THUMB2_INSN_SIZE_BYTES);
}
else
{
/* We are decoding thumb insn. */
- ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
+ ret = decode_insn (reader, &arm_record, THUMB_RECORD,
+ THUMB_INSN_SIZE_BYTES);
}
}
projects / binutils.git / blobdiff