/* tc-i960.c - All the i80960-specific stuff
- Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 1999
+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
+ 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
This file is part of GAS.
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
-/* See comment on md_parse_option for 80960-specific invocation options. */
+/* See comment on md_parse_option for 80960-specific invocation options. */
/* There are 4 different lengths of (potentially) symbol-based displacements
in the 80960 instruction set, each of which could require address fix-ups
a relocation directive. */
#include <stdio.h>
-#include <ctype.h>
#include "as.h"
+#include "safe-ctype.h"
#include "obstack.h"
#include "opcode/i960.h"
#endif
/* Local i80960 routines. */
-
-static void brcnt_emit (); /* Emit branch-prediction instrumentation code */
-static char *brlab_next (); /* Return next branch local label */
-void brtab_emit (); /* Emit br-predict instrumentation table */
-static void cobr_fmt (); /* Generate COBR instruction */
-static void ctrl_fmt (); /* Generate CTRL instruction */
-static char *emit (); /* Emit (internally) binary */
-static int get_args (); /* Break arguments out of comma-separated list */
-static void get_cdisp (); /* Handle COBR or CTRL displacement */
-static char *get_ispec (); /* Find index specification string */
-static int get_regnum (); /* Translate text to register number */
-static int i_scan (); /* Lexical scan of instruction source */
-static void mem_fmt (); /* Generate MEMA or MEMB instruction */
-static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */
-static void parse_expr (); /* Parse an expression */
-static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */
-static void parse_memop (); /* Parse a memory operand */
-static void parse_po (); /* Parse machine-dependent pseudo-op */
-static void parse_regop (); /* Parse a register operand */
-static void reg_fmt (); /* Generate a REG format instruction */
-void reloc_callj (); /* Relocate a 'callj' instruction */
-static void relax_cobr (); /* "De-optimize" cobr into compare/branch */
-static void s_leafproc (); /* Process '.leafproc' pseudo-op */
-static void s_sysproc (); /* Process '.sysproc' pseudo-op */
-static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */
-static void syntax (); /* Give syntax error */
-static int targ_has_sfr (); /* Target chip supports spec-func register? */
-static int targ_has_iclass (); /* Target chip supports instruction set? */
+struct memS;
+struct regop;
+
+/* Emit branch-prediction instrumentation code */
+static void brcnt_emit PARAMS ((void));
+/* Return next branch local label */
+static char *brlab_next PARAMS ((void));
+/* Generate COBR instruction */
+static void cobr_fmt PARAMS ((char *[], long, struct i960_opcode *));
+/* Generate CTRL instruction */
+static void ctrl_fmt PARAMS ((char *, long, int));
+/* Emit (internally) binary */
+static char *emit PARAMS ((long));
+/* Break arguments out of comma-separated list */
+static int get_args PARAMS ((char *, char *[]));
+/* Handle COBR or CTRL displacement */
+static void get_cdisp PARAMS ((char *, char *, long, int, int, int));
+/* Find index specification string */
+static char *get_ispec PARAMS ((char *));
+/* Translate text to register number */
+static int get_regnum PARAMS ((char *));
+/* Lexical scan of instruction source */
+static int i_scan PARAMS ((char *, char *[]));
+/* Generate MEMA or MEMB instruction */
+static void mem_fmt PARAMS ((char *[], struct i960_opcode *, int));
+/* Convert MEMA instruction to MEMB format */
+static void mema_to_memb PARAMS ((char *));
+/* Parse an expression */
+static void parse_expr PARAMS ((char *, expressionS *));
+/* Parse and replace a 'ldconst' pseudo-op */
+static int parse_ldconst PARAMS ((char *[]));
+/* Parse a memory operand */
+static void parse_memop PARAMS ((struct memS *, char *, int));
+/* Parse machine-dependent pseudo-op */
+static void parse_po PARAMS ((int));
+/* Parse a register operand */
+static void parse_regop PARAMS ((struct regop *, char *, char));
+/* Generate a REG format instruction */
+static void reg_fmt PARAMS ((char *[], struct i960_opcode *));
+/* "De-optimize" cobr into compare/branch */
+static void relax_cobr PARAMS ((fragS *));
+/* Process '.leafproc' pseudo-op */
+static void s_leafproc PARAMS ((int, char *[]));
+/* Process '.sysproc' pseudo-op */
+static void s_sysproc PARAMS ((int, char *[]));
+/* Will a 'shlo' substiture for a 'ldconst'? */
+static int shift_ok PARAMS ((int));
+/* Give syntax error */
+static void syntax PARAMS ((void));
+/* Target chip supports spec-func register? */
+static int targ_has_sfr PARAMS ((int));
+/* Target chip supports instruction set? */
+static int targ_has_iclass PARAMS ((int));
/* See md_parse_option() for meanings of these options */
static char norelax; /* True if -norelax switch seen */
#NO_APP at the beginning of its output.
*/
-/* Also note that comments started like this one will always work. */
+/* Also note that comments started like this one will always work. */
-const char line_comment_chars[1];
+const char line_comment_chars[] = "#";
-const char line_separator_chars[1];
+const char line_separator_chars[] = ";";
/* Chars that can be used to separate mant from exp in floating point nums */
const char EXP_CHARS[] = "eE";
*/
const char FLT_CHARS[] = "fFdDtT";
-
/* Table used by base assembler to relax addresses based on varying length
instructions. The fields are:
1) most positive reach of this state,
#define adds(e) e.X_add_symbol
#define offs(e) e.X_add_number
-
/* Branch-prediction bits for CTRL/COBR format opcodes */
#define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
#define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
#define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
-
/* Some instruction opcodes that we need explicitly */
#define BE 0x12000000
#define BG 0x11000000
#define CALLS 0x66003800
#define RET 0x0a000000
-
-/* These masks are used to build up a set of MEMB mode bits. */
+/* These masks are used to build up a set of MEMB mode bits. */
#define A_BIT 0x0400
#define I_BIT 0x0800
#define MEMB_BIT 0x1000
#define D_BIT 0x2000
-
/* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
used). */
#define MEMA_ABASE 0x2000
/* Info from which a MEMA or MEMB format instruction can be generated */
-typedef struct
+typedef struct memS
{
/* (First) 32 bits of instruction */
long opcode;
displacement should be determined. */
char *e;
}
-
memS;
-
/* The two pieces of info we need to generate a register operand */
struct regop
{
int n; /* Register number or literal value */
};
-
/* Number and assembler mnemonic for all registers that can appear in
operands. */
static const struct
{ NULL, 0 }, /* END OF LIST */
};
-
/* Hash tables */
static struct hash_control *op_hash; /* Opcode mnemonics */
static struct hash_control *reg_hash; /* Register name hash table */
static struct hash_control *areg_hash; /* Abase register hash table */
-
/* Architecture for which we are assembling */
#define ARCH_ANY 0 /* Default: no architecture checking done */
#define ARCH_KA 1
* instructions.
*/
-
/* BRANCH-PREDICTION INSTRUMENTATION
The following supports generation of branch-prediction instrumentation
const char *bp_error_msg = _("branch prediction invalid on this opcode");
-
/* Parse instruction into opcode and operands */
memset (args, '\0', sizeof (args));
n_ops = i_scan (textP, args);
}
}
-
-
/* Check for branch-prediction suffix on opcode mnemonic, strip it off */
n = strlen (args[0]) - 1;
branch_predict = 0;
md_chars_to_number: convert from target byte order to host byte order.
*************************************************************************** */
-int
+static int md_chars_to_number PARAMS ((unsigned char *, int));
+
+static int
md_chars_to_number (val, n)
unsigned char *val; /* Value in target byte order */
int n; /* Number of bytes in the input */
return retval;
}
-
#define MAX_LITTLENUMS 6
-#define LNUM_SIZE sizeof(LITTLENUM_TYPE)
+#define LNUM_SIZE sizeof (LITTLENUM_TYPE)
/*****************************************************************************
md_atof: convert ascii to floating point
LITTLENUM_TYPE *wordP;
int prec;
char *t;
- char *atof_ieee ();
switch (type)
{
return 0;
}
-
/*****************************************************************************
md_number_to_imm
*************************************************************************** */
-void
-md_number_to_imm (buf, val, n)
- char *buf;
- long val;
- int n;
-{
- md_number_to_chars (buf, val, n);
-}
-
+static void md_number_to_imm PARAMS ((char *, long, int));
-/*****************************************************************************
- md_number_to_disp
-
- *************************************************************************** */
-void
-md_number_to_disp (buf, val, n)
+static void
+md_number_to_imm (buf, val, n)
char *buf;
long val;
int n;
previously-generated instruction.
*************************************************************************** */
-void
+static void md_number_to_field PARAMS ((char *, long, bit_fixS *));
+
+static void
md_number_to_field (instrP, val, bfixP)
char *instrP; /* Pointer to instruction to be fixed */
long val; /* Address fixup value */
A table of all such "Labels" is also generated.
-
-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
Select the 80960 architecture. Instructions or features not
supported by the selected architecture cause fatal errors.
****************************************************************************/
-CONST char *md_shortopts = "A:b";
+const char *md_shortopts = "A:b";
struct option md_longopts[] =
{
#define OPTION_LINKRELAX (OPTION_MD_BASE)
#ifndef BFD_ASSEMBLER
void
md_convert_frag (headers, seg, fragP)
- object_headers *headers;
- segT seg;
+ object_headers *headers ATTRIBUTE_UNUSED;
+ segT seg ATTRIBUTE_UNUSED;
fragS *fragP;
#else
void
md_convert_frag (abfd, sec, fragP)
- bfd *abfd;
- segT sec;
+ bfd *abfd ATTRIBUTE_UNUSED;
+ segT sec ATTRIBUTE_UNUSED;
fragS *fragP;
#endif
{
relax_cobr (fragP);
return 4;
}
- return 0;
+
+ return md_relax_table[fragP->fr_subtype].rlx_length;
} /* md_estimate_size_before_relax() */
#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
does do the reordering (Ian Taylor 28 Aug 92).
*************************************************************************** */
+static void md_ri_to_chars PARAMS ((char *, struct relocation_info *));
static void
md_ri_to_chars (where, ri)
cobr_fmt: generate a COBR-format instruction
*************************************************************************** */
-static
-void
+static void
cobr_fmt (arg, opcode, oP)
/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
char *arg[];
instr |= (regop.n << 14) | regop.special;
}
-
if (n < 3)
{
emit (instr);
}
} /* cobr_fmt() */
-
/*****************************************************************************
ctrl_fmt: generate a CTRL-format instruction
*************************************************************************** */
-static
-void
+static void
ctrl_fmt (targP, opcode, num_ops)
char *targP; /* Pointer to text of lone operand (if any) */
long opcode; /* Template of instruction */
* how often the branch is taken
*/
-
if (num_ops == 0)
{
emit (opcode); /* Output opcode */
}
-
/*****************************************************************************
emit: output instruction binary
Return pointer to where it was placed.
*************************************************************************** */
-static
-char *
+static char *
emit (instr)
long instr; /* Word to be output, host byte order */
{
return toP;
}
-
/*****************************************************************************
get_args: break individual arguments out of comma-separated list
{
if (*p == ' '
- && (! isalnum ((unsigned char) p[1])
- || ! isalnum ((unsigned char) p[-1])))
+ && (! ISALNUM (p[1])
+ || ! ISALNUM (p[-1])))
{
p++;
return n;
}
-
/*****************************************************************************
get_cdisp: handle displacement for a COBR or CTRL instruction.
address displacement is greater than 13 bits.
****************************************************************************/
-static
-void
+static void
get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
/* displacement as specified in source instruction */
char *dispP;
}
}
-
/*****************************************************************************
get_ispec: parse a memory operand for an index specification
square brackets, and return a pointer to it. Otherwise, return NULL.
*************************************************************************** */
-static
-char *
+static char *
get_ispec (textP)
/* Pointer to memory operand from source instruction, no white space. */
char *textP;
associated register number (or -1 if not found).
*************************************************************************** */
-static
-int
+static int
get_regnum (regname)
char *regname; /* Suspected register name */
{
return (rP == NULL) ? -1 : *rP;
}
-
/*****************************************************************************
i_scan: perform lexical scan of ascii assembler instruction.
*************************************************************************** */
static int
i_scan (iP, args)
- /* Pointer to ascii instruction; MUCKED BY US. */
+ /* Pointer to ascii instruction; MUCKED BY US. */
register char *iP;
/* Output arg: pointers to opcode and operands placed here. MUST
ACCOMMODATE 4 ENTRIES. */
return (get_args (iP, args));
} /* i_scan() */
-
/*****************************************************************************
mem_fmt: generate a MEMA- or MEMB-format instruction
memset (&instr, '\0', sizeof (memS));
instr.opcode = oP->opcode;
- /* Process operands. */
+ /* Process operands. */
for (i = 1; i <= oP->num_ops; i++)
{
opdesc = oP->operand[i - 1];
}
} /* memfmt() */
-
/*****************************************************************************
mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
md_number_to_chars (opcodeP, opcode, 4);
} /* mema_to_memb() */
-
/*****************************************************************************
parse_expr: parse an expression
}
}
-
/*****************************************************************************
parse_ldcont:
Parse and replace a 'ldconst' pseudo-instruction with an appropriate
Returns the new number of arguments, or -1 on failure.
*************************************************************************** */
-static
-int
+static int
parse_ldconst (arg)
char *arg[]; /* See above */
{
static char buf2[5]; /* Literal for second operand */
expressionS e; /* Parsed expression */
-
arg[3] = NULL; /* So we can tell at the end if it got used or not */
parse_expr (arg[1], &e);
the displacement.
*************************************************************************** */
-static
-void
+static void
parse_memop (memP, argP, optype)
memS *memP; /* Where to put the results */
char *argP; /* Text of the operand to be parsed */
16 /* MEM16 */
};
-
iprel_flag = mode = 0;
/* Any index present? */
up the rest of the input line, breaks out the individual arguments,
and dispatches them to the correct handler.
*************************************************************************** */
-static
-void
+static void
parse_po (po_num)
int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
{
extern char is_end_of_line[];
- /* Advance input pointer to end of line. */
+ /* Advance input pointer to end of line. */
p = input_line_pointer;
while (!is_end_of_line[(unsigned char) *input_line_pointer])
{
In case of illegal operand, issue a message and return some valid
information so instruction processing can continue.
*************************************************************************** */
-static
-void
+static void
parse_regop (regopP, optext, opdesc)
struct regop *regopP; /* Where to put description of register operand */
char *optext; /* Text of operand */
struct regop regop; /* Description of register operand */
int n_ops; /* Number of operands */
-
instr = oP->opcode;
n_ops = oP->num_ops;
emit (instr);
}
-
/*****************************************************************************
relax_cobr:
Replace cobr instruction in a code fragment with equivalent branch and
{ CMPI, BO }, /* 0x3f - cmpibo */
};
-static
-void
+static void
relax_cobr (fragP)
register fragS *fragP; /* fragP->fr_opcode is assumed to point to
* the cobr instruction, which comes at the
frag_wane (fragP);
}
-
/*****************************************************************************
reloc_callj: Relocate a 'callj' instruction
passed fixup structure.
*************************************************************************** */
-void
+int
reloc_callj (fixP)
/* Relocation that can be done at assembly time */
fixS *fixP;
if (!fixP->fx_tcbit)
{
/* This wasn't a callj instruction in the first place */
- return;
+ return 0;
}
where = fixP->fx_frag->fr_literal + fixP->fx_where;
/* Nothing else needs to be done for this instruction. Make
sure 'md_number_to_field()' will perform a no-op. */
fixP->fx_bit_fixP = (bit_fixS *) 1;
-
}
else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
{
} /* switch on proc type */
/* else Symbol is neither a sysproc nor a leafproc */
+ return 0;
}
-
/*****************************************************************************
s_leafproc: process .leafproc pseudo-op
return;
} /* Check number of arguments */
- /* Find or create symbol for 'call' entry point. */
+ /* Find or create symbol for 'call' entry point. */
callP = symbol_find_or_make (args[1]);
if (TC_S_IS_CALLNAME (callP))
} /* if only one arg, or the args are the same */
}
-
/*
s_sysproc: process .sysproc pseudo-op
return;
} /* bad arg count */
- /* Parse "entry_num" argument and check it for validity. */
+ /* Parse "entry_num" argument and check it for validity. */
parse_expr (args[2], &exp);
if (exp.X_op != O_constant
|| (offs (exp) < 0)
TC_S_FORCE_TO_SYSPROC (symP);
}
-
/*****************************************************************************
shift_ok:
Determine if a "shlo" instruction can be used to implement a "ldconst".
Caller calculates X by shifting original constant right 'shift' places.
*************************************************************************** */
-static
-int
+static int
shift_ok (n)
int n; /* The constant of interest */
{
return shift;
}
-
/* syntax: issue syntax error */
static void
as_bad (_("syntax error"));
} /* syntax() */
-
/* targ_has_sfr:
Return TRUE iff the target architecture supports the specified
special-function register (sfr). */
-static
-int
+static int
targ_has_sfr (n)
int n; /* Number (0-31) of sfr */
{
}
}
-
/* targ_has_iclass:
Return TRUE iff the target architecture supports the indicated
class of instructions. */
-static
-int
+static int
targ_has_iclass (ic)
/* Instruction class; one of:
I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2
static void
s_endian (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
char *name;
char c;
demand_empty_rest_of_line ();
}
-/* We have no need to default values of symbols. */
+/* We have no need to default values of symbols. */
-/* ARGSUSED */
symbolS *
md_undefined_symbol (name)
- char *name;
+ char *name ATTRIBUTE_UNUSED;
{
return 0;
}
/* Exactly what point is a PC-relative offset relative TO?
On the i960, they're relative to the address of the instruction,
- which we have set up as the address of the fixup too. */
+ which we have set up as the address of the fixup too. */
long
md_pcrel_from (fixP)
fixS *fixP;
return fixP->fx_where + fixP->fx_frag->fr_address;
}
-#ifdef BFD_ASSEMBLER
-int
-md_apply_fix (fixP, valp)
- fixS *fixP;
- valueT *valp;
-#else
void
-md_apply_fix (fixP, val)
+md_apply_fix3 (fixP, valP, seg)
fixS *fixP;
- long val;
-#endif
+ valueT *valP;
+ segT seg ATTRIBUTE_UNUSED;
{
-#ifdef BFD_ASSEMBLER
- long val = *valp;
-#endif
+ long val = *valP;
char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
if (!fixP->fx_bit_fixP)
fixP->fx_addnumber = val;
#endif
- md_number_to_imm (place, val, fixP->fx_size, fixP);
+ md_number_to_imm (place, val, fixP->fx_size);
+ }
+ else if ((int) fixP->fx_bit_fixP == 13
+ && fixP->fx_addsy != NULL
+ && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
+ {
+ /* This is a COBR instruction. They have only a
+ 13-bit displacement and are only to be used
+ for local branches: flag as error, don't generate
+ relocation. */
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("can't use COBR format with external label"));
+ fixP->fx_addsy = NULL;
}
else
md_number_to_field (place, val, fixP->fx_bit_fixP);
-#ifdef BFD_ASSEMBLER
- return 0;
-#endif
+ if (fixP->fx_addsy == NULL)
+ fixP->fx_done = 1;
}
#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
ri.r_index = S_GET_TYPE (symbolP);
}
- /* Output the relocation information in machine-dependent form. */
+ /* Output the relocation information in machine-dependent form. */
md_ri_to_chars (where, &ri);
}
void
tc_crawl_symbol_chain (headers)
- object_headers *headers;
+ object_headers *headers ATTRIBUTE_UNUSED;
{
symbolS *symbolP;
void
tc_set_bal_of_call (callP, balP)
- symbolS *callP;
- symbolS *balP;
+ symbolS *callP ATTRIBUTE_UNUSED;
+ symbolS *balP ATTRIBUTE_UNUSED;
{
know (TC_S_IS_CALLNAME (callP));
know (TC_S_IS_BALNAME (balP));
symbolS *
tc_get_bal_of_call (callP)
- symbolS *callP;
+ symbolS *callP ATTRIBUTE_UNUSED;
{
symbolS *retval;
return retval;
} /* _tc_get_bal_of_call() */
+#ifdef OBJ_COFF
void
tc_coff_symbol_emit_hook (symbolP)
- symbolS *symbolP;
+ symbolS *symbolP ATTRIBUTE_UNUSED;
{
if (TC_S_IS_CALLNAME (symbolP))
{
-#ifdef OBJ_COFF
symbolS *balP = tc_get_bal_of_call (symbolP);
#if 0
S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
/* fix up the bal symbol */
S_SET_STORAGE_CLASS (balP, C_LABEL);
-#endif /* OBJ_COFF */
} /* only on calls */
}
+#endif /* OBJ_COFF */
void
i960_handle_align (fragp)
- fragS *fragp;
+ fragS *fragp ATTRIBUTE_UNUSED;
{
if (!linkrelax)
return;
}
int
-i960_validate_fix (fixP, this_segment_type, add_symbolPP)
+i960_validate_fix (fixP, this_segment_type)
fixS *fixP;
- segT this_segment_type;
- symbolS **add_symbolPP;
+ segT this_segment_type ATTRIBUTE_UNUSED;
{
-#define add_symbolP (*add_symbolPP)
- if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP))
+ if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy))
{
/* Relocation should be done via the associated 'bal'
- entry point symbol. */
+ entry point symbol. */
- if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP)))
+ if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy)))
{
- as_bad (_("No 'bal' entry point for leafproc %s"),
- S_GET_NAME (add_symbolP));
- return 1;
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("No 'bal' entry point for leafproc %s"),
+ S_GET_NAME (fixP->fx_addsy));
+ return 0;
}
- fixP->fx_addsy = add_symbolP = tc_get_bal_of_call (add_symbolP);
+ fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy);
}
-#if 0
- /* Still have to work out other conditions for these tests. */
- {
- if (fixP->fx_tcbit)
- {
- as_bad (_("callj to difference of two symbols"));
- return 1;
- }
- reloc_callj (fixP);
- if ((int) fixP->fx_bit_fixP == 13)
- {
- /* This is a COBR instruction. They have only a 13-bit
- displacement and are only to be used for local branches:
- flag as error, don't generate relocation. */
- as_bad (_("can't use COBR format with external label"));
- fixP->fx_addsy = NULL; /* No relocations please. */
- return 1;
- }
- }
-#endif
-#undef add_symbolP
- return 0;
+
+ return 1;
}
#ifdef BFD_ASSEMBLER
/* From cgen.c: */
+static short tc_bfd_fix2rtype PARAMS ((fixS *));
+
static short
tc_bfd_fix2rtype (fixP)
fixS *fixP;
arelent *
tc_gen_reloc (section, fixP)
- asection *section;
+ asection *section ATTRIBUTE_UNUSED;
fixS *fixP;
{
arelent * reloc;
projects / binutils.git / blobdiff