/* Integer registers 0 thru 31 are handled explicitly by
mips_register_name(). Processor specific registers 32 and above
- are listed in the followign tables. */
+ are listed in the following tables. */
enum
{ NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
}
}
-/* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
-
-static CORE_ADDR
-mips_read_sp (void)
-{
- return read_signed_register (MIPS_SP_REGNUM);
-}
/* Should the upper word of 64-bit addresses be zeroed? */
enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
NUM_REGS + mips_regnum (gdbarch)->pc);
}
+static CORE_ADDR
+mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+ return frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM);
+}
+
/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
dummy frame. The frame ID's base needs to match the TOS value
saved by save_dummy_frame_tos(), and the PC match the dummy frame's
It works by decoding the current instruction and predicting where a
branch will go. This isnt hard because all the data is available.
The MIPS32 and MIPS16 variants are quite different */
-CORE_ADDR
+static CORE_ADDR
mips_next_pc (CORE_ADDR pc)
{
if (pc & 0x01)
/* mips_software_single_step() is called just before we want to resume
the inferior, if we want to single-step it but there is no hardware
or kernel single-step support (MIPS on GNU/Linux for example). We find
- the target of the coming instruction and breakpoint it.
-
- single_step is also called just after the inferior stops. If we had
- set up a simulated single-step, we undo our damage. */
+ the target of the coming instruction and breakpoint it. */
-void
-mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
+int
+mips_software_single_step (struct regcache *regcache)
{
CORE_ADDR pc, next_pc;
- if (insert_breakpoints_p)
- {
- pc = read_register (mips_regnum (current_gdbarch)->pc);
- next_pc = mips_next_pc (pc);
+ pc = read_register (mips_regnum (current_gdbarch)->pc);
+ next_pc = mips_next_pc (pc);
- insert_single_step_breakpoint (next_pc);
- }
- else
- remove_single_step_breakpoints ();
+ insert_single_step_breakpoint (next_pc);
+ return 1;
}
/* Test whether the PC points to the return instruction at the
if (fp_register_arg_p (typecode, arg_type)
&& float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
{
- if (register_size (gdbarch, float_argreg) < 8 && len == 8)
+ /* EABI32 will pass doubles in consecutive registers, even on
+ 64-bit cores. At one time, we used to check the size of
+ `float_argreg' to determine whether or not to pass doubles
+ in consecutive registers, but this is not sufficient for
+ making the ABI determination. */
+ if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
{
int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
unsigned long regval;
register are only written to memory. */
while (len > 0)
{
- /* Rememer if the argument was written to the stack. */
+ /* Remember if the argument was written to the stack. */
int stack_used_p = 0;
int partial_len = (len < mips_abi_regsize (gdbarch)
? len : mips_abi_regsize (gdbarch));
cagney/2001-07-23: gdb/179: Also, GCC, when
outputting LE O32 with sizeof (struct) <
- mips_abi_regsize(), generates a left shift as
- part of storing the argument in a register a
- register (the left shift isn't generated when
+ mips_abi_regsize(), generates a left shift
+ as part of storing the argument in a register
+ (the left shift isn't generated when
sizeof (struct) >= mips_abi_regsize()). Since
it is quite possible that this is GCC
contradicting the LE/O32 ABI, GDB has not been
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
&& partial_len < mips_abi_regsize (gdbarch)
- && (typecode == TYPE_CODE_STRUCT ||
- typecode == TYPE_CODE_UNION))
- regval <<= ((mips_abi_regsize (gdbarch) - partial_len) *
- TARGET_CHAR_BIT);
+ && (typecode == TYPE_CODE_STRUCT
+ || typecode == TYPE_CODE_UNION))
+ regval <<= ((mips_abi_regsize (gdbarch) - partial_len)
+ * TARGET_CHAR_BIT);
if (mips_debug)
fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
/* Now make space on the stack for the args. */
for (argnum = 0; argnum < nargs; argnum++)
- len += align_up (TYPE_LENGTH (value_type (args[argnum])),
- mips_stack_argsize (gdbarch));
+ {
+ struct type *arg_type = check_typedef (value_type (args[argnum]));
+ int arglen = TYPE_LENGTH (arg_type);
+
+ /* Align to double-word if necessary. */
+ if (mips_type_needs_double_align (arg_type))
+ len = align_up (len, mips_stack_argsize (gdbarch) * 2);
+ /* Allocate space on the stack. */
+ len += align_up (arglen, mips_stack_argsize (gdbarch));
+ }
sp -= align_up (len, 16);
if (mips_debug)
up before the check to see if there are any FP registers
left. O32/O64 targets also pass the FP in the integer
registers so also round up normal registers. */
- if (mips_abi_regsize (gdbarch) < 8
- && fp_register_arg_p (typecode, arg_type))
+ if (fp_register_arg_p (typecode, arg_type))
{
if ((float_argreg & 1))
float_argreg++;
fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
argreg, phex (regval, len));
write_register (argreg, regval);
- argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2;
+ argreg += 2;
}
/* Reserve space for the FP register. */
stack_offset += align_up (len, mips_stack_argsize (gdbarch));
&& (len % mips_abi_regsize (gdbarch) != 0));
/* Structures should be aligned to eight bytes (even arg registers)
on MIPS_ABI_O32, if their first member has double precision. */
- if (mips_abi_regsize (gdbarch) < 8
- && mips_type_needs_double_align (arg_type))
+ if (mips_type_needs_double_align (arg_type))
{
if ((argreg & 1))
- argreg++;
+ {
+ argreg++;
+ stack_offset += mips_abi_regsize (gdbarch);
+ }
}
- /* Note: Floating-point values that didn't fit into an FP
- register are only written to memory. */
while (len > 0)
{
/* Remember if the argument was written to the stack. */
/* Write this portion of the argument to the stack. */
if (argreg > MIPS_LAST_ARG_REGNUM
- || odd_sized_struct
- || fp_register_arg_p (typecode, arg_type))
+ || odd_sized_struct)
{
/* Should shorter than int integer values be
promoted to int before being stored? */
}
/* Note!!! This is NOT an else clause. Odd sized
- structs may go thru BOTH paths. Floating point
- arguments will not. */
+ structs may go thru BOTH paths. */
/* Write this portion of the argument to a general
purpose register. */
- if (argreg <= MIPS_LAST_ARG_REGNUM
- && !fp_register_arg_p (typecode, arg_type))
+ if (argreg <= MIPS_LAST_ARG_REGNUM)
{
LONGEST regval = extract_signed_integer (val, partial_len);
/* Value may need to be sign extended, because
cagney/2001-07-23: gdb/179: Also, GCC, when
outputting LE O32 with sizeof (struct) <
- mips_abi_regsize(), generates a left shift as
- part of storing the argument in a register a
- register (the left shift isn't generated when
+ mips_abi_regsize(), generates a left shift
+ as part of storing the argument in a register
+ (the left shift isn't generated when
sizeof (struct) >= mips_abi_regsize()). Since
it is quite possible that this is GCC
contradicting the LE/O32 ABI, GDB has not been
identified as such and GDB gets tweaked
accordingly. */
- if (mips_abi_regsize (gdbarch) < 8
- && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
&& partial_len < mips_abi_regsize (gdbarch)
- && (typecode == TYPE_CODE_STRUCT ||
- typecode == TYPE_CODE_UNION))
- regval <<= ((mips_abi_regsize (gdbarch) - partial_len) *
- TARGET_CHAR_BIT);
+ && (typecode == TYPE_CODE_STRUCT
+ || typecode == TYPE_CODE_UNION))
+ regval <<= ((mips_abi_regsize (gdbarch) - partial_len)
+ * TARGET_CHAR_BIT);
if (mips_debug)
fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
/* Now make space on the stack for the args. */
for (argnum = 0; argnum < nargs; argnum++)
- len += align_up (TYPE_LENGTH (value_type (args[argnum])),
- mips_stack_argsize (gdbarch));
+ {
+ struct type *arg_type = check_typedef (value_type (args[argnum]));
+ int arglen = TYPE_LENGTH (arg_type);
+
+ /* Allocate space on the stack. */
+ len += align_up (arglen, mips_stack_argsize (gdbarch));
+ }
sp -= align_up (len, 16);
if (mips_debug)
val = value_contents (arg);
- /* 32-bit ABIs always start floating point arguments in an
- even-numbered floating point register. Round the FP register
- up before the check to see if there are any FP registers
- left. O32/O64 targets also pass the FP in the integer
- registers so also round up normal registers. */
- if (mips_abi_regsize (gdbarch) < 8
- && fp_register_arg_p (typecode, arg_type))
- {
- if ((float_argreg & 1))
- float_argreg++;
- }
-
/* Floating point arguments passed in registers have to be
treated specially. On 32-bit architectures, doubles
are passed in register pairs; the even register gets
if (fp_register_arg_p (typecode, arg_type)
&& float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
{
- if (mips_abi_regsize (gdbarch) < 8 && len == 8)
- {
- int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
- unsigned long regval;
-
- /* Write the low word of the double to the even register(s). */
- regval = extract_unsigned_integer (val + low_offset, 4);
- if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg, phex (regval, 4));
- write_register (float_argreg++, regval);
- if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
- argreg, phex (regval, 4));
- write_register (argreg++, regval);
-
- /* Write the high word of the double to the odd register(s). */
- regval = extract_unsigned_integer (val + 4 - low_offset, 4);
- if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg, phex (regval, 4));
- write_register (float_argreg++, regval);
-
- if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
- argreg, phex (regval, 4));
- write_register (argreg++, regval);
- }
- else
- {
- /* This is a floating point value that fits entirely
- in a single register. */
- /* On 32 bit ABI's the float_argreg is further adjusted
- above to ensure that it is even register aligned. */
- LONGEST regval = extract_unsigned_integer (val, len);
- if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg, phex (regval, len));
- write_register (float_argreg++, regval);
- /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
- registers for each argument. The below is (my
- guess) to ensure that the corresponding integer
- register has reserved the same space. */
- if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
- argreg, phex (regval, len));
- write_register (argreg, regval);
- argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2;
- }
+ LONGEST regval = extract_unsigned_integer (val, len);
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg, phex (regval, len));
+ write_register (float_argreg++, regval);
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
+ argreg, phex (regval, len));
+ write_register (argreg, regval);
+ argreg++;
/* Reserve space for the FP register. */
stack_offset += align_up (len, mips_stack_argsize (gdbarch));
}
both places. */
int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
&& (len % mips_abi_regsize (gdbarch) != 0));
- /* Structures should be aligned to eight bytes (even arg registers)
- on MIPS_ABI_O32, if their first member has double precision. */
- if (mips_abi_regsize (gdbarch) < 8
- && mips_type_needs_double_align (arg_type))
- {
- if ((argreg & 1))
- argreg++;
- }
- /* Note: Floating-point values that didn't fit into an FP
- register are only written to memory. */
while (len > 0)
{
/* Remember if the argument was written to the stack. */
/* Write this portion of the argument to the stack. */
if (argreg > MIPS_LAST_ARG_REGNUM
- || odd_sized_struct
- || fp_register_arg_p (typecode, arg_type))
+ || odd_sized_struct)
{
/* Should shorter than int integer values be
promoted to int before being stored? */
}
/* Note!!! This is NOT an else clause. Odd sized
- structs may go thru BOTH paths. Floating point
- arguments will not. */
+ structs may go thru BOTH paths. */
/* Write this portion of the argument to a general
purpose register. */
- if (argreg <= MIPS_LAST_ARG_REGNUM
- && !fp_register_arg_p (typecode, arg_type))
+ if (argreg <= MIPS_LAST_ARG_REGNUM)
{
LONGEST regval = extract_signed_integer (val, partial_len);
/* Value may need to be sign extended, because
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
&& partial_len < mips_abi_regsize (gdbarch)
- && (typecode == TYPE_CODE_STRUCT ||
- typecode == TYPE_CODE_UNION))
- regval <<= ((mips_abi_regsize (gdbarch) - partial_len) *
- TARGET_CHAR_BIT);
+ && (typecode == TYPE_CODE_STRUCT
+ || typecode == TYPE_CODE_UNION))
+ regval <<= ((mips_abi_regsize (gdbarch) - partial_len)
+ * TARGET_CHAR_BIT);
if (mips_debug)
fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
set_gdbarch_read_pc (gdbarch, mips_read_pc);
set_gdbarch_write_pc (gdbarch, mips_write_pc);
- set_gdbarch_read_sp (gdbarch, mips_read_sp);
/* Add/remove bits from an address. The MIPS needs be careful to
ensure that all 32 bit addresses are sign extended to 64 bits. */
/* Unwind the frame. */
set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
+ set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id);
/* Map debug register numbers onto internal register numbers. */
projects / binutils.git / blobdiff