+
+ * config/tc-m68k.c (m68k_ip): Reject pc-relative addresses for the
+ 'p' operand specifier.
+
+
+ * config/tc-m68k.c (HAVE_LONG_BRANCH): New macro, returns true for
+ m68k family cpus which support long branch addressing modes.
+ (m68k_ip, md_convert_frag_1, md_estimate_size_before_relax,
+ md_create_long_jump): Use it.
+
+
+ * config/tc-mips.c (md_begin): Don't set SEC_ALLOC or SEC_LOAD for
+ the .reginfo or .MIPS.options section if configured for an
+ embedded target.
+
+ * config/tc-mips.c (md_begin): Don't set interlocks for
+ mips_4650.
+
+
+ * read.c (read_a_source_file): Make sure the symbol ends with
+ whitespace before checking whether the next character is '='.
+
+
+ * config/tc-i386.c (sco_id): Moved from here...
+ * config/obj-elf.c (sco_id): ...to here. Adding the identifier
+ really is an SCO ELF specific thing, not just a SCO x86 specific
+ thing.
+
+start-sanitize-tic80
+
+ * configure.in (tic80-*-*): Don't require 'coff'.
+ * configure: Regenerate.
+
+end-sanitize-tic80
+
+ * read.c (emit_expr): Check for overflow of a negative value
+ correctly.
+ * write.c (fixup_segment): Likewise.
+ * config/obj-coff.c (fixup_segment): Likewise.
+
+ * config/tc-m68k.c (struct label_line): Define.
+ (labels, current_label): New static variables.
+ (md_assemble): Mark current_label as text, and clear it.
+ (m68k_frob_label): New function.
+ (m68k_flush_pending_output): New function.
+ (m68k_frob_symbol): New function.
+ * config/tc-m68k.h (tc_frob_label): Define.
+ (md_flush_pending_output): Define.
+ (tc_frob_symbol): Don't warn, just call m68k_frob_symbol.
+ (tc_frob_coff_symbol): Likewise.
+
+ * read.c (read_a_source_file): When defining a macro in MRI mode,
+ don't add the symbol to the symbol table.
+
+
+ * config/tc-mn10300.c (tc_gen_reloc): Handle sym1-sym2 fixups
+ here since fixup_segment doesn't (linkrelax is set).
+ * config/tc-mn10200.c (tc_gen_reloc): Likewise.
+
+
+ * config/tc-mn10200.c (md_assemble): Tweak fx_offset for pc-relative
+ relocs.
+
+
+ * config/tc-hppa.c (struct hppa_fix_struct): Tweak fx_r_field's type
+ to avoid warnings with the native HP compiler.
+ (fix_new_hppa): Similarly for the r_type argument.
+ (pa_build_unwind_subspace, hppa_elf_mark_end_of_function): Enclose
+ in an #if OBJ_ELF to keep gcc -Wall quiet.
+ (md_apply_fix): Always initialize "result".
+
+ * config/tc-mn10200.c (md_assemble): Generate relocations.
+
+
+ * config/tc-m68k.c (s_even): Adjust the alignment of the current
+ section.
+
+
+ * config/obj-elf.c (elf_file_symbol): When using ECOFF debugging,
+ pass on the new file hook.
+
+ * config/tc-alpha.c (alpha_fix_adjustable): Not quite the same as
+ !alpha_force_relocation, as local LITERALs can be adjusted to be
+ relative to the section.
+
+
+ * config/obj-coff.c (yank_symbols): If tc_frob_coff_symbol is
+ defined, call it.
+ * config/tc-m68k.h (tc_frob_symbol): Check whether text label is
+ aligned to odd boundary.
+ (tc_frob_coff_symbol): Define.
+
+ * doc/as.texinfo (Set): Change parenthesized @xref to @pxref.
+
+ * macro.c (macro_expand_body): In MRI mode, just copy a single &.
+
+ * config/tc-m68k.c (m68k_ip): Call frag_grow before adding a
+
+ * config/tc-m68k.c (m68k_ip): Accept 'B' as a size for an
+ immediate value.
+ (md_assemble): If the size is 'B', set fx_signed.
+ (md_apply_fix_2): Use fx_signed when checking for overflow.
+
+ * write.h (struct fix): Add fx_signed field.
+ * write.c (fix_new_internal): Initialize fx_no_overflow and
+ fx_signed fields.
+ (fixup_segment): Use fx_signed when checking for overflow.
+ * config/obj-coff.c (fixup_segment): Check fx_no_overflow and
+ fx_signed when checking for overflow.
+
+
+ * NOTES, NOTES.config: Removed. These are rarely, if ever,
+ updated, and all the useful information is in doc/internals.texi.
+
+ * read.c (read_a_source_file): Check for conditional operators
+ before doing an MRI pending alignment.
+ * config/tc-m68k.h (m68k_conditional_pseudoop): Declare.
+ (tc_conditional_pseudop): Define.
+ * config/tc-m68k.c (m68k_conditional_pseudop): New function.
+ * doc/internals.texi (CPU backend): Describe
+ tc_conditional_pseudoop.
+
+ * config/tc-m68k.c (m68k_rel32_from_cmdline): New static
+ variable.
+ (md_begin): Check m68k_rel32_from_cmdline before setting
+ m68k_rel32.
+ (m68k_mri_mode_change): Likewise.
+ (md_longopts): Add --disp-size-default-16 and
+ --disp-size-default-32.
+ (md_parse_option): Handle new options.
+ (md_show_usage): Mention new options.
+ * doc/c-m68k.texi (M68K-Opts): Document new options.
+
+ * config/tc-m68k.c (m68k_index_width_default): New static
+ variable.
+ (m68k_ip): Use m68k_index_width_default to set the size of a base
+ register whose size was not given.
+ (md_longopts): Add --base-size-default-16 and
+ --base-size-default-32.
+ (md_parse_option): Handle new options.
+ (md_show_usage): Mention new options.
+ * doc/c-m68k.texi (M68K-Opts): Document new options.
+
+ * doc/c-mips.texi: Mention ISA level 4, and the -mips16 option.
+
+ * configure.in: Recognize mips-*-linux* target.
+ * configure: Rebuild.
+
+ * config/tc-mips.c (load_register): Rewrite 64 bit handling to
+ work if valueT is only 32 bits.
+
+ * config/tc-mips.c: Throughout, check target_big_endian rather
+ than byte_order.
+ (byte_order): Remove.
+ (mips_init_after_args): Remove.
+ * config/tc-mips.h (LITTLE_ENDIAN, BIG_ENDIAN): Don't define.
+ (mips_init_after_args): Don't declare.
+ (tc_init_after_args): Don't define.
+
+ * config/tc-mips.h (tc_frob_after_relocs): Define if
+ OBJ_MAYBE_ELF.
+ (mips_elf_final_processing): Likewise.
+ (ELF_TC_SPECIAL_SECTIONS): Likewise.
+
+start-sanitize-v850
+
+ * config/tc-v850.c (md_assemble): If this is sst.{h,w} or
+ sld.{h,w} and the operand is relocatable, adjust the adend by
+ shifting it right one bit.
+
+end-sanitize-v850
+
+ * read.c (read_a_source_file): Check mri_pending_align after
+ checking for a macro. From Ronald F. Guilmette
+
+ * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE.
+
+ * config/tc-sparc.c (md_apply_fix3): Rename from md_apply_fix, and
+ add segment argument. If OBJ_ELF, treat a relocation against a
+ symbol in a linkonce section like a relocation against an external
+ symbol.
+ * config/tc-sparc.h (MD_APPLY_FIX3): Define.
+
+
+ * config/tc-mips.c (mips16_macro): Add case for M_ABS.
+
+
+ * NOTES.config (Implementation): as.h #define's "GAS" not "gas",
+ includes config.h instead of host.h, tc.h instead of tp.h, and
+ targ-env.h instead of target-environment.h.
+ Also, obj-format.h includes targ-cpu.h instead of
+ target-processor.h.
+start-sanitize-tic80
+ * configure.in (case ${generic_target}): Add tic80-*-coff entry.
+ * configure: Rebuild with autoconf.
+ * config/obj-coff.h (coff/tic80.h): Include if TC_TIC80 defined.
+ (TARGET_FORMAT): Define to "coff-tic80".
+ * config/tc-tic80.c: New file for TIc80 support.
+ * config/tc-tic80.h: New file for TIc80 support.
+end-sanitize-tic80
+
+
+ * doc/as.texinfo (M): Mention explicitly that -M changes macro
+ handling.
+
+
+ * write.c (adjust_reloc_syms): If the fixup symbol has been
+ equated to an undefined symbol, convert the fixup to being against
+ the target symbol. Remove obsolete code handling a special case
+ for i386 PIC.
+
+
+ * mpw-make.sed: Use NewFolderRecursive for installation.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c (do_assemble): Correct previous bug fix.
+
+
+ * config/tc-d10v.c (md_assemble): Fix bug which caused
+ second instruction in a line to be case sensitize. PR11312
+
+end-sanitize-d10v
+
+ * config/tc-mn10200.c (mn10200_insert_operand): Don't
+ range check operands with MN10200_OPERAND_NOCHECK set.
+ (check_operand): Likewise.
+
+
+ * config/tc-mips.c: Undo part of last Friday's alignment changes.
+ (md_begin): Always align the text section to a four byte
+ boundary.
+ (append_insn): Remove call to record_align.
+
+ * config/tc-mips.c (insn_label): Remove.
+ (struct insn_label_list): Define.
+ (insn_labels, free_insn_labels): New static variables.
+ (mips_clear_insn_labels): New static function.
+ (append_insn): Mark all mips16 text labels, and make them odd.
+ Handle all labels after emitting a nop, not just one. Call
+ mips_clear_insn_labels rather than just clearing insn_label.
+ (mips_emit_delays): Add insns parameter, and use it to decide
+ whether to mark mips16 labels. Handle all labels, not just one.
+ Force mips16 labels to be odd. Change all callers.
+ (mips16_immed): Don't check for an odd branch target.
+ (md_apply_fix): Don't check mips16 mode for a branch reloc.
+ (mips16_extended_frag): Ignore the low bit in a branch target.
+ (md_convert_frag): Likewise.
+ (mips_no_prev_insn): Call mips_clear_insn_labels rather than just
+ clearing insn_label.
+ (mips_align, mips_flush_pending_output, s_cons): Likewise.
+ (s_float_cons, s_gpword): Likewise.
+ (s_align): Use insn_labels rather than insn_label.
+ (s_cons, s_float_cons, s_gpword): Likewise.
+ (mips_frob_file_after_relocs): New function.
+ (mips_define_label): Rewrite to add to insn_labels list.
+ * config/tc-mips.h (tc_frob_file_after_relocs): Define.
+ * ecoff.c (ecoff_build_symbols): If the size of a function comes
+ out odd, increment it.
+
+ * config/tc-mips.c (append_insn): Only update prev_insn when not
+ reordering if place is NULL.
+
+ * config/tc-mips.c (mips16_ip): Check for a missing expression
+ when using the register indirect addressing mode.
+
+
+ * config/tc-mn10200.c (mn10200_insert_operand): Don't
+ check 24bit operands for overflow.
+ (check_operand): Likewise.
+
+
+ * doc/as.texinfo (Section): Document how to use the .section
+ pseudo-op for COFF and ELF.
+
+
+ * write.c (adjust_reloc_syms): Fix linkonce check for ELF.
+
+
+ * config/tc-mips.c (prev_insn_reloc_type): New static variable.
+ (RELAX_MIPS16_ENCODE): Add dslot and jal_dslot arguments, and
+ store them. Adjust other RELAX_MIPS16 macros.
+ (RELAX_MIPS16_DSLOT): Define.
+ (RELAX_MIPS16_JAL_DSLOT): Define.
+ (append_insn): Pass new arguments to RELAX_MIPS16_ENCODE. Correct
+ handling of whether previous instruction has a fixup. Set
+ prev_insn_reloc_type.
+ (mips_no_prev_insn): Clear prev_insn_reloc_type.
+ (mips16_extended_frag): Use the right base address for a PC
+ relative add or load.
+ (md_convert_frag): Likewise. If a PC relative add or load is
+ used, record the alignment for the section.
+
+
+ * write.c (adjust_reloc_syms): Don't reduce a reloc against a
+ linkonce section into a reloc against the section symbol.
+
+ * config/tc-mips.c (mips16_macro): Remove nop instructions after
+ branch instructions.
+
+ * config/tc-mips.c (md_begin): If configured for an embedded ELF
+ system, don't set the section alignment to 2**4.
+ (s_change_sec): Likewise.
+ (append_insn): Call record_alignment for the section.
+ (md_section_align): Don't align the section size for an embedded
+ ELF system.
+
+
+ * write.c (adjust_reloc_syms): Make sure that symbols are
+ resolved; expression symbols may have been skipped.
+ * config/obj-coff.c (fixup_segment): Likewise.
+
+
+ * config/tc-ppc.c (ppc_elf_suffix): Move @plt to
+ BFD_RELOC_24_PLT_PCREL relocation.
+ (md_apply_fix3): Support BFD_RELOC_24_PLT_PCREL.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c (write_2_short): Remove code that called
+ parallel_ok() when the programmer specified parallel instructions.
+
+end-sanitize-d10v
+
+ * config/tc-mn10300.c (md_assemble): Update to handle endianness
+ issues correctly.
+
+ * config/tc-mn10200.c (md_assemble): Opcode 0x0 is valid!
+ * config/tc-mn10300.c (md_assemble): Likewise.
+
+
+ * config/tc-mips.c (append_insn): Make sure there is enough room
+ in a frag after a mips16 instruction to switch it with a jump
+ instruction.
+
+ * config/tc-mips.c (mips16_extended_frag): Give an error for an
+ attempt to use a non absolute symbol in an extending frag.
+
+
+ * config/tc-mn10200.c: Flesh out assembler support for MN10200.
+ * config/tc-mn10200.h: Likewise.
+
+
+ * app.c (do_scrub_chars): At the end of a C comment, pass space to
+ UNGET rather than PUT. Set old_state before setting state to -2.
+
+ * config/tc-mips.c (mips16_extended_frag): Avoid an infinite loop
+ when extending because the value is exactly maxtiny + 1.
+
+ * config/tc-mips.c (RELAX_MIPS16_ENCODE): Add small and ext
+ arguments, and store them. Adjust other RELAX_MIPS16 macros.
+ (RELAX_MIPS16_USER_SMALL): Define.
+ (RELAX_MIPS16_USER_EXT): Define.
+ (mips16_small, mips16_ext): New static variables.
+ (append_insn): Pass mips16_small and mips16_ext to
+ RELAX_MIPS16_ENCODE.
+ (mips16_ip): Set mips16_small and mips16_ext.
+ (mips16_immed): Don't check mips16_autoextend.
+ (mips16_extended_frag): Check USER_SMALL and USER_EXT.
+
+ * write.c (write_relocs): Print an error for an out of range
+ fixup, rather than calling abort.
+
+ * as.c (main): Unlink the output file if there are errors while
+ generating the fixups.
+
+
+ * config/tc-mips.c (mips16_extended_frag): Don't call
+ S_GET_VALUE.
+ (md_convert_frag): Call resolve_symbol_value before calling
+ S_GET_VALUE, and don't add in the frag address.
+
+ * config/tc-mips.c (mips16_immed): Add file and line parameters,
+ and use them when reporting errors. Change all callers.
+
+
+ * config/tc-mn10300.c: Fix various gcc -Wall warnings.
+ Remove '$' prefixing for registers.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c (md_assemble): Check to see if prev_seg
+ is initialized before using it.
+ (d10v_cleanup): No longer uses its argument, so make it void.
+
+ * config/tc-d10v.h (d10v_cleanup): Change prototype.
+
+end-sanitize-d10v
+
+ * write.c (fixup_segment): Don't discard the symbol for a PC
+ relative fixup to an absolute symbol.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c (md_assemble, d10v_cleanup): Fix bug
+ with multiple sections.
+
+end-sanitize-d10v
+
+ * config/tc-mips.c (md_longopts): Rename mips-16 to mips16, and
+ no-mips-16 to no-mips16.
+ (s_mipsset): Accept .set mips16 and .set nomips16.
+
+
+ * config/tc-ppc.c (ppc_elf_suffix): Take expressionS pointer
+ argument, and check for +/- constant following the suffix, folding
+ it into the expression.
+ (ppc_elf_cons): Change ppc_elf_suffix calls.
+ (md_assemble): Ditto.
+ (shlib): Replace boolean mrelocatable with enumeration shlib.
+ (md_parse_option): Discriminate between PIC style shared libraries
+ and -mrelocatable.
+ (ppc_elf_validate_fix): Don't report warnings for PIC style shared
+ libraries.
+
+
+ * config/tc-ppc.h ({tc,ppc}_comment_chars): Define, so that we can
+ change the comment characters.
+
+ * config/tc-ppc.c (comment_chars): Delete in favor of
+ tc_comment_chars.
+ (ppc_{eabi,solaris}_comment_chars): Eabi and Solaris versions of
+ comment chars.
+ (ppc_comment_chars): Select appropriate comment chars by default.
+ (msolaris): New flag for -m{,no-}solaris.
+ (md_parse_option): Recognize -K pic. Add support for
+ -m{,no-}solaris.
+ (md_show_usage): Update.
+ (md_begin): Do not set ELF flags if Solaris.
+ (ppc_elf_suffix): @local sets R_PPC_LOCAL24PC relocation.
+ (md_apply_fix3): Add support for R_PPC_LOCAL24PC.
+
+
+ * as.c (main): Correct handling of flag_always_generate_output.
+
+
+ * config/tc-mn10300.c (tc_gen_reloc): Get the addend from
+ fx_offset, not fx_addnumber.
+
+ * config/tc-mn10300.h (tc_fix_adjustable): Don't do any
+ reloc adjustments.
+
+
+ * config/tc-i386.c: Correct misspelling: balenced to balanced.
+
+
+ * config/tc-mips.c (md_section_align): Check for an alignment of
+ 4, not an alignment of 16. Corrects August 7 patch.
+
+
+ * configure, conf.in: Rebuild with autoconf 2.12.
+
+ * config/tc-ppc.c (ppc_elf_lcomm): Don't give an error if no
+ alignment is specified.
+
+ Add support for mips16 (16 bit MIPS implementation):
+ * config/tc-mips.c: Extensive additions for mips16 support, not
+ listed here.
+ (RELAX_OLD, RELAX_NEW): Use only 7 bits each.
+ (insn_uses_reg): Change last parameter to an enum.
+ * config/tc-mips.h (LOCAL_LABELS_DOLLAR): Define as 0.
+ (md_relax_frag): Define as mips_relax_frag.
+ (mips_relax_frag): Declare.
+ (struct mips_cl_insn): Add use_extend and extend fields.
+ (tc_fix_adjustable): Define.
+ * config/obj-elf.h (S_GET_OTHER): Define.
+ (S_SET_OTHER): Define.
+
+
+ * config/tc-m68k.c (m68k_ip): Implement cases for new <, >, m, n,
+ o and p operand specifiers.
+
+
+ * write.c: Delete "ifndef md_relax_frag" around is_dnrange.
+ (relax_segment, case rs_org): Move code inside braces. Move locals
+ target,after inside too.
+ (relax_segment, case rs_machine_dependent): Guts moved to ...
+ (relax_frag): New function.
+ Call md_prepare_relax_scan if defined.
+ * config/tc-m68k.h (md_prepare_relax_scan): Renamed from
+ M68K_AIM_KLUDGE.
+
+
+ * config/tc-mn10300.c (address_registers): Use '$' as register
+ prefix instead of '%'.
+ (data_registers, other_registers, md_assemble): Likewise.
+
+ * config/tc-mn10300.c (address_registers): Use '%' prefix for regs.
+ (data_registers, other_registers, md_assemble): Likewise.
+
+ * config/tc-mn10300.c (md_assemble): Correctly determine the
+ correct location and type for each relocation.
+ (md_pcrel_from): Simplify.
+
+
+ * config/tc-sh.c (md_convert_frag): Improve warning when branch is
+ converted into branch around branch.
+
+
+ * config/tc-mn10300.h (DIFF_EXPR_OK): Don't define this.
+ (tc_fix_adjustable): Don't adjust relocs against weak symbols or
+ pc-relative relocs.
+ * config/tc-mn10300.c (md_begin): Set linkrelax.
+ (md_assemble): Create fixups as needed.
+ (md_apply_fix3): Gut. It shouldn't ever get called anymore.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c (parallel_ok): When automatically converting
+ serial ops to parallel, do not consider a branch as the first
+ instruction.
+
+end-sanitize-d10v
+
+ * config/tc-mn10300.c (md_assemble): Handle MN10300_OPERAND_REG_LIST.
+
+
+ * config/tc-mn10300.c (mn10300_insert_operand): Provide prototype
+ via PARAMS.
+ (check_operand): Likewise.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c (parallel_ok): Branch and link instructions
+ modify r13.
+ (write_2_short): Call parallel_ok to check whether two short
+ instructions the user requested execute in parallel, can be
+ executed that way.
+
+
+ * config/tc-d10v.c (write_2_short): Fix bug that wouldn't
+ allow a branch and link in parallel with an exe instruction.
+
+
+ * doc/c-d10v.texi: Add info on @word modifier.
+
+end-sanitize-d10v
+
+ * config/tc-mn10300.c (mn10300_insert_operand): MN10300_OPERAND_SPLIT
+ operands are assumed to be 32bits. Use "bits" field to hold the
+ number of bits in the main instruction word for MN10300_OPERAND_SPLIT.
+ (mn10300_check_operand): MN10300_OPERAND_SPLIT operands are assumed
+ to be 32bits.
+
+ * config/tc-mn10300.c (mn10300_insert_operand): Shift low part
+ of a MN10300_OPERAND_SPLIT operand by operand->shift.
+
+ * config/tc-mn10300.c (mn10300_insert_operand): Handle
+ MN10300_OPERAND_SPLIT.
+
+
+ * config/tc-mn10300.c (md_assemble): Insert operands into
+ the extension part of the instruction if necessary.
+ (mn10300_insert_operand): Accept pointer to extension word
+ argument. Make insn a pointer argument too. Return type
+ is now void. All callers changed.
+
+
+ * config/tc-mn10300.c (mn10300_insert_operand): Handle
+ repeated register operands.
+
+
+ * doc/as.texinfo: Added section on reporting bugs.
+
+ * config/tc-alpha.c: Change uses of void * to PTR. Change the
+ alpha_macro emit field to expect a const argument, and change the
+ arg field to be const. Fix some spacing to follow the GNU
+ standard.
+
+
+ * config/tc-alpha.c (md_parse_option): Add knowledge of 21164pc
+ (pca56) and 21264 (ev6) cpus.
+ (md_apply_fix): Private relocation types are now negative.
+ (alpha_force_relocation): Likewise.
+ (tc_gen_reloc): Likewise.
+ (emit_insn): Likewise.
+ (emit_ldXu): Do the right thing when the hardware can do byte insns.
+ (emit_stX): Likewise.
+ (emit_sextX): Likewise.
+
+
+ * config/obj-coff.c (do_relocs_for): Call resolve_symbol_value on
+ a symbol found in a reloc.
+
+ * symbols.c (resolve_symbol_value): Improve the error message if
+ an undefined symbol is used in an expression.
+
+
+ * doc/internals.texi: Rewrite, and add a lot of documentation.
+ * doc/Makefile.in (internals.info): New target.
+
+start-sanitize-v850
+
+ * config/tc-v850.h (tc_fix_adjustable): Don't adjust relocs
+ against weak symbols.
+
+
+ * config/tc-v850.c (md_assemble): Don't lose for relaxable
+ addresses like .+6.
+
+ * config/tc-v850.c (md_convert_frag): Make sure we insert the
+ fixup at the right address within the frag.
+
+ * config/tc-v850.c (md_convert_frag): Don't set fragP->fr_fix
+ to an absolute value, instead increment it as needed.
+
+ * config/tc-v850.h (TC_GENERIC_RELAX_TABLE): Define.
+ * config/tc-v850.c: Fix some indention problems.
+ (md_relax_table): Define for D9->D99 branch displacement
+ relaxing.
+ (md_convert_frag): Do something useful instead of aborting.
+ (md_estimate_size_before_relax): Likewise.
+ (md_assemble): Note if the matching instruction has a relaxable
+ operand. If it does, allocate frag with frag_var and don't
+ do any fixups.
+
+end-sanitize-v850
+start-sanitize-d10v
+
+ * config/tc-d10v.h (md_cleanup): New function. This is needed to
+ write out any buffered instructions when a ".end" is found.
+
+end-sanitize-d10v
+
+ * read.c (read_a_source_file): New hook md_cleanup().
+
+
+ * write.c (fix_new_exp): Use make_expr_symbol to build an
+ expression symbol for a complex fixup.
+
+start-sanitize-v850
+
+ * config/tc-v850.c (v850_reloc_prefix): Several disgusting
+ hacks to improve parsing of complex hi, lo, zda, etc
+ expressions.
+ (md_assemble): Don't demand and eat a trailing ')' after finding
+ a v850 relocation prefix. Sign extend the constant in a
+ BFD_RELOC_LO16 expression. Do eat a trailing ')' after a complete
+ operand.
+ (parse_cons_expression_v850): Don't eat a trailing ')' after
+ finding a v850 relocation prefix.
+
+ * config/tc-v850.h (TC_PARSE_CONS_EXPRESSION): Define.
+ (TC_CONS_FIX_NEW): Likewise.
+ * config/tc-v850.c (parse_cons_expression_v850): New function.
+ (cons_fix_new_v850): Likewise.
+
+ * config/tc-v850.h (tc_fix_adjustable): Don't adjust TDA relocs.
+
+end-sanitize-v850
+
+ * config/tc-ppc.c (md_apply_fix3): Give a better warning message
+ for an unknown relocation type.
+
+start-sanitize-v850
+
+ * config/tc-v850.c (md_pseudo_table): Add .word; allocates
+ 4 bytes of space.
+
+
+ * config/tc-v850.c (md_assemble): Handle TDAOFF relocs
+ differently for movea & sst/sld insns.
+
+end-sanitize-v850
+start-sanitize-d10v
+
+ * config/tc-d10v.c (parallel_ok): Don't allow illegal combinations
+ of instructions.
+
+end-sanitize-d10v
+
+ * obj.h (struct format_ops): Add frob_file_after_relocs field.
+ * config/obj-multi.h (obj_frob_file_after_relocs): Define.
+ * config/obj-ecoff.c (ecoff_format_ops): Initialize new
+ frob_file_after_relocs field.
+ * config/obj-elf.c (elf_format_ops): Likewise.
+ * config/tc-mips.c: Undefine obj_frob_file_after_relocs before
+ including obj-elf.h.
+
+
+ * config/tc-mips.c (cons_fix_new_mips): Only treat 8 byte reloc
+ specially if not ELF.
+ (md_apply_fix): Handle BFD_RELOC_64.
+ (tc_gen_reloc): Handle BFD_RELOC_64.
+
+ * config/tc-i386.c (md_apply_fix3): Don't increment value for a PC
+ relative reloc when BFD_ASSEMBLER and OBJ_AOUT (more ugly gas
+ reloc hacking).
+
+ * config/obj-aout.h (S_IS_DEFINE): non BFD_ASSEMBLER version:
+ Don't check S_GET_OTHER.
+
+
+ * config/tc-mips.c (mips_ip): Accept an odd floating point
+ register with l.s or s.s.
+
+ * config/obj-aout.c (obj_pseudo_table): Use obj_aout_type for
+ .type pseudo-op.
+ (obj_aout_type): New static function.
+
+
+ * Makefile.in ($(OBJS)): Depend upon libiberty.h.
+
+start-sanitize-v850
+
+ * config/tc-v850.c (v850_reloc_prefix): Recognize zdaoff, tdaoff
+ and sdaoff expressions.
+
+ * write.c (fixup_segment): Don't add symbol value to addend if
+ TC_V850 and OBJ_ELF.
+ * config/tc-v850.h (tc_fix_adjustable): Don't adjust any
+ pc-relative fixups.
+
+ * config/tc-v850.c (md_pcrel_from): Undo yesterday's changes.
+ (md_pcrel_from_section): Likewise.
+ * config/tc-v850.h (MD_PCREL_FROM_SECTION): Likewise.
+
+
+ * config/tc-v850.c (md_pcrel_from): Delete unused function.
+ (md_pcrel_from_section): New function.
+ * config/tc-v850.h (MD_PCREL_FROM_SECTION): Define.
+
+end-sanitize-v850
+
+ * config/tc-mips.c (load_register): Add cast to offsetT when using
+ a constant with &~.
+
+
+ * config/obj-elf.c (elf_frob_file): Move ECOFF debug processing to ...
+ (elf_frob_file_after_relocs): ... here. New function.
+ * config/obj-elf.h (obj_from_file_after_relocs): New macro.
+ * write.c (write_object_file): Call *frob_after_relocs after the
+ call to write_relocs.
+
+ * config/tc-alpha.c: Use new BFD_RELOC_ALPHA_ELF_LITERAL reloc.
+
+ * config/tc-alpha.c (load_expression): Don't SET_VALUE on the section
+ symbol, as this messes up linking. Instead, expand the recursive call
+ inline and change up the appropriate bits to get the 0x8000 offset
+ in the reloc addend.
+
+
+ * config/tc-sparc.h (tc_fix_adjustable): Permit the difference of
+ two symbols in the same segment to be adjusted.
+
+ * configure.in: Don't get confused by CPU-VENDOR-linux-gnu.
+ * configure: Rebuild.
+
+
+ * config/tc-ppc.c (ppc_insert_operand): Change most warnings into
+ errors.
+ (ppc_elf_validate_fix): Ditto.
+ (md_assemble): Ditto.
+ (ppc_tc): Ditto.
+ (ppc_pe_section): Ditto.
+ (ppc_frob_symbol): Ditto.
+
+
+ * config/mn10300.c (md_assemble): Pass an extra shift count
+ to mn10300_insert_operand based on the opcode format.
+ (mn10300_insert_operand): Accept and use extra shift count
+ parameter.
+
+ * config/tc-mn10300.c (md_assemble): Use FMT_* macros for
+ formats rather than hard-coded constants.
+
+ * config/tc-mn10300.c (md_assemble): Format D5 instructions
+ are 7 bytes long. Write out instructions in big-endian format.
+
+
+ * config/tc-mn10300.c (md_assemble): Tweak further so
+ that all instructions are parsed correctly.
+
+
+ * as.h: Include libiberty.h.
+ (xmalloc, xrealloc): Don't declare.
+ * as.c: Don't include libiberty.h.
+ * expr.c, read.c, stabs.c, config/obj-coff.c: Likewise.
+ * config/tc-mips.c: Likewise.
+ * messages.c: Likewise.
+ (xstrerror): Don't declare.
+ * xmalloc.c: Remove.
+
+
+ * config/tc-mn10300.h (pre_defined_registers) Remove.
+ (system_registers, cc_names): Likewise.
+ (address_registers, data_registers, other_registers): New register
+ arrays.
+ (register_name, system_register_name, cc_name): Remove.
+ (mn10300_reloc_prefix): Likewise.
+ (data_register_name): New function.
+ (address_register_name, other_register_name): Likewise.
+ (md_assemble): Rough cut at parsing operands. Remove lots of
+ unwanted code.
+ (md_apply_fix3): Disable for now.
+
+
+ * config/tc-m68k.c (select_control_regs): New function, extracted
+ out of m68k_init_after_args.
+ (m68k_init_after_args): Use it.
+ (mri_chip): Use it here as well to update set of allowed control
+ regs for movec.
+
+
+ * config/obj-elf.c (elf_begin): New function.
+ (obj_elf_section): Add the section symbol to the symbol table.
+ * config/obj-elf.h (obj_begin): Define.
+ (elf_begin): Declare.
+ * as.c (perform_an_assembly_pass): Call obj_begin if it is
+ defined.
+
+
+ * config/obj-coff.c (fixup_segment): Subtract the section address
+ from a PC relative reloc if TC_M68K.
+
+
+ * config/tc-sparc.c (md_pseudo_table): Make .uahalf, .uaword, and
+ .uaxword available even if not OBJ_ELF.
+ (md_atof): Remove unused local variable wordP.
+
+
+ * config/tc-mn10x00.c, config/tc-mn10x00.h: New files
+ for Matsushita MN10x00 support.
+ * configure.in: Recognize mn10x00-*-*
+ * configure: Rebuilt.
+
+
+ * obj-evax.h: move openvms definitions from here to tc-alpha.c.
+ * tc-alpha.c: add support for vms_case_hack like in vax/vms.
+ (load_expression): track clobbering of base reg before jmp/jsr.
+ (s_alpha_file): pass case_hack flags and source filename via
+ symbol table to bfd.
+ * tc-alpha.h (TC_CONS_FIX_NEW): define
+
+
+ * configure.in (mips-*-rtems*): New target, like mips-*-elf*.
+ * configure: Rebuild.
+
+
+ * read.c (s_macro): Warn if a macro has the same name as a
+ pseudo-op.
+ (s_space): In m68k MRI mode, align to a word boundary.
+ * macro.c (define_macro): Add namep parameter. Change all
+ callers.
+ * macro.h (define_macro): Update declaration.
+
+ * as.c (show_usage): Print bug report address.
+ (parse_args): Change version printing to match current GNU
+ standards.
+ * gasp.c (show_usage): Print bug report address.
+ (main): Change version printing to match current GNU standards.
+
+ * config/tc-m68k.c (init_table): Correct access control unit
+
+ * config/tc-alpha.c: Add some static function prototypes.
+ (alpha_macros): Move to top of file. Make static.
+ (alpha_num_macros): Move to top of file.
+
+start-sanitize-v850
+
+ * tc-v850.h: Define LOCAL_LABEL to recognise _.L_* symbols
+ generated by DWARF.
+
+end-sanitize-v850
+
+ * listing.c (list_symbol_table): Remove bogus code in BFD64 case,
+ and just call sprintf_vma.
+
+
+ * expr.c (expr): Change >>= to >> (fix typo). (From meissner).
+
+
+ * read.c (float_cons): Call md_flush_pending_output if it is
+ defined.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c (md_operand): Created. Allows operands to
+ start with '#'.
+ * config/tc-d10v.h (md_operand): Undefined.
+
+end-sanitize-d10v
+
+ * config/tc-m68k.c (add_fix): Treat a width of '3' like 'B'.
+ (md_assemble): A fixup width of '3' means a 1 byte reloc.
+
+
+ * config/obj-coff.c (fixup_segment): Don't adjust PC relative
+ reloc for the i960 for a reloc in the same section. This undoes
+ one of the two changes made Aug 19.
+
+
+ * config/obj-coff.c (obj_coff_endef): Both versions: Move C_STAT
+ symbols to the position of the debugging information.
+
+
+ * expr.c (expr): Always use unsigned right shifts for >>.
+
+
+ * config/tc-arm.c (md_apply_fix3): Update two thumb instruction
+ slots when processing BL fixups.
+
+ * config/tc-arm.c (output_inst): Ensure Thumb BL fixup is marked
+ on the first half of the instruction.
+
+
+ * ecoff.c (ecoff_stab): Create an expression symbol for a complex
+ stabs expression, rather than giving an error.
+
+ * ecoff.c (ecoff_new_file): Don't do anything if we are still in
+ the same file.
+
+
+ * config/tc-mips.c (append_insn): Fill in the value for a constant
+ jump, rather than creating a reloc.
+
+
+ * config/tc-mips.c (append_insn): Don't swap an instruction which
+ sets a condition code with an instruction which uses a condition
+ code.
+ (mips_ip): In cases 'N' and 'M', look for $fccN rather than an
+ immediate value.
+
+ * config/tc-mips.c (md_begin): Recognize r5000 for cpu.
+ (mips_ip): Give a better error message if the ISA level is wrong.
+ (md_parse_option): Recognize -mcpu=[v][r]5000.
+
+
+ * config/tc-mips.c (COUNT_TOP_ZEROES): Added macro to count
+ leading zeroes.
+ (load_register): Ensure hi32 bits are not lost during lo32bit
+ processing. Fix shift offset that was overflowing into the next
+ instruction field. Add code to generate shorter sequences for
+ constants with a single contiguous seqeuence of ones.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c (d10v_dot_word): New function to support
+ "@word" with the word pseudo-op.
+ (md_apply_fix3): Cleanup and changes to support correct sizes
+ for 16 and 18-bit relocs.
+
+end-sanitize-d10v
+
+ * configure.in (sparc-*-aout): Set `em'.
+ * configure: Regenerated.
+ * config/te-sparcaout.h: New file.
+ * config/tc-sparc.h (TARGET_BYTES_BIG_ENDIAN): Define.
+ Ifdef TE_SPARCOUT define TARGET_FORMAT and SPARC_BIENDIAN.
+ * config/tc-sparc.c (INSN_BIG_ENDIAN): New macro.
+ (SPECIAL_CASE_{SETSW,SETX}): Define.
+ ({NOP,OR,FMOVS,SETHI,SLLX,SRA}_INSN): Define.
+ (md_begin): Delete setting of `target_big_endian'.
+ (output_insn): New function.
+ (md_assemble): Rewrite. Add `setx' support.
+ (sparc_ip): Handle `0' operand char. Recognize setuw, setsw, setx
+ special cases.
+ (md_atof): Add little endian support.
+ (md_number_to_chars): Likewise.
+ (md_apply_fix): Likewise.
+ (md_longopts): Recognize -EL,-EB ifdef SPARC_BIENDIAN.
+ (md_parse_option): Likewise.
+ (md_show_usage): Print -EL, -EB ifdef SPARC_BIENDIAN.
+
+
+ * ecoff.c (ecoff_new_file): New function.
+ * ecoff.h (ecoff_new_file): Declare.
+ * config/obj-ecoff.h (obj_app_file): Define.
+
+
+ * config/tc-alpha.c (load_expression): Bias the .lit8 section
+ symbol by 32k so that our 16-bit signed offset can address the
+
+
+ * config/tc-mips.c (load_register): Remove unused variable tmp.
+
+
+ * config/tc-mips.c (load_register): Remove unnecessary code that
+ was causing the high 32bits of 64bit constants to be lost.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c: Added changes to support function
+ pointers and "@word" syntax.
+
+end-sanitize-d10v
+start-sanitize-v850
+
+ * config/tc-v850.c: Remove commented out and #if 0'd code.
+ (v850_reloc_prefix): Provide prototype.
+ (postfix, get_reloc, build_insn): Remove prototypes for nonexistant
+ functions.
+ (md_begin, md_assemble, md_apply_fix3): Remove unused variables.
+ (md_assemble): Add default to case statement.
+
+
+ * config/tc-v850.c (md_assemble): Compute size of the instrction
+ from the opcode.
+
+ * config/tc-v850.c (md_apply_fix3): Do simple byte, short and
+ word fixups too.
+
+
+ * config/tc-v850.c (md_apply_fix3): Use little endian get/put
+ routines to fetch/store the updated instruction from/to memory.
+ (v850_insert_operand): If the operand has a specialized insert
+ routine, call it.
+
+
+ * config/tc-v850.c (reg_name_search): Align calling convention to
+ be like identical function found in tc-ppc.c.
+ (get_reloc): Removed.
+ (v850_reloc_prefix): New function, parse lo(), hi() and hi0().
+ (md_assemble): emit fixups.
+ (md_pcrel_from): renamed from md_pcrel_from_section, emit proper
+ displacement.
+ (md_apply_fix3): handle fixups/relocs.
+ * config/tc-v850.h (MD_PCREL_FROM_SECTION): Removed definition.
+
+end-sanitize-v850
+
+ Add SH ELF support.
+ * configure.in (sh-*-elf*): New target.
+ * config/tc-sh.h (TARGET_ARCH): Define.
+ (WORKING_DOT_WORD): Define.
+ (TC_COFF_FIX2RTYPE): Only define if OBJ_COFF.
+ (BFD_ARCH, COFF_MAGIC, TC_COUNT_RELOC): Likewise.
+ (TC_RELOC_MANGLE, tc_coff_symbol_emit_hook): Likewise.
+ (DO_NOT_STRIP, NEED_FX_R_TYPE, TC_KEEP_FX_OFFSET): Likewise.
+ (TC_COFF_SIZEMACHDEP, tc_frob_file): Likewise.
+ (SUB_SEGMENT_ALIGN): Likewise.
+ (RELOC_32): Don't define.
+ (tc_frob_file_before_adjust): Define if BFD_ASSEMBLER.
+ (target_big_endian): Declare if OBJ_ELF.
+ (TARGET_FORMAT): Define if OBJ_ELF.
+ * config/tc-sh.c: Use BFD reloc codes instead of SH COFF reloc
+ numbers throughout.
+ (tc_crawl_symbol_chain): Only define if OBJ_COFF.
+ (tc_headers_hook, tc_coff_sizemachdep): Likewise.
+ (struct sh_count_relocs): Define.
+ (sh_count_relocs): New static function, broken out of
+ sh_frob_file. Add BFD_ASSEMBLER code.
+ (sh_frob_section): Likewise.
+ (sh_frob_file): Call sh_frob_section.
+ (md_convert_frag): If BFD_ASSEMBLER, change type of headers, and
+ call section_symbol rather than seg_info (seg)->dot.
+ (md_section_align): Add OBJ_ELF version.
+ (SWITCH_TABLE_CONS): Define.
+ (SWITCH_TABLE): Use SWITCH_TABLE_CONS.
+ (md_apply_fix): Change parameter types if BFD_ASSEMBLER. Only
+ handle fx_r_type == 0 if not BFD_ASSEMBLER. Return 0 if
+ BFD_ASSEMBLER.
+ (struct reloc_map): Define if not BFD_ASSEMBLER.
+ (coff_reloc_map): Likewise.
+ (sh_coff_reloc_mangle): Use coff_reloc_map to convert fx_r_type.
+ (tc_gen_reloc): New function if BFD_ASSEMBLER.
+ * write.c (write_relocs): Ifdef out fx_where test which triggers
+ inappropriately for SH ELF.
+ (write_object_file): Call tc_frob_file_before_adjust and
+ obj_frob_file_before_adjust if they are defined.
+
+ * write.c (write_object_file): Use BFD_RELOC_16, not
+ BFD_RELOC_NONE, when calling fix_new_exp for a broken word.
+
+ * read.c (emit_expr): Fix conversion of byte count to BFD reloc
+ code.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c (find_opcode): Fix problem with calculating
+ branch sizes in across sections.
+
+end-sanitize-d10v
+start-sanitize-v850
+
+ * config/tc-850.c (md_assemble): Handle hi() correctly. Handle
+ hi0() too.
+
+
+ * config/tc-v850.c (md_begin): Deal with end of opcode
+ table marker.
+
+end-sanitize-v850
+start-sanitize-d10v
+
+ * config/tc-d10v.c (find_opcode): Fix a bug which could generate
+ the wrong opcode for cases like st2w where there are many forms
+ of the same instruction.
+
+end-sanitize-d10v
+
+ * expr.c (operand): If md_parse_name is defined, call it before
+ calling symbol_find_or_make.
+ * config/tc-ppc.h (md_parse_name): Define.
+ (ppc_parse_name): Declare.
+ * config/tc-ppc.c (reg_name_search): Add regs and regcount
+ parameters.
+ (register_name): Update call to reg_name_search.
+ (cr_operand): New static variable.
+ (cr_names): New static const array.
+ (ppc_parse_name): New function.
+ (md_assemble): If PPC_OPERAND_CR is set in the operand flags, set
+ cr_operand before calling expression.
+
+
+ * config/tc-hppa.c (tc_gen_reloc): Add new argument to
+ hppa_gen_reloc_type call.
+
+start-sanitize-d10v
+
+ * config/tc-d10v.c: Fixed ".word". Fixed problem with range checking
+ on addresses. Improved error messages.
+ * doc/c-d10v.texi: Added docs for register pairs.
+
+
+ * config/tc-d10v.c (parallel_ok): Fix bug in parallel
+ checking code.
+
+end-sanitize-d10v
* ecoff.c (init_file): Initialize fMerge to 1.
projects / binutils.git / blobdiff