+
+ * mmix.h: New file.
+
+
+ * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end
+ of the expression, to make source code merging easier.
+
+
+ * mips.h: Sort coprocessor instruction argument characters
+ in comment, add a few more words of description for "H".
+
+
+ * mips.h (INSN_SB1): New cpu-specific instruction bit.
+ (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
+ if cpu is CPU_SB1.
+
+
+ * ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
+
+
+ * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New
+ opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403
+ instructions, respectively.
+
+
+ * v850.h: Remove spurious comment.
+
+
+ * h8300.h: Fix compile time warning messages
+
+
+ * alpha.h (struct alpha_operand): Pack elements into bitfields.
+
+
+ * mips.h: Remove CPU_MIPS32_4K.
+
+
+ * ppc.h (PPC_OPERAND_DS): Define.
+
+
+ * d30v.h: Fix declaration of reg_name_cnt.
+
+ * d10v.h: Fix declaration of d10v_reg_name_cnt.
+
+ * arc.h: Add prototypes from opcodes/arc-opc.c.
+
+
+ * mips.h (INSN_10000): Define.
+ (OPCODE_IS_MEMBER): Check for INSN_10000.
+
+
+ * ppc.h: Revert 2001-08-08.
+
+
+ * ppc.h (struct powerpc_operand): New field `reloc'.
+
+
+ * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
+ (cgen_cpu_desc): Ditto.
+
+
+ * m88k.h: Clean up and reformat. Remove unused code.
+
+
+ * cgen.h (cgen_keyword): Add nonalpha_chars field.
+
+
+ * mips.h (CPU_R12000): Define.
+
+
+ * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
+
+
+ * mips.h (INSN_ISA_MASK): Define.
+
+
+ * i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg,
+ not an mmx reg. Swap xmm/mmx regs on both movdq2q and movq2dq,
+ and use InvMem as these insns must have register operands.
+
+
+ * i386.h (i386_optab): Move InvMem to first operand of pmovmskb
+ and pextrw to swap reg/rm assignments.
+
+
+ * cris.h (enum cris_insn_version_usage): Correct comment for
+ cris_ver_v3p.
+
+
+ * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq".
+ Add InvMem to first operand of "maskmovdqu".
+
+
+ * cris.h (ADD_PC_INCR_OPCODE): New macro.
+
+
+ * h8300.h: Fix formatting.
+
+
+ * i386.h (i386_optab): Add paddq, psubq.
+
+
+ * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define.
+
+
+ * m68k.h: new defines for Coldfire V4. Update mcf to know
+ about mcf5407.
+
+
+ * pdp11.h: New file.
+
+
+ * i386.h (i386_optab): SSE integer converison instructions have
+ 64bit versions on x86-64.
+
+
+ * mips.h: Remove extraneous whitespace. Formating change to allow
+ for future contribution.
+
+
+ * s390.h: New file.
+
+
+ * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
+ (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
+ (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
+
+
+ * i386.h (i386_optab): Fix swapgs
+
+
+ * hppa.h: Describe new '<' and '>' operand types, and tidy
+ existing comments.
+ (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw.
+ Remove duplicate "ldw j(s,b),x". Sort some entries.
+
+
+ * i386.h (i386_optab): Fix pusha and ret templates.
+
+
+ * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New
+ definitions for masking cpu type.
+ (arc_ext_operand_value) New structure for storing extended
+ operands.
+ (ARC_OPERAND_*) Flags for operand values.
+
+
+ * i386.h (pinsrw): Add.
+ (pshufw): Remove.
+ (cvttpd2dq): Fix operands.
+ (cvttps2dq): Likewise.
+ (movq2q): Rename to movdq2q.
+
+
+ * i386.h: Correct movnti instruction.
+
+
+ * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number
+ of operands (unsigned char or unsigned short).
+ (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
+ (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
+
+
+ * i386.h (i386_optab): Make [sml]fence template to use immext field.
+
+
+ * i386.h (i386_optab): Fix 64bit pushf template; Add instructions
+ introduced by Pentium4
+
+
+ * i386.h (i386_optab): Add "rex*" instructions;
+ add swapgs; disable jmp/call far direct instructions for
+ 64bit mode; add syscall and sysret; disable registers for 0xc6
+ template. Add 'q' suffixes to extendable instructions, disable
+ obsolete instructions, add new sign/zero extension ones.
+ (i386_regtab): Add extended registers.
+ (*Suf): Add No_qSuf.
+ (q_Suf, wlq_Suf, bwlq_Suf): New.
+
+
+ * i386.h (i386_optab): Replace "Imm" with "EncImm".
+ (i386_regtab): Add flags field.
+
+
+ * mips.h: Fix formatting.
+
+
+ mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
+ (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
+ OP_*_SYSCALL definitions.
+ (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
+ 19 bit wait codes.
+ (MIPS operand specifier comments): Remove 'm', add 'U' and
+ 'J', and update the meaning of 'B' so that it's more general.
+
+ * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
+ INSN_ISA5): Renumber, redefine to mean the ISA at which the
+ instruction was added.
+ (INSN_ISA32): New constant.
+ (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
+ Renumber to avoid new and/or renumbered INSN_* constants.
+ (INSN_MIPS32): Delete.
+ (ISA_UNKNOWN): New constant to indicate unknown ISA.
+ (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
+ ISA_MIPS32): New constants, defined to be the mask of INSN_*
+ constants available at that ISA level.
+ (CPU_UNKNOWN): New constant to indicate unknown CPU.
+ (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
+ define it with a unique value.
+ (OPCODE_IS_MEMBER): Update for new ISA membership-related
+ constant meanings.
+
+ * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
+ definitions.
+
+ * mips.h (CPU_SB1): New constant.
+
+
+ * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
+ Note that '3' is used for siam operand.
+
+
+ * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
+
+
+ * mips.h: Use defines instead of hard-coded processor numbers.
+ (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
+ CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
+ CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
+ CPU_4KC, CPU_4KM, CPU_4KP): Define..
+ (OPCODE_IS_MEMBER): Use new defines.
+ (OP_MASK_SEL, OP_SH_SEL): Define.
+ (OP_MASK_CODE20, OP_SH_CODE20): Define.
+ Add 'P' to used characters.
+ Use 'H' for coprocessor select field.
+ Use 'm' for 20 bit breakpoint code.
+ Document new arg characters and add to used characters.
+ (INSN_MIPS32): New define for MIPS32 extensions.
+ (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
+
+
+ * hppa.h: Mention cz completer.
+
* ia64.h (IA64_OPCODE_POSTINC): New.
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
IgnoreSize change.
+
+ * i860.h: Small formatting adjustments.
+
* avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.
* cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
+
+ * i860.h (btne, bte, bla): Changed these opcodes
+ to use sbroff ('r') instead of split16 ('s').
+ (J, K, L, M): New operand types for 16-bit aligned fields.
+ (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
+ use I, J, K, L, M instead of just I.
+ (T, U): New operand types for split 16-bit aligned fields.
+ (st.x): Changed these opcodes to use S, T, U instead of just S.
+ (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
+ exist on the i860.
+ (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
+ (pfeq.ss, pfeq.dd): New opcodes.
+ (st.s): Fixed incorrect mask bits.
+ (fmlow): Fixed incorrect mask bits.
+ (fzchkl, pfzchkl): Fixed incorrect mask bits.
+ (faddz, pfaddz): Fixed incorrect mask bits.
+ (form, pform): Fixed incorrect mask bits.
+ (pfld.l): Fixed incorrect mask bits.
+ (fst.q): Fixed incorrect mask bits.
+ (all floating point opcodes): Fixed incorrect mask bits for
+ handling of dual bit.
+
cris.h: New file.
* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
(CGEN_CPU_TABLE): flags: new field.
Add prototypes for new functions.
-
+
* i386.h: Add some more UNIXWARE_COMPAT comments.
* i370.h: New file.
+
+ * d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation
+ cannot be combined in parallel with ADD/SUBppp.
+
* mips.h: (OPCODE_IS_MEMBER): Add comment.
* hppa.h (pa_opcodes): Use 'fX' for first register operand
- in xmpyu.
+ in xmpyu.
* hppa.h (pa_opcodes): Fix mask for probe and probei.
* hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
- * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
+ * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
* hppa.h (pa_opcodes): Move integer arithmetic instructions after
- integer logical instructions.
+ integer logical instructions.
- * hppa.h (pa_opcodes): Add second entry for "comb", "comib",
+ * hppa.h (pa_opcodes): Add second entry for "comb", "comib",
"addb", and "addib" to be used by the disassembler.
(CGEN_INSN_ATTR): New type.
-
+
* i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define.
(x_FP, d_FP, dls_FP, sldx_FP): Define.
Change *Suf definitions to include x and d suffixes.
* cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT,
CGEN_MODE_UINT.
* hppa.h (bv): Fix mask.
The following is part of a change made by Edith Epstein
- changes by HP; HP did not create ChangeLog entries.
+ changes by HP; HP did not create ChangeLog entries.
* hppa.h (completer_chars): list of chars to not put a space
- after.
+ after.
* i386.h (i386_optab): Permit w suffix on processor control and
- status word instructions.
+ status word instructions.
* hppa.h: Add "fid".
-
+
* mn10300.h: Add "machine" field for instructions.
(MN103, AM30): Define machine types.
-
+
* i386.h: Use FP, not sl_Suf, for fxsave and fxrstor.
* alpha.h: Don't include "bfd.h"; private relocation types are now
- negative to minimize problems with shared libraries. Organize
- instruction subsets by AMASK extensions and PALcode
- implementation.
+ negative to minimize problems with shared libraries. Organize
+ instruction subsets by AMASK extensions and PALcode
+ implementation.
(struct alpha_operand): Move flags slot for better packing.
* v850.h (v850_operands): Add insert and extract fields, pointers
- to functions used to handle unusual operand encoding.
+ to functions used to handle unusual operand encoding.
(V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC,
- V850_OPERAND_SIGNED): Defined.
+ V850_OPERAND_SIGNED): Defined.
* mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
- OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
- OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
- OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
- OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
- Defined.
+ OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
+ OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
+ OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
+ OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
+ Defined.
* d10v.h: Add some additional defines to support the
- assembler in determining which operations can be done in parallel.
+ assembler in determining which operations can be done in parallel.
* d10v.h: Changes for divs, parallel-only instructions, and
- signed numbers.
+ signed numbers.
- * m68k.h (mcf5200): New macro.
+ * m68k.h (mcf5200): New macro.
Document names of coldfire control registers.
* mips.h: Added INSN_4100 flag to mark NEC VR4100 specific
- instructions.
+ instructions.
- * ../include/opcode/vax.h (struct vot_wot, field `args'): make
- it pointer to const char;
+ * vax.h (struct vot_wot, field `args'): Make it pointer to const
+ char.
(struct vot, field `name'): ditto.
* hppa.h: Update "free list" of letters and update
comments describing each letter's function.
+
+ * h8300.h: Lots of little fixes for the h8/300h.
+
+
+ Support for H8/300-H
+ * h8300.h: Lots of new opcodes.
+
* h8300.h: checkpoint, includes H8/300-H opcodes.
* sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is
disassembled as a nop.
+Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com)
+
+ * m68k.h, sparc.h: ANSIfy enums.
+
Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com)
* sparc.h: fix a typo.
* a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h,
m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h,
- vax.h, ChangeLog: renamed from ../<foo>-opcode.h
+ vax.h: Renamed from ../<foo>-opcode.h.
\f
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