* stabs.c (_bfd_link_section_stabs): If the output_section field

[binutils.git] / bfd / bfd-in2.h

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 496fb617f8ea656b5dd7cd1798ff0ecb6ccfd8ce..0ab5432f9b37600cdfd77ffdfb590c5ecff04838 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -53,8 +53,12 @@ extern "C" {
 
 /* These two lines get substitutions done by commands in Makefile.in.  */
 #define BFD_VERSION  "@VERSION@"
-#define BFD_ARCH_SIZE @WORDSIZE@
+#define BFD_ARCH_SIZE @wordsize@
 #define BFD_HOST_64BIT_LONG @BFD_HOST_64BIT_LONG@
+#if @BFD_HOST_64_BIT_DEFINED@
+#define BFD_HOST_64_BIT @BFD_HOST_64_BIT@
+#define BFD_HOST_U_64_BIT @BFD_HOST_U_64_BIT@
+#endif
 
 #if BFD_ARCH_SIZE >= 64
 #define BFD64
@@ -114,27 +118,29 @@ typedef long int file_ptr;
 /* Support for different sizes of target format ints and addresses.
    If the type `long' is at least 64 bits, BFD_HOST_64BIT_LONG will be
    set to 1 above.  Otherwise, if gcc is being used, this code will
-   use gcc's "long long" type.  Otherwise, the compilation will fail
-   if 64-bit targets are requested.  */
+   use gcc's "long long" type.  Otherwise, BFD_HOST_64_BIT must be
+   defined above.  */
 
 #ifdef BFD64
 
 #ifndef BFD_HOST_64_BIT
 #if BFD_HOST_64BIT_LONG
 #define BFD_HOST_64_BIT long
+#define BFD_HOST_U_64_BIT unsigned long
 #else
 #ifdef __GNUC__
 #define BFD_HOST_64_BIT long long
+#define BFD_HOST_U_64_BIT unsigned long long
 #else /* ! defined (__GNUC__) */
  #error No 64 bit integer type available
 #endif /* ! defined (__GNUC__) */
 #endif /* ! BFD_HOST_64BIT_LONG */
 #endif /* ! defined (BFD_HOST_64_BIT) */
 
-typedef unsigned BFD_HOST_64_BIT bfd_vma;
+typedef BFD_HOST_U_64_BIT bfd_vma;
 typedef BFD_HOST_64_BIT bfd_signed_vma;
-typedef unsigned BFD_HOST_64_BIT bfd_size_type;
-typedef unsigned BFD_HOST_64_BIT symvalue;
+typedef BFD_HOST_U_64_BIT bfd_size_type;
+typedef BFD_HOST_U_64_BIT symvalue;
 
 #ifndef fprintf_vma
 #if BFD_HOST_64BIT_LONG
@@ -193,7 +199,7 @@ typedef enum bfd_format {
    to another, and are not necessarily correct).  */
 
 /* No flags.  */
-#define NO_FLAGS       0x00
+#define BFD_NO_FLAGS           0x00
 
 /* BFD contains relocation entries.  */
 #define HAS_RELOC      0x01
@@ -1198,6 +1204,9 @@ enum bfd_architecture
   bfd_arch_powerpc,    /* PowerPC */
   bfd_arch_rs6000,     /* IBM RS/6000 */
   bfd_arch_hppa,       /* HP PA RISC */
+  /* start-sanitize-d10v */
+  bfd_arch_d10v,       /* Mitsubishi D10V */
+  /* end-sanitize-d10v */
   bfd_arch_z8k,        /* Zilog Z8000 */
 #define bfd_mach_z8001         1
 #define bfd_mach_z8002         2
@@ -1207,6 +1216,9 @@ enum bfd_architecture
   bfd_arch_arm,        /* Advanced Risc Machines ARM */
   bfd_arch_ns32k,      /* National Semiconductors ns32000 */
   bfd_arch_w65,        /* WDC 65816 */
+  /* start-sanitize-v850 */
+  bfd_arch_v850,       /* NEC V850 */
+  /* end-sanitize-v850 */
   /* start-sanitize-arc */
   bfd_arch_arc,        /* Argonaut RISC Core */
 #define bfd_mach_arc_base 0
@@ -1547,11 +1559,6 @@ decided relatively late. */
   BFD_RELOC_GPREL16,
   BFD_RELOC_GPREL32,
 
-/* For openVMS/Alpha systems, these are displacements for switch
-tables. */
-  BFD_RELOC_SWREL32,
-  BFD_RELOC_SWREL64,
-
 /* Reloc types used for i960/b.out. */
   BFD_RELOC_I960_CALLJ,
 
@@ -1641,13 +1648,10 @@ The GNU linker currently doesn't do any of this optimizing. */
 prediction logic which may be provided on some processors. */
   BFD_RELOC_ALPHA_HINT,
 
-/* The LINKAGE relocation outputs a special code in the object file,
-the rest is handled by the linker. */
+/* The LINKAGE relocation outputs a linkage pair in the object file,
+which is filled by the linker. */
   BFD_RELOC_ALPHA_LINKAGE,
 
-/* The BASEREG relocation calculates differences to basereg. */
-  BFD_RELOC_ALPHA_BASEREG,
-
 /* Bits 27..2 of the relocation address shifted right 2 bits;
 simple reloc otherwise. */
   BFD_RELOC_MIPS_JMP,
@@ -1762,6 +1766,32 @@ not stored in the instruction. */
   BFD_RELOC_ARM_LDR_IMM,
   BFD_RELOC_ARM_LITERAL,
   BFD_RELOC_ARM_IN_POOL,
+  BFD_RELOC_ARM_OFFSET_IMM8,
+  BFD_RELOC_ARM_HWLITERAL,
+  BFD_RELOC_ARM_THUMB_ADD,
+  BFD_RELOC_ARM_THUMB_IMM,
+  BFD_RELOC_ARM_THUMB_SHIFT,
+  BFD_RELOC_ARM_THUMB_OFFSET,
+
+/* Hitachi SH relocs.  Not all of these appear in object files. */
+  BFD_RELOC_SH_PCDISP8BY2,
+  BFD_RELOC_SH_PCDISP12BY2,
+  BFD_RELOC_SH_IMM4,
+  BFD_RELOC_SH_IMM4BY2,
+  BFD_RELOC_SH_IMM4BY4,
+  BFD_RELOC_SH_IMM8,
+  BFD_RELOC_SH_IMM8BY2,
+  BFD_RELOC_SH_IMM8BY4,
+  BFD_RELOC_SH_PCRELIMM8BY2,
+  BFD_RELOC_SH_PCRELIMM8BY4,
+  BFD_RELOC_SH_SWITCH16,
+  BFD_RELOC_SH_SWITCH32,
+  BFD_RELOC_SH_USES,
+  BFD_RELOC_SH_COUNT,
+  BFD_RELOC_SH_ALIGN,
+  BFD_RELOC_SH_CODE,
+  BFD_RELOC_SH_DATA,
+  BFD_RELOC_SH_LABEL,
 /* start-sanitize-arc */
 
 /* Argonaut RISC Core (ARC) relocs.
@@ -1775,6 +1805,34 @@ stored in the instruction.  The high 24 bits are installed in bits 23
 through 0. */
   BFD_RELOC_ARC_B26,
 /* end-sanitize-arc */
+
+/* start-sanitize-d10v */
+
+/* Mitsubishi D10V relocs.
+This is a 10-bit reloc with the right 2 bits
+assumed to be 0. */
+  BFD_RELOC_D10V_10_PCREL_R,
+
+/* Mitsubishi D10V relocs.
+This is a 10-bit reloc with the right 2 bits
+assumed to be 0.  This is the same as the previous reloc
+except it is in the left container, i.e.,
+shifted left 15 bits. */
+  BFD_RELOC_D10V_10_PCREL_L,
+
+/* This is an 18-bit reloc with the right 2 bits
+assumed to be 0. */
+  BFD_RELOC_D10V_18,
+
+/* This is an 18-bit reloc with the right 2 bits
+assumed to be 0. */
+  BFD_RELOC_D10V_18_PCREL,
+/* end-sanitize-d10v */
+
+/* NEC V850 relocs. */
+  BFD_RELOC_V850_9_PCREL,
+  BFD_RELOC_V850_22_PCREL,
+
   BFD_RELOC_UNUSED };
 typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
 reloc_howto_type *