+
+ Contribute support for Intel's iWMMXt chip - an ARM variant:
+
+ * arm-dis.c (regnames): Add iWMMXt register names.
+ (set_iwmmxt_regnames): New function.
+ (print_insn_arm): Handle iWMMXt formatters.
+ * arm-opc.h: Document iWMMXt formatters.
+ (arm_opcod): Add iWMMXt instructions.
+
+
+ * i386-dis.c (dis386): Recognize icebp (0xf1).
+
+
+ * s390-dis.c (init_disasm): Rename S390_OPCODE_ESAME to
+ S390_OPCODE_ZARCH.
+ (print_insn_s390): Use new modes field of s390_opcodes.
+ * s390-mkopc.c (ARCHBITS_ESAONLY, ARCHBITS_ESA, ARCHBITS_ESAME): Remove.
+ (s390_opcode_mode_val, s390_opcode_cpu_val): New enums.
+ (struct op_struct): Remove archbits. Add mode_bits and min_cpu.
+ (insertOpcode): Replace archbits by min_cpu and mode_bits.
+ (dumpTable): Write mode_bits and min_cpu instead of archbits.
+ (main): Adapt to new format in s390-opcode.txt.
+ * s390-opc.c (s390_opformats): Replace archbits by min_cpu and
+ mode_bits.
+ * s390-opc.txt: Replace archbits by min_cpu and mode_bits.
+
+
+ * ppc-opc.c: Fix formatting. Update copyright date.
+
+
+ * ppc-opc.c (powerpc_opcodes): Readd tlbre for PPC403.
+
+
+ * hppa-dis.c: Formatting.
+
+
+ * hppa-dis.c (print_insn_hppa): Implement fcnv instruction modifiers.
+
+ * hppa-dis.c (print_insn_hppa <2 bit space register>): Do not print
+ the space register when the value is zero.
+
+
+ * mips-dis.c (print_mips_disassembler_options): Make 'i' unsigned,
+ use ARRAY_SIZE in loops.
+
+
+ * fr30-desc.c: Regenerate.
+
+
+ * i386-dis.c (dq_mode, Edq): Define.
+ (dis386_twobyte): Correct movd operands.
+ (OP_E): Handle dq_mode case.
+
+
+ * sparc-dis.c (print_insn_sparc): When examining values added in
+ to rs1, make sure that there are previous instructions.
+
+
+ * Add sh2e support:
+
+
+ * sh-dis.c (print_insn_shx): Handle bfd_mach_sh2e.
+ * sh-opc.h (arch_sh2e, arch_sh2e_up): New.
+ (arch_sh2_up): Added sh2e.
+ (sh_table): Replaced all occurrences of arch_sh3e_up with
+ arch_sh2e_up, except in fsqrt.
+
+
+ * sh64-dis.c: Include elf32-sh64.h.
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+
+
+ * alpha-opc.c (alpha_opcodes): Add bugchk, rduniq, wruniq, gentrap
+ PAL entry points.
+
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+
+ * Makefile.am (ALL_MACHINES): Add msp430-dis.lo.
+ * Makefile.in: Regenerate.
+
+
+ * ppc-opc.c (powerpc_macros <extrwi>): Accept a shift of 32.
+
+
+ * iq2000-asm.c: New file.
+ * iq2000-desc.c: Likewise.
+ * iq2000-desc.h: Likewise.
+ * iq2000-dis.c: Likewise.
+ * iq2000-ibld.c: Likewise.
+ * iq2000-opc.c: Likewise.
+ * iq2000-opc.h: Likewise.
+ * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h.
+ (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c,
+ iq2000-ibld.c, iq2000-opc.c.
+ (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo,
+ iq2000-ibld.lo, iq2000-opc.lo.
+ (CLEANFILES): Add stamp-iq2000.
+ (IQ2000_DEPS): New macro.
+ (stamp-iq2000): New target.
+ * Makefile.in: Regenerate.
+ * configure.in: Handle bfd_iq2000_arch.
+ * configure: Regenerate.
+
+
+ * mips-dis.c (print_insn_args): Use position extracted by "+A"
+ to calculate size for "+B". Redo code for "+C" so it shares
+ the same style as "+A" and "+B" now do.
+
+
+ * mips-dis.c: Update copyright years.
+ (print_insn_arg): Rename to...
+ (print_insn_args): This, returning void. Process the whole
+ string of args rather than a single one. Reindent.
+ (print_insn_mips): Update to match the above.
+
+
+ * mips-opc.c (mips_builtin_opcodes): Move "di" into the
+ right order alphabetically, and make all hex constants use
+ lower-case letters.
+
+
+ * mips-dis.c (mips_cp0sel_name): New structure.
+ (mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
+ (mips_cp0sel_names_sb1): New arrays.
+ (mips_arch_choice): New structure members "cp0sel_names" and
+ "cp0sel_names_len".
+ (mips_arch_choices): Add references to new cp0sel_names arrays
+ as appropriate, and make all existing entries reference
+ appropriate mips_XXX_names_numeric arrays rather than simply
+ using NULL.
+ (mips_cp0sel_names, mips_cp0sel_names_len): New variables.
+ (lookup_mips_cp0sel_name): New function.
+ (set_default_mips_dis_options): Set mips_cp0sel_names and
+ mips_cp0sel_names_len as appropriate. Remove now-unnecessary
+ checks for NULL register name arrays.
+ (parse_mips_dis_option): Likewise.
+ (print_insn_arg): Handle "+D" operand type.
+ * mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
+ of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
+ names symbolically.
+
+
+ * mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
+ (mips_hwr_names_mips3264r2): New arrays.
+ (mips_arch_choice): New "hwr_names" member.
+ (mips_arch_choices): Adjust for structure change, and add a new
+ entry for "mips32r2" ISA.
+ (mips_hwr_names): New variable.
+ (set_default_mips_dis_options): Set mips_hwr_names.
+ (parse_mips_dis_option): New "hwr-names" option which sets
+ mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
+ (print_insn_arg): Change return type to "int"
+ and use that to indicate number of characters consumed.
+ Add support for "+" operand extension character, "+A", "+B",
+ "+C", and "K" operands.
+ (print_insn_mips): Adjust for changes to print_insn_arg.
+ (print_mips_disassembler_options): Adjust for "hwr-names"
+ addition and "reg-names" change.
+ * mips-opc (I33): New define (shorthand for INSN_ISA32R2).
+ (mips_builtin_opcodes): Note that "nop" and "ssnop" are special
+ forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
+ di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
+ rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
+ Note that hardware rotate instructions (ror, rorv) can be
+ used on MIPS32 Release 2, and add the official mnemonics
+ for them (rotr, rotrv) and the similar "rotl" mnemonic for
+ left-rotate.
+
+
+ * configure.in: Add msp430 target.
+ * configure: Regenerate.
+ * disassemble.c: Add entry for msp430 disassembly.
+ * msp430-dis.c: New file: msp430 disassembler.
+
+
+ * disassemble.c (disassembler_usage): Add invocation of
+ print_mips_disassembler_options.
+ * mips-dis.c: Include libiberty.h.
+ (print_mips_disassembler_options, set_default_mips_dis_options)
+ (parse_mips_dis_option, parse_mips_dis_options, choose_abi_by_name)
+ (choose_arch_by_name, choose_arch_by_number): New functions.
+ (mips_abi_choice, mips_arch_choice): New structures.
+ (mips32_reg_names, mips64_reg_names, reg_names): Remove.
+ (mips_gpr_names_numeric, mips_gpr_names_oldabi)
+ (mips_gpr_names_newabi, mips_fpr_names_numeric)
+ (mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64)
+ (mips_cp0_names_numeric, mips_cp0_names_mips3264)
+ (mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices)
+ (mips_processor, mips_isa, mips_gpr_names, mips_fpr_names)
+ (mips_cp0_names): New variables.
+ (print_insn_args): Use new variables to print GPR, FPR, and CP0
+ register names.
+ (mips_isa_type): Remove.
+ (print_insn_mips): Remove ISA and CPU setup since it is now done...
+ (_print_insn_mips): Here. Remove register setup code, and
+ call set_default_mips_dis_options and parse_mips_dis_options
+ instead.
+ (print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names.
+
+
+ * Makefile.in: Regenerate.
+
+
+ * cgen-asm.c (cgen_parse_keyword): Added underscore to symbol character
+ check to fix false keyword trigger with names such as <keyword>_foo.
+
+
+ * Makefile.am (CGEN_CPUS): New variable.
+ (run-cgen-all): New rule.
+ * Makefile.in: Regenerate.
+
+
+ * mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
+ "dror" entries, and reorder the remaining "dror" and "ror" entries.
+
+
+ * xstormy16-asm.c (parse_immediate16): Add prototype.
+
+
+ * xstormy16-asm.c: Regenerate.
+
+
+ * ns32k-dis.c (print_insn_ns32k): Constify "d", remove register
+ keyword.
+
+
+ * h8500-opc.h (h8500_table): Add missing initializers to quiet
+ warnings.
+ * pj-dis.c (print_insn_pj): Adjust for pj_opc_info_t change.
+ * pj-opc.c (pj_opc_info): Add braces around union initializer.
+ * z8kgen.c: Include "libiberty.h".
+ (opt, args, toks): Fix initializer warnings.
+ (chewname): Make "name" a char **. Return mnemonic trimmed of
+ operands.
+ (gas): Improve emitted "DO NOT EDIT" warning. Format emitted
+ opcode_entry_type, and make "nicename" and "name" const. Make
+ z8k_table const too. Formatting. Generate idx as gas needs it.
+ * z8k-opc.h: Regenerate.
+
+
+ * m68hc11-dis.c (print_indexed_operand): Fix PC-relative address
+ for 9 and 16-bit PC-relative addressing mode.
+
+
+ * ppc-opc.c: Delete evsabs, evsnabs, evsneg, evsadd, evssub,
+ evsmul, evsdiv, evscmpgt, evsgmplt, evststgt, evtstlt, evststeq,
+ evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi,
+ evsctsiz, evsctuf, evsctsf, evmwhssfaa, evmwhssmaa, evmwhsmfaa,
+ evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian,
+ evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa,
+ evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan,
+ evmwhgsmian, evmwhgumian.
+ (mftb): Add to opcode table.
+ (mtspefscr): Change RT to RS in opcode table.
+
+
+ * ppc-opc.c: Move mbar and msync up. Change mask for mbar and
+ msync.
+
+
+ * ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
+ * ia64-opc-b.c: Add "hint.b" instruction.
+ * ia64-opc-f.c: Add "hint.f" instruction.
+ * ia64-opc-i.c: Add "hint.i" instruction.
+ * ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
+ "cmp8xchg16" instructions.
+ * ia64-opc-x.c: Add "hint.x" instruction.
+
+ * ia64-opc.h (AR_CSD): New macro.
+
+ * ia64-ic.tbl: Update according to SDM2.1.
+ * ia64-raw.tbl: Ditto.
+ * ia64-waw.tbl: Ditto.
+
+ * ia64-gen.c (in_iclass): Handle "hint" like "nop".
+ (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
+ AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
+ * ia64-asmtab.c: Regenerate.
+
+
+ * ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa,
+ evmwlssfaaw, evmwlsmfaaw, evmwlssfanw, evmwlsfanw.
+
+
+ * ppc-opc.c (PMRN): Remove.
+ (RA): Set to NB + 1.
+ (powerpc_opcodes): Change PMRN to SPR.
+ Change all RD to RS.
+ Change mftb to look like mftbl.
+ Move mftb before mftbl.
+ Add mfbbtar.
+ Add mtbbtar.
+ Change mfpmr to use PMR.
+ Change mtpmr to use PMR.
+ (RD): Remove.
+ (insert_ev2): Fix mask and shift.
+ (extract_ev2): Same.
+ (insert_ev4): Same.
+ (extract_ev4): Same.
+ (PMR): Define.
+ (extract_pmrn): Remove.
+ (insert_pmrn): Remove.
+
+
+ * ia64-opc-m.c: Add ld8.mov.
+ * ia64-asmtab.c: Regenerate.
+
+
+ * arm-dis.c (print_insn_arm): Constify "insn". Formatting.
+ (print_insn_thumb): Likewise.
+ * h8500-dis.c (print_insn_h8500): Constify "opcode".
+ * mcore-dis.c (print_insn_mcore): Constify "op". Formatting.
+ * ns32k-dis.c (print_insn_arg <case 'F'>): Use a union to avoid
+ type-punned pointer warnings.
+ <case 'L'>: Likewise. Fix error message too.
+ * pdp11-dis.c (print_reg): Warning fix.
+ * sh-dis.c (print_movxy): Constify "op" param.
+ (print_insn_ddt): Constify sh_opcode_info vars.
+ (print_insn_ppi): Likewise.
+ (print_insn_sh): Likewise.
+ * tic30-dis.c (cnvt_tmsfloat_ieee): Use a union to avoid
+ type-punned pointer warnings.
+ * w65-dis.c (print_insn_w65): Constify "op".
+
+
+ * m68hc11-dis.c (PC_REGNUM): Define.
+ (print_indexed_operand): Need an adjustment for some PC-relative
+ operand modes; print the final address of PC-relative modes.
+ (print_insn): Take into account movw/movb to adjust the PC-relative
+ operand addresses.
+
+
+ *arm-dis.c, cris-dis.c, h8300-dis.c, mips-dis.c, mmix-dis.c, sh-dis.c,
+ sh64-dis.c, v850-dis.c: Replace boolean with bfd_boolean, true with
+ TRUE, false with FALSE. Simplify comparisons of bfd_boolean vars
+ with TRUE/FALSE. Formatting.
+
+
+ * xstormy16-opc.c: Regenerate.
+
+
+ * ia64-dis.c (print_insn_ia64): Correct handling of IA64_OPND_TGT64.
+
+
+ * xstormy16-desc.c: Regenerate.
+ * xstormy16-opc.c: Regenerate.
+ * xstormy16-opc.h: Regenerate.
+
+
+ * avr-dis.c: Include libiberty.h (for xmalloc).
+ (struct avr_opcodes_s): Remove 'bin_mask' field (it's
+ automatically computed in the init routine).
+ (AVR_INSN): No longer provide bin_mask field in initializer.
+ (avr_opcodes_s): Declare as const.
+ (print_insn_avr): Store the bin_mask field in a separate table
+ (allocated with xmalloc); iterate through it at the same time as
+ we iterate through the opcodes.
+
+
+ * h8300-dis.c: Include libiberty.h (for xmalloc).
+ (struct h8_instruction): New type, used to wrap h8_opcodes with a
+ length field (computed at run-time).
+ (h8_instructions): New variable.
+ (bfd_h8_disassemble_init): Allocate the storage for
+ h8_instructions. Fill h8_instructions with pointers to the
+ appropriate opcode and the correct value for the length field.
+ (bfd_h8_disassemble): Iterate through h8_instructions instead of
+ h8_opcodes.
+
+
+ * arc-opc.c (arc_ext_opcodes): Define.
+ (arc_ext_operands): Define.
+ * i386-dis.c (Suffix3DNow): Declare as const.
+ * arm-opc.h (arm_opcodes): Declare as const.
+ (thumb_opcodes): Declare as const.
+ * h8500-opc.h (h8500_table): Declare as const.
+ (h8500_table): Use a NULL for the opcode in the terminator, so
+ that code testing (opcode->name) behaves correctly.
+ * mcore-opc.h (mcore_table): Declare as const.
+ * sh-opc.h (sh_table): Declare as const.
+ * w65-opc.h (optable): Declare as const.
+ * z8k-opc.h (z8k_table): Declare as const.
+
+
+ * tic4x-dis.c: Added support for enhanced and special insn.
+ (c4x_print_op): Added insn class 'i' and 'j'
+ (c4x_hash_opcode_special): Add to support special insn
+ (c4x_hash_opcode): Update to support the new opcode-list
+ format. Add support for the new special insns.
+ (c4x_disassemble): New opcode-list support.
+
+
+ * m88k-dis.c: Include libiberty.h (for xmalloc).
+ (HASHTAB): New type, used to build instruction hash tables.
+ Contains a pointer to an INSTAB and a pointer to the next hash
+ chain entry.
+ (instructions): Move definition from m88k.h; remove initialization
+ of 'next' field.
+ (hashtable): Now an aray of pointer-to-HASHTAB, not INSTAB.
+ (printop): Mark pointer to OPSPEC as const.
+ (install): Remove; fold into init_disasm.
+ (m88kdis): Update to ihashtab_initialized to 1 after calling
+ init_disasm. entry_ptr now iterates through HASHTABs, not
+ INSTABs.
+ (init_disasm): Iterate through the instructions and add to
+ hashtable[].
+
+
+ * tic4x-dis.c: (c4x_print_op): Add support for the new argument
+ format. Fix bug in 'N' register printer.
+
+
+ * ppc-dis.c (print_insn_powerpc): Correct condition register display.
+
+
+ * ppc-opc.c (EVUIMM_4): Change bit size to 32.
+ (EVUIMM_2): Same.
+ (EVUIMM_8): Same.
+
+
+ * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir'
+ argument to ia64-gen.
+ Regenerate dependencies for ia64-len.lo.
+ * Makefile.in: Regenerate.
+ * ia64-gen.c: Convert to use getopt(). Add the standard GNU
+ options, as well as '--srcdir', which controls the directory in
+ which ia64-gen looks for the sources it uses to generate the
+ output table. Add a 'const' to the declaration of the final
+ output table. Call xmalloc_set_program_name to set the program
+ name.
+ * ia64-asmtab.c: Regenerate.
+
+
+ * ia64-gen.c: Fix comment formatting and compile time warnings.
+ * ia64-opc-a.c: Fix compile time warnings.
+ * ia64-opc-b.c: Likewise.
+ * ia64-opc-d.c: Likewise.
+ * ia64-opc-f.c: Likewise.
+ * ia64-opc-i.c: Likewise.
+ * ia64-opc-m.c: Likewise.
+ * ia64-opc-x.c: Likewise.
+
+
+ * opcodes/ppc-opc.c: Change RD to RS for evmerge*.
+
+
+ * sparc-opc.c (sparc_opcodes) <fb, fba, fbe, fbz, fbg, fbge,
+ fbl, fble, fblg, fbn, fbne, fbnz, fbo, fbu, fbue, fbug, fbuge,
+ fbul, fbule>: Add conditional/unconditional branch
+ classification.
+
+
+ * m68hc11-dis.c (print_insn): Treat bitmask and branch operands
+ at the end.
+
+
+ * mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'.
+ (mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400
+ and bfd_mach_mips5500.
+ * mips-opc.c (V1): Include INSN_4111 and INSN_4120.
+ (N411, N412, N5, N54, N55): New convenience defines.
+ (mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes.
+ Change dmadd16 and madd16 from V1 to N411.
+
+
+ * mips-dis.c (print_insn_mips): Always allow disassembly of
+ 32-bit jalx opcode.
+
+
+ * po/de.po: Updated German translation.
+
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+
+ * ppc-opc.c (CRFD, CRFS): Add PPC_OPERAND_CR flag so that cr
+ register names are accepted.
+
* tic4x-dis.c: Add function declarations and ATTRIBUTE_UNUSED.
* ppc-opc.c (MFDEC2): Include Book-E.
- (PPCCHLK64): New opcode mask.
- (evsubw, evsubiw, evmr, evnot, isellt, iselgt, iseleq, mfpid,
- mfcsrr0, mfcsrr1, mfdear, mfesr, mfivpr, mfusprg0, mftbl,
- mftbu, mfpir, mfdbsr, mfdbcr0, mfdbcr1, mfdbcr2, mfiac1,
- mfiac2, mfiac3, mfiac4, mfdac1, mfdac2, mfdvc1, mfdvc2, mftsr,
- mftcr, mfivor0, mfivor1, mfivor2, mfivor3, mfivor4, mfivor5,
- mfivor6, mfivor7, mfivor8, mfivor9, mfivor10, mfivor11,
- mfivor12, mfivor13, mfivor14, mfivor15, mfbbear, mfmcsrr0,
- mfmcsrr1, mfmcsr, mtpid, mtdecar, mtcsrr0, mtcsrr1, mtdear,
- mtesr, mtivpr, mtusprg0, mtsprg4, mtsprg5, mtsprg6, mtsprg7,
- mtdbsr, mtdbcr0, mtdbcr1, mtdbcr2, mtiac1, mtiac2, mtiac3,
- mtiac4, mtdac1, mtdac2, mtdvc1, mtdvc2, mttsr, mttcr, mtivor0,
- mtivor1, mtivor2, mtivor3, mtivor4, mtivor5, mtivor6, mtivor7,
- mtivor8, mtivor9, mtivor10, mtivor11, mtivor12, mtivor13,
- mtivor14, mtivor15, mtbbear, mtmcsrr0, mtmcsrr1, mtmcsr): New
- Book-E instructions.
- (evfsneg): Fix opcode value.
- (dcbtstlse, dcbtlse, icblce, dcblce, icbtsle): Use PPCCHLK64
- mask.
- (mcrxr64, tlbivaxe, tlbsxe, tlbsxe.): Restrict to 64-bit
- Book-E.
- (extsw): Restrict to 64-bit PPC instruction sets.
- (extsw.): Does not exist in 64-bit Book-E.
- (powerpc_macro): Remove mftbl, mftbu and mftb Book-E macros as
- they are no longer needed.
+ (PPCCHLK64): New opcode mask.
+ (evsubw, evsubiw, evmr, evnot, isellt, iselgt, iseleq, mfpid,
+ mfcsrr0, mfcsrr1, mfdear, mfesr, mfivpr, mfusprg0, mftbl,
+ mftbu, mfpir, mfdbsr, mfdbcr0, mfdbcr1, mfdbcr2, mfiac1,
+ mfiac2, mfiac3, mfiac4, mfdac1, mfdac2, mfdvc1, mfdvc2, mftsr,
+ mftcr, mfivor0, mfivor1, mfivor2, mfivor3, mfivor4, mfivor5,
+ mfivor6, mfivor7, mfivor8, mfivor9, mfivor10, mfivor11,
+ mfivor12, mfivor13, mfivor14, mfivor15, mfbbear, mfmcsrr0,
+ mfmcsrr1, mfmcsr, mtpid, mtdecar, mtcsrr0, mtcsrr1, mtdear,
+ mtesr, mtivpr, mtusprg0, mtsprg4, mtsprg5, mtsprg6, mtsprg7,
+ mtdbsr, mtdbcr0, mtdbcr1, mtdbcr2, mtiac1, mtiac2, mtiac3,
+ mtiac4, mtdac1, mtdac2, mtdvc1, mtdvc2, mttsr, mttcr, mtivor0,
+ mtivor1, mtivor2, mtivor3, mtivor4, mtivor5, mtivor6, mtivor7,
+ mtivor8, mtivor9, mtivor10, mtivor11, mtivor12, mtivor13,
+ mtivor14, mtivor15, mtbbear, mtmcsrr0, mtmcsrr1, mtmcsr): New
+ Book-E instructions.
+ (evfsneg): Fix opcode value.
+ (dcbtstlse, dcbtlse, icblce, dcblce, icbtsle): Use PPCCHLK64
+ mask.
+ (mcrxr64, tlbivaxe, tlbsxe, tlbsxe.): Restrict to 64-bit
+ Book-E.
+ (extsw): Restrict to 64-bit PPC instruction sets.
+ (extsw.): Does not exist in 64-bit Book-E.
+ (powerpc_macro): Remove mftbl, mftbu and mftb Book-E macros as
+ they are no longer needed.
* disassemble.c (disassembler_usage): Add invocation of
print_ppc_disassembler_options.
- * ppc-dis.c (print_ppc_disassembler_options): New function.
+ * ppc-dis.c (print_ppc_disassembler_options): New function.
* z8kgen.c (opt): Fix definition of "in rd,imm16" opcode.
* z8k-opc.h: Regenerated with new z8kgen.c.
* ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and
`-mefs'. Turn off AltiVec for E500 and efs.
(efsabs, efsnabs, efsneg, efsadd, efssub, efsmul,
efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt,
efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf,
- efsctui, efsctsi, efsctsiz, efsctuf, efsctsf,
+ efsctui, efsctsi, efsctsiz, efsctuf, efsctsf,
evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb,
evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor,
evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi,
* mips-opc.c: Clean up a few whitespace issues, and sort a
few entries understanding that 'x' follows 'w' in the alphabet.
-
+
* mips-opc.c: Add support for SB-1 MDMX subset and extensions.
* po/POTFILES.in: Regenerate.
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
- (mips_isa_type): Add MDMX instructions to the ISA
+ (mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* d10v-opc.c (d10v_opcodes): `btsti' does not modify its
- arguments.
+ arguments.
- * cgen-dis.in: (print_insn_@arch@): Cache list of opened CPUs rather
+ * cgen-dis.in: (print_insn_@arch@): Cache list of opened CPUs rather
than just most-recently-opened.
* Makefile.am: Tidy up sh64 rules.
- * Makefile.in: Regenerate.
+ * Makefile.in: Regenerate.
* cgen-asm.in (parse_insn_normal): Change call from
- @arch@_cgen_parse_operand to cd->parse_operand, to
+ @arch@_cgen_parse_operand to cd->parse_operand, to
facilitate CGEN_ASM_INIT_HOOK doing useful work.
-
+
* sparc-dis.c (print_insn_sparc): Make sure 0xFFFFFFFF is not
* cgen-asm.in: Include safe-ctype.h in preference to
ctype.h. Fix formatting. Use ISSPACE instead of isspace and
TOLOWER instead of tolower.
- (@arch@_cgen_build_insn_regex): Remove duplication of syntax
+ (@arch@_cgen_build_insn_regex): Remove duplication of syntax
string elements in constructed regular expression.
* fr30-asm.c: Regenerate.
* fr30-desc.c: Regenerate.
* sh-opc.h: Fix encoding of least significant nibble of the
DSP single data transfer instructions.
- * sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP
+ * sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP
instructions.
C files.
* cgen-dis.in: The same.
* cgen-ibld.in: The same.
- * fr30-asm.c: Regenerate.
- * fr30-desc.c: Regenerate.
- * fr30-dis.c: Regenerate.
- * fr30-ibld.c: Regenerate.
- * fr30-opc.c: Regenerate.
- * m32r-asm.c: Regenerate.
- * m32r-desc.c: Regenerate.
- * m32r-dis.c: Regenerate.
- * m32r-ibld.c: Regenerate.
- * m32r-opc.c: Regenerate.
- * m32r-opinst.c Regenerate.
- * openrisc-asm.c: Regenerate.
- * openrisc-desc.c: Regenerate.
- * openrisc-dis.c: Regenerate.
- * openrisc-ibld.c: Regenerate.
- * openrisc-opc.c: Regenerate.
- * openrisc-opc.h: Regenerate.
+ * fr30-asm.c: Regenerate.
+ * fr30-desc.c: Regenerate.
+ * fr30-dis.c: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * fr30-opc.c: Regenerate.
+ * m32r-asm.c: Regenerate.
+ * m32r-desc.c: Regenerate.
+ * m32r-dis.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * m32r-opc.c: Regenerate.
+ * m32r-opinst.c Regenerate.
+ * openrisc-asm.c: Regenerate.
+ * openrisc-desc.c: Regenerate.
+ * openrisc-dis.c: Regenerate.
+ * openrisc-ibld.c: Regenerate.
+ * openrisc-opc.c: Regenerate.
+ * openrisc-opc.h: Regenerate.
* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
* po/opcodes.pot: Regenerate.
- * arm-opc.h (arm_opcodes): Add cirrus insns.
+ * arm-opc.h (arm_opcodes): Add cirrus insns.
* arm-dis.c (print_insn_arm): Add 'I' case.
- * cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits
- calls to cgen_get_insn_value and cgen_put_insn_value calls.
- (extract_1): Switched bfd_get_bits call to cgen_get_insn_value call.
+ * cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits
+ calls to cgen_get_insn_value and cgen_put_insn_value calls.
+ (extract_1): Switched bfd_get_bits call to cgen_get_insn_value call.
- * cgen-asm.in: Include "xregex.h" always to enable the libiberty
- regex support.
- (@arch@_cgen_build_insn_regex): New routine from Graydon.
- (@arch@_cgen_assemble_insn): Add Graydon's code to use regex
+ * cgen-asm.in: Include "xregex.h" always to enable the libiberty
+ regex support.
+ (@arch@_cgen_build_insn_regex): New routine from Graydon.
+ (@arch@_cgen_assemble_insn): Add Graydon's code to use regex
to verify if it is worth parsing the insn as insn "x". Also update
error message when insn is not a recognized format of the insn vs
when the insn is completely unrecognized.
- * z8k-dis.c: Fix formatting.
- (unpack_instr): Remove unused cases in switch statement. Add
- safety abort() in default case.
- (unparse_instr): Add safety abort() in default case.
+ * z8k-dis.c: Fix formatting.
+ (unpack_instr): Remove unused cases in switch statement. Add
+ safety abort() in default case.
+ (unparse_instr): Add safety abort() in default case.
- * Makefile.am: Add OpenRISC target.
- * Makefile.in: Regenerated.
+ * Makefile.am: Add OpenRISC target.
+ * Makefile.in: Regenerated.
- * disassemble.c (disassembler): Recognize the OpenRISC disassembly.
+ * disassemble.c (disassembler): Recognize the OpenRISC disassembly.
- * configure.in (bfd_openrisc_arch): Add target.
- * configure: Regenerated.
+ * configure.in (bfd_openrisc_arch): Add target.
+ * configure: Regenerated.
- * openrisc-asm.c: New file.
- * openrisc-desc.c: Likewise.
- * openrisc-desc.h: Likewise.
- * openrisc-dis.c: Likewise.
- * openrisc-ibld.c: Likewise.
- * openrisc-opc.c: Likewise.
- * openrisc-opc.h: Likewise.
+ * openrisc-asm.c: New file.
+ * openrisc-desc.c: Likewise.
+ * openrisc-desc.h: Likewise.
+ * openrisc-dis.c: Likewise.
+ * openrisc-ibld.c: Likewise.
+ * openrisc-opc.c: Likewise.
+ * openrisc-opc.h: Likewise.
- * cgen-dis.in (print_insn_@arch@): Add support for target machine
- determination via CGEN_COMPUTE_MACH.
+ * cgen-dis.in (print_insn_@arch@): Add support for target machine
+ determination via CGEN_COMPUTE_MACH.
* fr30-desc.c: Regenerate.
* fr30-dis.c: Regenerate.
* fr30-opc.h: Regenerate.
* arm-dis.c (print_insn_thumb): Compute destination address
- of BLX(1) instruction by taking bit 1 from PC and not from bit
- 0 of the offset.
+ of BLX(1) instruction by taking bit 1 from PC and not from bit
+ 0 of the offset.
- * Makefile.am: Add PDP-11 target.
- * configure.in: Likewise.
- * disassemble.c: Likewise.
- * pdp11-dis.c: New file.
- * pdp11-opc.c: New file.
+ * Makefile.am: Add PDP-11 target.
+ * configure.in: Likewise.
+ * disassemble.c: Likewise.
+ * pdp11-dis.c: New file.
+ * pdp11-opc.c: New file.
- * mips-dis.c (print_insn_arg): Use top four bits of the address of
+ * mips-dis.c (print_insn_arg): Use top four bits of the address of
the following instruction not of the jump itself for the jump
target.
(print_mips16_insn_arg): Likewise.
- * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO,
- MOD_HILO, and MOD_LO macros.
+ * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO,
+ MOD_HILO, and MOD_LO macros.
- * mips-opc.c (M1, M2): Delete.
- (mips_builtin_opcodes): Remove all uses of M1.
+ * mips-opc.c (M1, M2): Delete.
+ (mips_builtin_opcodes): Remove all uses of M1.
- * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2
- instructions take "G" format second operands and use the
- correct flags.
- There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to
+ * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2
+ instructions take "G" format second operands and use the
+ correct flags.
+ There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to
match.
- Delete "sel" code operands from mfc1 and mtc1.
- Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants
+ Delete "sel" code operands from mfc1 and mtc1.
+ Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants
for dm[ft]c[023].
- * mips-opc.c (mips_builtin_opcodes): Finish additions
- for MIPS32 support, and clean up existing entries for
- aesthetics, consistency with the MIPS32 ISA, and
- with consistency the rest of the table.
+ * mips-opc.c (mips_builtin_opcodes): Finish additions
+ for MIPS32 support, and clean up existing entries for
+ aesthetics, consistency with the MIPS32 ISA, and
+ with consistency the rest of the table.
- mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument
- specifiers. Update 'B' for new constant names, and remove
- 'm'.
- mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop"
- near the top of the array, so they are disassembled properly.
- Enable "ssnop" for MIPS32. Add "break" variant with 20 bit
- code for MIPS32. Update "clo" and "clz" to use 'U' operand
- specifier. Add 'H' format specifier variants for "mfc1,"
- "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update
- MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32
- "wait" variant which uses 'J' operand specifier.
-
- * mips-dis.c (set_mips_isa_type): Update to use
- CPU_UNKNOWN and ISA_* constants. Add bfd_mach_mips32 case.
- Replace bfd_mach_mips4K with bfd_mach_mips32_4k case.
- * mips-opc.c (I32): New constant for instructions added in
- MIPS32.
- (P4): Delete.
- (mips_builtin_opcodes) Replace all uses of P4 with I32.
-
- * mips-dis.c (set_mips_isa_type): Add cases for
- bfd_mach_mips5 and bfd_mach_mips64.
- * mips-opc.c (I64): New definitions.
-
- * mips-dis.c (set_mips_isa_type): Add case for
- bfd_mach_mips_sb1.
+ mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument
+ specifiers. Update 'B' for new constant names, and remove
+ 'm'.
+ mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop"
+ near the top of the array, so they are disassembled properly.
+ Enable "ssnop" for MIPS32. Add "break" variant with 20 bit
+ code for MIPS32. Update "clo" and "clz" to use 'U' operand
+ specifier. Add 'H' format specifier variants for "mfc1,"
+ "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update
+ MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32
+ "wait" variant which uses 'J' operand specifier.
+
+ * mips-dis.c (set_mips_isa_type): Update to use
+ CPU_UNKNOWN and ISA_* constants. Add bfd_mach_mips32 case.
+ Replace bfd_mach_mips4K with bfd_mach_mips32_4k case.
+ * mips-opc.c (I32): New constant for instructions added in
+ MIPS32.
+ (P4): Delete.
+ (mips_builtin_opcodes) Replace all uses of P4 with I32.
+
+ * mips-dis.c (set_mips_isa_type): Add cases for
+ bfd_mach_mips5 and bfd_mach_mips64.
+ * mips-opc.c (I64): New definitions.
+
+ * mips-dis.c (set_mips_isa_type): Add case for
+ bfd_mach_mips_sb1.
- * d30v-opc.c (d30v_format_tab): Use format Ra for
- modinc and moddec.
+ * d30v-opc.c (d30v_format_tab): Use format Ra for
+ modinc and moddec.
projects / binutils.git / blobdiff