- * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
+ * rx-decode.opc (MOV): Do not sign-extend immediates which are
+ already the maximum bit size.
+ * rx-decode.c: Regenerate.
- * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
- Use branch types instead.
- (print_insn): Likewise.
+ * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
+ * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
+ * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
+ * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
- * mips-opc.c (mips_builtin_opcodes): Correct register use
- annotation of "alnv.ps".
+ * sparc-opc.c (CBCOND): New define.
+ (CBCOND_XCC): Likewise.
+ (cbcond): New helper macro.
+ (sparc_opcodes): Add compare-and-branch instructions.
+ * sparc-dis.c (print_insn_sparc): Handle ')'.
+ * sparc-opc.c (sparc_opcodes): Add crypto instructions.
- * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
+ * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
+ into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
- * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
+ * sparc-dis.c (X_DISP10): Define.
+ (print_insn_sparc): Handle '='.
- * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
+ * bfin-dis.c (fmtconst): Replace decimal handling with a single
+ sprintf call and the '*' field width.
- * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
- a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
- av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
- exception, end_of_registers, msize, memory, bfd_mach.
- (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
- LB0REG, LC1REG, LT1REG, LB1REG): Delete
- (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
- (get_allreg): Change to new defines. Fallback to abort().
+ * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
- * bfin-dis.c: Add whitespace/parenthesis where needed.
-
-
- * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
- than 7.
-
-
- * configure: Regenerate.
-
-
- * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
-
-
- * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
- dregs only when P is set, and dregs_lo otherwise.
-
-
- * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
-
-
- * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
-
-
- * bfin-dis.c (machine_registers): Delete REG_GP.
- (reg_names): Delete "GP".
- (decode_allregs): Change REG_GP to REG_LASTREG.
-
-
- * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
- M_IH, M_IU): Delete.
-
-
- * bfin-dis.c (reg_names): Add const.
- (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
- decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
- decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
- decode_counters, decode_allregs): Likewise.
-
-
- * i386-dis.c (OP_J): Parenthesize expression to prevent
- truncated addresses.
- (print_insn): Fix indentation off-by-one.
-
-
- * po/da.po: Updated Danish translation.
-
-
- * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
-
-
- * i386-dis.c (sIbT): New.
- (b_T_mode): Likewise.
- (dis386): Replace sIb with sIbT on "pushT".
- (x86_64_table): Replace sIb with Ib on "aam" and "aad".
- (OP_sI): Handle b_T_mode. Properly sign-extend byte.
-
+ * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
+ (powerpc_opcd_indices): Bump array size.
+ (disassemble_init_powerpc): Set powerpc_opcd_indices entries
+ corresponding to unused opcodes to following entry.
+ (lookup_powerpc): New function, extracted and optimised from..
+ (print_insn_powerpc): ..here.
+
+ * disassemble.c (disassemble_init_for_target): Handle ppc init.
+ * ppc-dis.c (private): New var.
+ (powerpc_init_dialect): Don't return calloc failure, instead use
+ private.
+ (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
+ (powerpc_opcd_indices): New array.
+ (disassemble_init_powerpc): New function.
+ (print_insn_big_powerpc): Don't init dialect here.
+ (print_insn_little_powerpc): Likewise.
+ (print_insn_powerpc): Start search using powerpc_opcd_indices.
+
+
+ * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
+ * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
+ (PPCVEC2, PPCTMR, E6500): New short names.
+ (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
+ mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
+ lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
+ lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
+ lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
+ optional operands on sync instruction for E6500 target.
+
+
+ * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
+
+
+ * mt-dis.c: Regenerate.
+
+
+ * v850-opc.c (extract_v8): Rearrange to make it obvious this
+ is the inverse of corresponding insert function.
+ (extract_d22, extract_u9, extract_r4): Likewise.
+ (extract_d9): Correct sign extension.
+ (extract_d16_15): Don't assume "long" is 32 bits, and don't
+ rely on implementation defined behaviour for shift right of
+ signed types.
+ (extract_d16_16, extract_d17_16, extract_i9): Likewise.
+ (extract_d23): Likewise, and correct mask.
+
+
+ * crx-dis.c (print_arg): Mask constant to 32 bits.
+ * crx-opc.c (cst4_map): Use int array.
+
+
+ * arc-dis.c (BITS): Don't use shifts to mask off bits.
+ (FIELDD): Sign extend with xor,sub.
+
+
+ * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
+ * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
+ TILEPRO_OPC_LW_TLS_SN.
+
+
+ * i386-opc.h (HLEPrefixNone): New.
+ (HLEPrefixLock): Likewise.
+ (HLEPrefixAny): Likewise.
+ (HLEPrefixRelease): Likewise.
+
+
+ * i386-dis.c (HLE_Fixup1): New.
+ (HLE_Fixup2): Likewise.
+ (HLE_Fixup3): Likewise.
+ (Ebh1): Likewise.
+ (Evh1): Likewise.
+ (Ebh2): Likewise.
+ (Evh2): Likewise.
+ (Ebh3): Likewise.
+ (Evh3): Likewise.
+ (MOD_C6_REG_7): Likewise.
+ (MOD_C7_REG_7): Likewise.
+ (RM_C6_REG_7): Likewise.
+ (RM_C7_REG_7): Likewise.
+ (XACQUIRE_PREFIX): Likewise.
+ (XRELEASE_PREFIX): Likewise.
+ (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
+ cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
+ Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
+ (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
+ not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
+ MOD_C6_REG_7 and MOD_C7_REG_7.
+ (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
+ (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
+ xtest.
+ (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
+ (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
+
+ * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
+ CPU_RTM_FLAGS.
+ (cpu_flags): Add CpuHLE and CpuRTM.
+ (opcode_modifiers): Add HLEPrefixOk.
+
+ * i386-opc.h (CpuHLE): New.
+ (CpuRTM): Likewise.
+ (HLEPrefixOk): Likewise.
+ (i386_cpu_flags): Add cpuhle and cpurtm.
+ (i386_opcode_modifier): Add hleprefixok.
+
+ * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
+ add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
+ sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
+ operand. Add xacquire, xrelease, xabort, xbegin, xend and
+ xtest.
* i386-init.h: Regenerated.
- * i386-tbl.h: Regenerated
-
-
- * i386-dis.c (REG_XOP_TBM_01): New.
- (REG_XOP_TBM_02): New.
- (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
- (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
- entries, and add bextr instruction.
-
- * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
- (cpu_flags): Add CpuTBM.
-
- * i386-opc.h (CpuTBM) New.
- (i386_cpu_flags): Add bit cputbm.
-
- * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
- blcs, blsfill, blsic, t1mskc, and tzmsk.
-
-
- * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
+ * i386-tbl.h: Likewise.
-2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
+2012-01-24 DJ Delorie <dj@redhat.com>
- * mips-dis.c (print_insn_args): Adjust the value to print the real
- offset for "+c" argument.
+ * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
+ * rl78-decode.c: Regenerate.
- * po/da.po: Updated Danish translation.
+ PR binutils/10173
+ * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
- * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
+ * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
+ register and move them after pmove with PSR/PCSR register.
- * i386-dis.c (REG_VEX_38F3): New.
- (PREFIX_0FBC): Likewise.
- (PREFIX_VEX_38F2): Likewise.
- (PREFIX_VEX_38F3_REG_1): Likewise.
- (PREFIX_VEX_38F3_REG_2): Likewise.
- (PREFIX_VEX_38F3_REG_3): Likewise.
- (PREFIX_VEX_38F7): Likewise.
- (VEX_LEN_38F2_P_0): Likewise.
- (VEX_LEN_38F3_R_1_P_0): Likewise.
- (VEX_LEN_38F3_R_2_P_0): Likewise.
- (VEX_LEN_38F3_R_3_P_0): Likewise.
- (VEX_LEN_38F7_P_0): Likewise.
- (dis386_twobyte): Use PREFIX_0FBC.
- (reg_table): Add REG_VEX_38F3.
- (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
- PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
- PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
- (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
- PREFIX_VEX_38F7.
- (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
- VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
- VEX_LEN_38F7_P_0.
+ * i386-dis.c (mod_table): Add vmfunc.
- * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
- (cpu_flags): Add CpuBMI.
+ * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
+ (cpu_flags): CpuVMFUNC.
- * i386-opc.h (CpuBMI): New.
- (i386_cpu_flags): Add cpubmi.
+ * i386-opc.h (CpuVMFUNC): New.
+ (i386_cpu_flags): Add cpuvmfunc.
- * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
+ * i386-opc.tbl: Add vmfunc.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
-
- * i386-dis.c (VexGdq): New.
- (OP_VEX): Handle dq_mode.
-
-
- * i386-gen.c (process_copyright): Update copyright to 2011.
-
-For older changes see ChangeLog-2010
+For older changes see ChangeLog-2011
\f
Local Variables:
mode: change-log
projects / binutils.git / blobdiff