+
+ PR gas/11356
+ * listing.c (listing_newline): Correct backslash quote logic.
+
+
+ * config/tc-i386.h [TE_SOLARIS] (ELF_TARGET_FORMAT): Define.
+ (ELF_TARGET_FORMAT64): Define.
+
+
+ * config/tc-arm.c (arm_cpu_option_table): Add cortex-m4.
+
+
+ * config/tc-sh.c (get_specific): Move overflow checking code to avoid
+ reading uninitialized data.
+
+
+ * config/tc-score7.c (s7_frag_check): Add ATTRIBUTE_UNUSED.
+
+
+ * configure.tgt: Fix mep cpu case.
+
+
+ * config/tc-arm.c (do_t_strexd): Remove
+ operand[1] != operand[2] contraint.
+
+
+ * config/tc-arm.c (neon_select_shape): No need to match
+ the remaining operands in the shape when one operand does
+ not match.
+
+
+ * config/tc-arm.c (do_neon_ld_st_interleave): Reject bad
+ alignment.
+
+
+ * cgen.c: Whitespace fixes.
+ (weak_operand_overflow_check): Formatting fix.
+
+
+ * config/tc-i386.c (match_template): Update error messages.
+
+
+ * config/tc-i386.c (_i386_insn): Add err_msg.
+ (operand_size_match): Set err_msg on failure.
+ (operand_type_match): Likewise.
+ (operand_type_register_match): Likewise.
+ (VEX_check_operands): Likewise.
+ (match_template): Likewise. Use i.err_msg with as_bad.
+
+
+ * config/tc-mips.c (mips_fix_loongson2f, mips_fix_loongson2f_nop,
+ mips_fix_loongson2f_jump): New variables.
+ (md_longopts): Add New options -mfix-loongson2f-nop/jump,
+ -mno-fix-loongson2f-nop/jump.
+ (md_parse_option): Initialize variables via above options.
+ (options): New enums for the above options.
+ (md_begin): Initialize nop_insn from LOONGSON2F_NOP_INSN.
+ (fix_loongson2f, fix_loongson2f_nop, fix_loongson2f_jump):
+ New functions.
+ (append_insn): call fix_loongson2f().
+ (mips_handle_align): Replace the implicit nops.
+ * config/tc-mips.h (MAX_MEM_FOR_RS_ALIGN_CODE): Modified
+ for the new mips_handle_align().
+ * doc/c-mips.texi: Document the new options.
+
+
+ * config/tc-arm.c (do_rd_rm_rn): Added warning
+ for obsolete insns.
+
+
+ PR binutils/11297
+ * config/tc-avr.c (md_apply_fix): Handle BFD_RELOC_8.
+ (avr_cons_fix_new): Handle fixups of a single byte.
+
+
+ PR 9861
+ * config/tc-arm.c (CPU_DEFAULT): Do not define based upon build
+ compiler's predefines.
+
+
+ * configure.tgt: Whiltespace. Sort moxie entry.
+
+
+ * config/tc-arm.c (arm_convert_symbolic_attribute): Add Tag_DIV_use.
+ * doc/c-arm.texi: Likewise.
+
+
+ * config/tc-arm.c (asm_opcode): operands type
+ change.
+ (BAD_PC_ADDRESSING): New macro message.
+ (BAD_PC_WRITEBACK): Likewise.
+ (MIX_ARM_THUMB_OPERANDS): New macro.
+ (operand_parse_code): Added enum values.
+ (parse_operands): Added thumb/arm distinction,
+ plus new enum values handling.
+ (encode_arm_addr_mode_2): Validations enhanced.
+ (encode_arm_addr_mode_3): Likewise.
+ (do_rm_rd_rn): Likewise.
+ (encode_thumb32_addr_mode): Likewise.
+ (do_t_ldrex): Likewise.
+ (do_t_ldst): Likewise.
+ (do_t_strex): Likewise.
+ (md_assemble): Call parse_operands with
+ a new parameter.
+ (OPS_1): New macro.
+ (OPS_2): Likewise.
+ (OPS_3): Likewise.
+ (OPS_4): Likewise.
+ (OPS_5): Likewise.
+ (OPS_6): Likewise.
+ (insns): Updated insns operands.
+
+
+ * config/tc-ia64.c (enum reloc_func): Add FUNC_SLOTCOUNT_RELOC.
+ (DUMMY_RELOC_IA64_SLOTCOUNT): Added.
+ (pseudo_func): Add an entry for slotcount.
+ (md_begin): Initialize slotcount pseudo symbol.
+ (ia64_parse_name): Handle @slotcount parameter.
+ (ia64_gen_real_reloc_type): Handle slotcount.
+ (md_apply_fix): Ditto.
+ * doc/c-ia64.texi (IA-64-Relocs): Document @slotcount.
+
+
+ * config/tc-xtensa.c (istack_init): Don't call memset.
+
+
+ * config/tc-xtensa.c (cache_literal_section): Handle prefixes as
+ well as suffixes.
+
+
+ * config/tc-xtensa.c (xtensa_find_unaligned_loops): Rewrite.
+
+
+ * config/tc-i386.c (build_modrm_byte): Reformat.
+
+
+ * config/tc-i386.c: Update copyright.
+
+
+ * config/tc-i386.c (vec_imm4) New operand type.
+ (fits_in_imm4): New.
+ (VEX_check_operands): New.
+ (check_reverse): Call VEX_check_operands.
+ (build_modrm_byte): Reintroduce code for 5
+ operand insns. Fix whitespace.
+
+
+ * config/tc-ppc.c (md_show_usage): Add -mpwr4, -mpwr5, -mpwr5x,
+ -mpwr6 and -mpwr7.
+
+
+ * config/tc-xtensa.c (RELAXED_LOOP_INSN_BYTES): New.
+ (next_frag_pre_opcode_bytes): Use RELAXED_LOOP_INSN_BYTES.
+ (xtensa_mark_zcl_first_insns): Rewrite to handle corner case.
+
+
+ * config/tc-arm.c (md_pcrel_from_section): Keep base to zero for
+ non-local branches (BFD_RELOC_THUMB_PCREL_BRANCH23,
+ BFD_RELOC_THUMB_PCREL_BLX, BFD_RELOC_ARM_PCREL_BLX,
+ BFD_RELOC_ARM_PCREL_CALL)
+
+
+ * config/tc-xtensa.c (frag_format_size): Generalize logic to
+ handle more instruction sizes and fetch widths.
+ (branch_align_power): Likewise.
+ (text_align_power): Likewise.
+ (bytes_to_stretch): Likewise.
+
+
+ * config/tc-ppc.c (md_show_usage): Mention -mtitan. Don't use tabs.
+ (ppc_mach): Handle titan.
+ * doc/c-ppc.texi: Mention -mtitan.
+
+
+ * config/tc-xtensa.c (UNREACHABLE_MAX_WIDTH): Delete and
+ replace with...
+ (xtensa_fetch_width) ...this.
+
+
+ * Makefile.am (CPU_TYPES, OBJ_FORMATS, CPU_OBJ_VALID,
+ MULTI_CPU_TYPES, MULTI_CPU_OBJ_VALID): Remove.
+ * Makefile.in: Regenerate.
+
+
+ * config/tc-i386.c (cpu_arch): Change amdfam15 to bdver1.
+ (i386_align_code): Rename PROCESSOR_AMDFAM15 to PROCESSOR_BDVER1.
+ * config/tc-i386.h (processor_type): Same.
+ * doc/c-i386.texi: Change amdfam15 to bdver1.
+
+
+ PR 11136
+ * config/tc-arm.c (neon_check_type): Handle a neon_shape value of
+ NS_NULL.
+
* NEWS: Mention new feature.
Include obj-format.h earlier.
-
+
* config/tc-s390.c (s390_elf_final_processing): New function.
* config/tc-s390.h (elf_tc_final_processing): New macro definition.
(s390_elf_final_processing): Added prototype.
projects / binutils.git / blobdiff