+
+ * config/tc-i386.c (check_string): Use register_prefix for error
+ message.
+ (process_operands): Likewise.
+
+
+ * c-arm.texi: Add tutorial on ARM unwinding pseudo ops.
+
+
+ * config/bfin-parse.y (check_macfunc_option): Fix instruction
+ mode checking.
+ (asm_1): Check mode for 16-bit multiply instructions.
+
+
+ * configure.in: Update a number of obsolete autoconf macros.
+ * configure: Regenerate.
+ * aclocal.m4: Regenerate.
+
+
+ * config/tc-mcore.c (md_assemble): Increase length of name array
+ to include terminating NUL.
+
+
+ * config/bfin-lex.l (NUMBER): Protect special `.'.
+
+
+ * symbols.c (symbol_clone): Ensure clones are not external.
+
+
+ * config/tc-hppa.c (md_begin): Set BSF_KEEP for "dummy_symbol".
+
+
+ * dw2gencfi.c (DWARF2_FDE_RELOC_SIZE): New.
+ (output_cie, output_fde): Use it.
+ (DWARF2_EH_FRAME_READ_ONLY): New.
+ (cfi_finish): Use it.
+
+ * config/tc-hppa.h (DWARF2_FDE_RELOC_SIZE): Set to 8 for 64-bit.
+ (DWARF2_CIE_DATA_ALIGNMENT): Change sign.
+ (DWARF2_EH_FRAME_READ_ONLY): New.
+ * config/tc-hppa.c (tc_gen_reloc): Generate pc-relative relocations
+ from the results of DIFF_EXPR_OK manipulation.
+
+
+ * config/xtensa-istack.h (MAX_INSN_ARGS): Increase to 64.
+
+
+ * config/tc-xtensa.c (O_tlsfunc, O_tlsarg, O_tlscall): Define.
+ (O_tpoff, O_dtpoff): Define.
+ (suffix_relocs): Add entries for TLS suffixes.
+ (xtensa_elf_cons): Check for invalid use of TLS relocations.
+ (map_operator_to_reloc): Add is_literal parameter and use it to
+ control translating TLS instruction relocations to the corresponding
+ literal relocations.
+ (xg_valid_literal_expression): Allow TLS operators.
+ (xg_build_to_insn): Copy TLS operators from pseudo-instruction
+ operands to generated literals.
+ (xg_assemble_literal): Handle TLS operators. Update call to
+ map_operator_to_reloc.
+ (md_assemble): Handle CALLXn.TLS pseudo-instruction.
+ (md_apply_fix): Handle TLS relocations.
+ (emit_single_op): Handle TLS operators.
+ (convert_frag_immed): Update call to map_operator_to_reloc.
+ (vinsn_to_insnbuf): Emit relocations for TLS-related instructions.
+ * config/xtensa-istack.h (tinsn_struct): Add tls_reloc field.
+ * config/xtensa-relax.c (append_literal_op): Add src_op parameter
+ to initialize the op_data field of the BuildOp.
+ (build_transition): Use it here to record the source operand
+ corresponding to a generated literal.
+ * config/xtensa-relax.h (build_op): Comment op_data use for literals.
+
+
+ AVX Programming Reference (August, 2008)
+ * config/tc-i386.c (CPU_FLAGS_AES_MATCH): New.
+ (CPU_FLAGS_AVX_MATCH): Likewise.
+ (CPU_FLAGS_32BIT_MATCH): Updated.
+ (cpu_flags_match): Likewise.
+
+
+ PR 6848
+ * write.c (install_reloc): Check that reloc symbols have been
+ written.
+ (set_symtab): Mark symbols with BSF_KEEP.
+
+
+ * config/tc-i386.c (i386_align_code): Fix a comment typo.
+
+
+ PR 6526
+ * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
+ * Makefile.in: Regenerate.
+ * aclocal.m4: Regenerate.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+ * doc/Makefile.in: Regenerate.
+
+
+ * config/tc-tic4x.c (tic4x_operands_parse): Make static.
+
+
+ * doc/as.texinfo (Align): Document the PowerPC behaviour.
+
+
+ * as.c, as.h, ecoff.c, hash.c, macro.c, symbols.c, config/obj-evax.c,
+ config/obj-som.c, config/tc-alpha.c, config/tc-arm.c, config/tc-bfin.c,
+ config/tc-bfin.h, config/tc-crx.c, config/tc-frv.c, config/tc-frv.h,
+ config/tc-hppa.h, config/tc-i386.c, config/tc-i860.c, config/tc-i960.h,
+ config/tc-ia64.c, config/tc-ia64.h, config/tc-m32c.c, config/tc-m32c.h,
+ config/tc-m68k.c, config/tc-maxq.c, config/tc-s390.c, config/tc-s390.h,
+ config/tc-sparc.c, config/tc-sparc.h, config/tc-spu.c, config/tc-spu.h,
+ config/tc-tic4x.c, config/tc-tic4x.h, config/tc-tic54x.c,
+ config/tc-tic54x.h, config/tc-vax.c, doc/internals.texi: Banish PARAMS
+ and PTR. Convert to ISO C. Delete unnecessary forward declarations.
+
+
+ * config/tc-arm.c (s_unreq): Adjust hash_delete call.
+ * config/tc-ia64.c (dot_rot): Likewise.
+
+
+ PR 6575
+ * hash.c: Expand PTR to void *.
+ (hash_delete): Add "freeme" parameter. Call obstack_free.
+ * hash.h: Expand PTR to void *.
+ (hash_delete): Update prototype.
+ * macro.c (macro_expand_body): hash_delete LOCALs from formal_hash.
+ * config/tc-tic54x.c (tic54x_remove_local_label): Update hash_delete
+ call.
+ (subsym_substitute): Likewise.
+ * doc/internals.texi (hash_delete): Update.
+
+
+ * config/tc-avr.c (mcu_types): Add avr25, avr31, avr35, and avr51
+ architectures. Reorganize list to put mcu types in correct
+ architectures and to order list same as in GCC. Use new ISA
+ definitions in include/opcode/avr.h.
+ * doc/c-avr.texi: Add avr25, avr31, avr35, and avr51 architecture
+ descriptions. Reorganize descriptions to put mcu types in correct
+ architectures and to order lists same as in GCC.
+
+
+ * config/tc-mips.c (OPTION_CALL_NONPIC): New macro.
+ (OPTION_NON_SHARED, OPTION_XGOT, OPTION_MABI, OPTION_32)
+ (OPTION_N32, OPTION_64, OPTION_MDEBUG, OPTION_NO_MDEBUG)
+ (OPTION_PDR, OPTION_NO_PDR, OPTION_MVXWORKS_PIC): Bump by 1.
+ (md_longopts): Add -call_nonpic.
+ (md_parse_option): Handle OPTION_CALL_NONPIC.
+ (md_show_usage): Add -call_nonpic.
+
+
+ * config/tc-xtensa.c (exclude_section_from_property_tables): New.
+ (xtensa_create_property_segments): Use it.
+ (xtensa_create_xproperty_segments): Likewise.
+
+
+ * doc/internals.texi (DWARF2_FORMAT): Update for 2008-08-04 change.
+
+
+ * config/tc-mips.c (mips16_reloc_p, got16_reloc_p, hi16_reloc_p)
+ (lo16_reloc_p): New functions.
+ (reloc_needs_lo_p): Use hi16_reloc_p and got16_reloc_p to
+ generalize relocation checks.
+ (matching_lo_reloc): New function.
+ (fixup_has_matching_lo_p): Use it.
+ (mips16_mark_labels): Don't clobber a symbol's visibility.
+ (append_insn): Use hi16_reloc_p and lo16_reloc_p.
+ (mips16_ip): Handle BFD_RELOC_MIPS16_GOT16 and BFD_RELOC_MIPS16_CALL16.
+ (md_apply_fix): Likewise.
+ (mips16_percent_op): Add %got and %call16.
+ (mips_frob_file): Use got16_reloc_p to generalize relocation checks.
+ Use matching_lo_reloc.
+ (mips_force_relocation): Use hi16_reloc_p and lo16_reloc_p to
+ generalize relocation checks.
+ (mips_fix_adjustable): Use lo16_reloc_p to generalize relocation
+ checks.
+
+
+ * NEWS: Mention these changes.
+
+ * config/tc-h8300.h (H_TICK_HEX): Define.
+ * config/tc-h8300.c (OPTION_H_TICK_HEX): New.
+ (md_longopts): Add "-h-tick-hex".
+ (md_parse_option): Support it.
+ * doc/c-h8300.texi (H8/300 Options): Document it.
+ * doc/as.texinfo (Overview): Likewise.
+
+ * config/tc-sh.h (H_TICK_HEX): Define.
+ * config/tc-sh.c (OPTION_H_TICK_HEX): New.
+ (md_longopts): Add "-h-tick-hex".
+ (md_parse_option): Support it.
+ * doc/c-sh.texi (SH Options): Document it.
+ * doc/c-sh64.texi (SH64 Options): Document it.
+ * doc/as.texinfo (Overview): Likewise.
+
+
+ PR gas/6656
+ * dwarf2dbg.c (dwarf2_directive_file): Disable gas generated
+ debug info if we see compiler generated debug info.
+ (dwarf2_directive_loc): Likewise. Remove redundant debug_type test.
+
+
+ * dwarf2dbg.c: Remove superfluous forward function declarations.
+ (DWARF2_FORMAT): Add section arg.
+ (out_header): New function, split out from..
+ (out_debug_line): ..here.
+ (out_debug_aranges): Use out_header.
+ (out_debug_abbrev): Add info_seg and line_seg args. Use
+ DW_FORM_data8 (for DW_AT_stmt_list) if line_seg is 64-bit.
+ (out_debug_info): Use out_header. Output 8 byte DW_AT_stmt_list
+ if line_seg is 64-bit.
+ (dwarf2_finish): Adjust out_debug_abbrev call.
+ * config/tc-mips.h (DWARF2_FORMAT, mips_dwarf2_format): Add sec arg.
+ * config/tc-mips.c (mips_dwarf2_format): Likewise.
+
+
+ * Makefile.am (POTFILES.in): Set LC_ALL=C.
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+
+ * config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags.
+ Handle -mvsx and -mpower7.
+ (md_show_usage): Document -mpower7 and -mvsx.
+ * doc/as.texinfo (Target PowerPC): Document -mvsx.
+ * doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7.
+
+
+ * config/tc-ppc.c (parse_cpu) <power6>: Accept Altivec instructions.
+ <cell>: Likewise.
+
+
+ * config/tc-ppc.c (parse_cpu): Separate handling of -m403/405.
+ (md_show_usage): Likewise.
+
+
+ * messages.c, symbols.c, write.c: Silence gcc warnings.
+
+
+ * config/tc-i386.c (operand_type_check): Warning fix.
+
+
+ * doc/as.texinfo: Add description of single-precision attribute.
+
+
+ * config/bfin-parse.y (asm_1): Error if plain symbol is used
+ as load/store offset.
+
+
+ * config/tc-mips.c (mips_ip): Reset s to argsStart.
+
+
+ * config/tc-bfin.c (bfin_gen_loop): Remove loop symbol.
+
+
+ * config/tc-h8300.c (fix_operand_size): Use the default size
+ specified by the .lbranch/.sbranch pseudos.
+
+
+ * config/tc-m32c.h (H_TICK_HEX): Define.
+ * config/tc-m32c.c (OPTION_H_TICK_HEX): Define.
+ (md_longopts): Add support for it.
+ (md_parse_option): Likewise.
+ * doc/as.texinfo (Overview): Add new m32c options.
+ * doc/c-m32c.texi (M32C-Modifiers): Likewise
+
+ * as.h: (enable_h_tick_hex): New.
+ * app.c (enable_h_tick_hex): New.
+ (LEX_IS_H): New.
+ (do_scrub_begin): Mark 'H' and 'h' as special if enable_h_tick_hex.
+ (do_scrub_chars): If enable_h_tick_hex and 'h', check for H'00
+ style hex constants and convert the input stream to 0x00 style.
+ (do_scrub_chars): If a 'X style character constant is found after
+ a symbol character (like you're or X'00), warn the user.
+
+
+ * config/tc-mips.c (mips16_mark_labels): Use ELF_ST_SET_MIPS16.
+ (mips_fix_adjustable): Likewise.
+ (mips_frob_file_after_relocs): Likewise.
+
+
+ * config/tc-m68k.c (m68k_set_cpu, m68k_set_arch): Don't complain
+ about overriding an earlier setting.
+
+
+ * config/tc-mips.c (NO_ISA_COP): New macro.
+ (COP_INSN): New macro.
+ (is_opcode_valid): Use them.
+ (macro) <ld_st>: Use them. Don't accept coprocessor load store
+ insns based on the ISA if CPU is NO_ISA_COP.
+ <copz>: Likewise for coprocessor operations.
+
+
+ * config/tc-arm.c (arm_fix_adjustable): Don't adjust MOVW/MOVT
+ relocations.
+
+
+ * configure.tgt: Add bfin-*-rtems*.
+
+
+ * config/tc-spu.c (md_apply_fix): Handle fully resolved
+ BFD_RELOC_32_PCREL, BFD_RELOC_SPU_HI16 and BFD_RELOC_SPU_LO16.
+
+
+ * config/tc-ppc.c (parse_cpu): Handle -m464.
+ (md_show_usage): Likewise.
+
+
+ Add support for ATtiny13A.
+ * config/tc-avr.c (mcu_types): Add attiny13a.
+ * doc/c-avr.texi: Likewise.
+
+
+ * write.c (relax_segment <rs_org>): Include current stretch
+ value when calculating whether .org is backwards.
+
+
+ * configure: Regenerate.
+
+
+ * app.c (do_scrub_chars): Do not UNGET an EOF value.
+
+
+ PR gas/6607
+ * config/tc-mmix.c (s_loc): Assume "negative" addresses belong to
+ text_section. Do the "stepping backwards" test for text_section
+ using unsigned operands.
+
+
+ * config/tc-ppc.c (ppc_cpu): Use ppc_cpu_t typedef.
+ (ppc_insert_operand): Likewise.
+ (ppc_machine): Likewise.
+ * config/tc-ppc.h: #include "opcode/ppc.h"
+ (struct _ppc_fix_extra <ppc_cpu>): Use ppc_cpu_t typedef.
+ (ppc_cpu): Update extern decl.
+
+
+ * config/tc-mips.c (validate_mips_insn): Handle field descriptors
+ +x, +X, +p, +P, +s, +S.
+ (mips_ip): Likewise.
+
+ * config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q.
+ (mips_ip): Likewise.
+ (macro_build): Likewise.
+ (CPU_HAS_SEQ): New macro.
+ (macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei.
+
+
+ * config/tc-avr.c (mcu_types): Remove support for ATmega32HVB device.
+ * doc/c-avr.texi: Likewise.
+
+
+ * app.c (do_scrub_chars): Do not UNGET an EOF value.
+
+
+ * config/tc-i386.c (set_sse_check): New.
+ (md_pseudo_table): Add "sse_check".
+
+
+ * config/tc-arm.c (do_t_rbit): Populate both rm fields.
+
+
+ PR 5523
+ * config/tc-avr.c (avr_ldi_expression): Do not warn about unknown
+ relocs here.
+
+
+ * config/tc-mips.c (mips_cpu_info_table): Move records for
+ ST Loongson-2E/2F processors to a better place.
+
+
+ PR gas/6518
+ * config/tc-i386.c (match_template): Report ambiguous operand
+ size, not invalid suffix when there is no match in Intel
+ syntax.
+
+
+ * config/tc-arm.c (parse_cond): Covert to lowercase before matching.
+
+
+ * config/tc-arm.c (arm_cpus): Add Faraday ARMv4 and ARMv5TE
+ compatible cores: fa526, fa626, fa626te, fa726te.
+ * doc/c-arm.texi (ARM Opts): Add -mcpu={fa526, fa626, fa626te,
+ fa726te} options.
+
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+ * doc/Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+
+ * config/tc-mips.c (mips_frob_file): Don't match MIPS16 relocs
+ with non-MIPS16 relocs.
+
+
+ * config/tc-mips.c (md_begin): Use strncmp to compare TARGET_OS, in
+ case that some characters append at the end of the name.
+ (mips_ip): Likewise.
+ (s_change_sec): Likewise.
+ (md_section_align): Likewise.
+
+
+ * config/tc-xtensa.c (xtensa_create_property_segments): Use
+ xtensa_make_property_section instead of xtensa_get_property_section.
+ (xtensa_create_xproperty_segments): Likewise.
+
+
+ * NEWS: Mention XSAVE, EPT and MOVBE.
+
+ * config/tc-i386.c (cpu_arch): Add .movbe and .ept.
+ (md_show_usage): Add .movbe and .ept.
+
+ * doc/c-i386.texi: Add movbe and ept to -march=. Document
+ .movbe and .ept.
+
* config/tc-sparc.c (v9a_asr_table): Fix order of softint entries.
-
+
* config/tc-xtensa.c (xg_apply_fix_value): Check return code from
call to decode_reloc.
-
+
* NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
* config/tc-bfin.c (bfin_start_line_hook): Localize the labels
generated for LOOP_BEGIN and LOOP_END instructions.
- (bfin_gen_loop): Likewise.
+ (bfin_gen_loop): Likewise.
* config/tc-hppa.c (is_same_frag): Delete.
-
+
* config/tc-xtensa.h (xtensa_relax_statesE): Update comment for
RELAX_LOOP_END_ADD_NOP.
-
+
PR gas/5895
-
+
* config/tc-xtensa.c (xtensa_num_pipe_stages): New.
(md_begin): Initialize it.
(resources_conflict): Use it.
-
+
-
+
* config/tc-xtensa.h (RELAX_XTENSA_NONE): New.
-
+
(process_immext): New.
(md_assemble): Use it.
(update_imm): Use imm16 and imm32s.
- (i386_att_operand): Use inoutportreg.
+ (i386_att_operand): Use inoutportreg.
* config/tc-i386.c (set_cpu_arch, md_parse_option): Likewise.
-
+
* config/tc-xtensa.c (relax_frag_immed): Change internal consistency
checks into assertions. When relaxation produces an operation that
does not fit in the current FLIX instruction, make sure that the
operation is relaxed as needed to account for being placed following
the current instruction.
-
+
PR 5715
- * read.c: (emit_expr): Correct for mingw use of printf size
+ * read.c: (emit_expr): Correct for mingw use of printf size
specifier.
-
+
* doc/c-xtensa.texi (Xtensa Syntax): Clarify handling of opcodes that
can only be encoded in FLIX instructions but are not specified as such.
(Xtensa Automatic Alignment): Remove obsolete comment about debugging
labels.
-
+
* NEWS: Mention new command line options for x86 targets.
* doc/c-i386.texi: Update -march= for ISA.
-
+
* config/tc-xtensa.c (xtensa_leb128): New function.
(md_pseudo_table): Use it for sleb128 and uleb128.
(is_leb128_expr): New internal flag.
(xtensa_symbol_new_hook): Check new flag.
-
+
* config/tc-avr.c (mcu_types): Change opcode set for avr3,
at90usb82, at90usb162.
- * doc/c-avr.texi: Change architecture grouping for at90usb82,
+ * doc/c-avr.texi: Change architecture grouping for at90usb82,
at90usb162.
These changes support the new avr35 architecture group in gcc.
unwind personality function address.
-
+
* dwarf2dbg.c (out_sleb128): Delete.
(size_fixed_inc_line_addr, emit_fixed_inc_line_addr): New.
(out_fixed_inc_line_addr): Delete.
* read.h (emit_expr_fix): New prototype.
* read.c (emit_expr): Move code to emit_expr_fix and use it here.
(emit_expr_fix): New.
-
+
* config/tc-i386.c (match_template): Check register size
projects / binutils.git / blobdiff