+start-sanitize-r5900
+
+ * interp.c (SignalException): Clear the simDELAYSLOT flag when an
+ exception has been taken.
+
+ * interp.c: Implement the ERET and mt/f sr instructions.
+
+
+ * gencode.c (build_instruction): For paddu, extract unsigned
+ sub-fields.
+
+ * gencode.c (build_instruction): Saturate padds instead of padd
+ instructions.
+
+end-sanitize-r5900
+
+ * interp.c (SignalException): Don't bother restarting an
+ interrupt.
+
+
+ * interp.c (SignalException): Really take an interrupt.
+ (interrupt_event): Only deliver interrupts when enabled.
+
+
+ * interp.c (sim_info): Only print info when verbose.
+ (sim_info) Use sim_io_printf for output.
+
+
+ * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
+ mips architectures.
+
+
+ * interp.c (sim_do_command): Check for common commands if a
+ simulator specific command fails.
+
+
+ * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
+ and simBE when DEBUG is defined.
+
+
+ * interp.c (interrupt_event): New function. Pass exception event
+ onto exception handler.
+
+ * configure.in: Check for stdlib.h.
+ * configure: Regenerate.
+
+ * gencode.c (build_instruction): Add UNUSED attribute to tempS
+ variable declaration.
+ (build_instruction): Initialize memval1.
+ (build_instruction): Add UNUSED attribute to byte, bigend,
+ reverse.
+ (build_operands): Ditto.
+
+ * interp.c: Fix GCC warnings.
+ (sim_get_quit_code): Delete.
+
+ * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
+ * Makefile.in: Ditto.
+ * configure: Re-generate.
+
+ * Makefile.in (SIM_OBJS): Add sim-watch.o module.
+
+
+ * interp.c (mips_option_handler): New function parse argumes using
+ sim-options.
+ (myname): Replace with STATE_MY_NAME.
+ (sim_open): Delete check for host endianness - performed by
+ sim_config.
+ (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
+ (sim_open): Move much of the initialization from here.
+ (sim_load): To here. After the image has been loaded and
+ endianness set.
+ (sim_open): Move ColdReset from here.
+ (sim_create_inferior): To here.
+ (sim_open): Make FP check less dependant on host endianness.
+
+ * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
+ run.
+ * interp.c (sim_set_callbacks): Delete.
+
+ * interp.c (membank, membank_base, membank_size): Replace with
+ STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
+ (sim_open): Remove call to callback->init. gdb/run do this.
+
+ * interp.c: Update
+
+ * sim-main.h (SIM_HAVE_FLATMEM): Define.
+
+ * interp.c (big_endian_p): Delete, replaced by
+ current_target_byte_order.
+
+
+ * interp.c (host_read_long, host_read_word, host_swap_word,
+ host_swap_long): Delete. Using common sim-endian.
+ (sim_fetch_register, sim_store_register): Use H2T.
+ (pipeline_ticks): Delete. Handled by sim-events.
+ (sim_info): Update.
+ (sim_engine_run): Update.
+
+
+ * interp.c (sim_stop_reason): Move code determining simEXCEPTION
+ reason from here.
+ (SignalException): To here. Signal using sim_engine_halt.
+ (sim_stop_reason): Delete, moved to common.
+
+
+ * interp.c (sim_open): Add callback argument.
+ (sim_set_callbacks): Delete SIM_DESC argument.
+ (sim_size): Ditto.
+
+
+ * Makefile.in (SIM_OBJS): Add common modules.
+
+ * interp.c (sim_set_callbacks): Also set SD callback.
+ (set_endianness, xfer_*, swap_*): Delete.
+ (host_read_word, host_read_long, host_swap_word, host_swap_long):
+ Change to functions using sim-endian macros.
+ (control_c, sim_stop): Delete, use common version.
+ (simulate): Convert into.
+ (sim_engine_run): This function.
+ (sim_resume): Delete.
+
+ * interp.c (simulation): New variable - the simulator object.
+ (sim_kind): Delete global - merged into simulation.
+ (sim_load): Cleanup. Move PC assignment from here.
+ (sim_create_inferior): To here.
+
+ * sim-main.h: New file.
+ * interp.c (sim-main.h): Include.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * tconfig.in (SIM_HAVE_BIENDIAN): Define.
+
+
+ * gencode.c (build_instruction): DIV instructions: check
+ for division by zero and integer overflow before using
+ host's division operation.
+
+
+ * Makefile.in (SIM_OBJS): Add sim-load.o.
+ * interp.c: #include bfd.h.
+ (target_byte_order): Delete.
+ (sim_kind, myname, big_endian_p): New static locals.
+ (sim_open): Set sim_kind, myname. Move call to set_endianness to
+ after argument parsing. Recognize -E arg, set endianness accordingly.
+ (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
+ load file into simulator. Set PC from bfd.
+ (sim_create_inferior): Return SIM_RC. Delete arg start_address.
+ (set_endianness): Use big_endian_p instead of target_byte_order.
+
+
+ * interp.c (sim_size): Delete prototype - conflicts with
+ definition in remote-sim.h. Correct definition.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+
+ * interp.c (sim_open): New arg `kind'.
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * interp.c (sim_open): Set optind to 0 before calling getopt.
+
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+ * interp.c : Replace uses of pr_addr with pr_uword64
+ where the bit length is always 64 independent of SIM_ADDR.
+ (pr_uword64) : added.
+
+
+ * configure: Re-generate.
+
+
+ * configure: Regenerate to track ../common/aclocal.m4 changes.
+
+
+ * interp.c (sim_open): New SIM_DESC result. Argument is now
+ in argv form.
+ (other sim_*): New SIM_DESC argument.
+
+start-sanitize-r5900
+
+ * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
+ Change values to avoid overloading DOUBLEWORD which is tested
+ for all insns.
+ * gencode.c: reinstate "offending code".
+
+end-sanitize-r5900
+
+ * interp.c: Fix printing of addresses for non-64-bit targets.
+ (pr_addr): Add function to print address based on size.
+start-sanitize-r5900
+ * gencode.c: #ifdef out offending code until a permanent fix
+ can be added. Code is causing build errors for non-5900 mips targets.
+end-sanitize-r5900
+
+start-sanitize-r5900
+
+ * gencode.c (process_instructions): Correct test for ISA dependent
+ architecture bits in isa field of MIPS_DECODE.
+
+end-sanitize-r5900
+
+ * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
+
+start-sanitize-r5900
+
+ * gencode.c (MIPS_DECODE): Correct instruction feature flags for
+ PMADDUW.
+
+end-sanitize-r5900
+
+ * gencode.c (build_mips16_operands): Correct computation of base
+ address for extended PC relative instruction.
+
+start-sanitize-r5900
+
+ * Makefile.in, configure, configure.in, gencode.c,
+ interp.c, support.h: add r5900.
+
+end-sanitize-r5900
+
+ * interp.c (mips16_entry): Add support for floating point cases.
+ (SignalException): Pass floating point cases to mips16_entry.
+ (ValueFPR): Don't restrict fmt_single and fmt_word to even
+ registers.
+ (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
+ or fmt_word.
+ (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
+ and then set the state to fmt_uninterpreted.
+ (COP_SW): Temporarily set the state to fmt_word while calling
+ ValueFPR.
+
+
+ * gencode.c (build_instruction): The high order may be set in the
+ comparison flags at any ISA level, not just ISA 4.
+
+
+ * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
+ COMMON_{PRE,POST}_CONFIG_FRAG instead.
+ * configure.in: sinclude ../common/aclocal.m4.
+ * configure: Regenerated.
+
+
+ * configure: Rebuild after change to aclocal.m4.
+
* configure configure.in Makefile.in: Update to new configure
projects / binutils.git / blobdiff