/* Print SPARC instructions.
- Copyright 1989, 1991, 1992, 1993, 1995 Free Software Foundation, Inc.
+ Copyright (C) 1989, 91-93, 1995, 1996 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
#include "libiberty.h"
#include <string.h>
+/* Bitmask of v9 architectures. */
+#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
+ | (1 << SPARC_OPCODE_ARCH_V9A))
+/* 1 if INSN is for v9 only. */
+#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
+/* 1 if INSN is for v9. */
+#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
+
/* For faster lookup, after insns are sorted they are hashed. */
/* ??? I think there is room for even more improvement. */
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
-#ifndef NO_V9
"f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
"f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
"f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
"f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
/* psr, wim, tbr, fpsr, cpsr are v8 only. */
-#endif
"y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
};
#define freg_names (®_names[4 * 8])
-#ifndef NO_V9
/* These are ordered according to there register number in
rdpr and wrpr insns. */
static char *v9_priv_reg_names[] =
"wstate", "fq"
/* "ver" - special cased */
};
-#endif
/* Macros used to extract instruction fields. Not all fields have
macros defined here, only those which are actually used. */
#define X_IMM22(i) X_DISP22 (i)
#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
-#ifndef NO_V9
+/* These are for v9. */
#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
-#endif
+#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
+#define X_MEMBAR(i) ((i) & 0x7f)
/* Here is the union which was used to extract instruction fields
before the shift and mask macros were written.
#define disp22 branch.DISP22
#define imm22 disp22
} branch;
- #ifndef NO_V9
struct
{
unsigned int anop:2;
unsigned int _rs1:5;
unsigned int DISP16LO:14;
} branch16;
- #endif
struct
{
unsigned int anop:2;
return 0;
}
-/* Nonzero of opcode table has been initialized. */
-static int opcodes_initialized = 0;
-
-/* Nonzero of the current architecture is sparc64.
- This is kept in a global because compare_opcodes uses it. */
-static int sparc64_p;
-
/* extern void qsort (); */
static int compare_opcodes ();
+/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
+ to compare_opcodes. */
+static unsigned int current_arch_mask;
+static int compute_arch_mask ();
+
/* Print one instruction from MEMADDR on INFO->STREAM.
We suffix the instruction with a comment that gives the absolute
displacement to that register, or it is an `add' or `or' instruction
on that register. */
-static int
-print_insn (memaddr, info)
+int
+print_insn_sparc (memaddr, info)
bfd_vma memaddr;
disassemble_info *info;
{
unsigned long insn;
register unsigned int i;
register struct opcode_hash *op;
+ /* Nonzero of opcode table has been initialized. */
+ static int opcodes_initialized = 0;
+ /* bfd mach number of last call. */
+ static unsigned long current_mach = 0;
- if (!opcodes_initialized)
+ if (!opcodes_initialized
+ || info->mach != current_mach)
{
- qsort ((char *) sparc_opcodes, NUMOPCODES,
+ current_arch_mask = compute_arch_mask (info->mach);
+ qsort ((char *) sparc_opcodes, sparc_num_opcodes,
sizeof (sparc_opcodes[0]), compare_opcodes);
- build_hash_table (sparc_opcodes, opcode_hash_table, NUMOPCODES);
+ build_hash_table (sparc_opcodes, opcode_hash_table, sparc_num_opcodes);
+ current_mach = info->mach;
opcodes_initialized = 1;
}
{
CONST struct sparc_opcode *opcode = op->opcode;
+ /* If the insn isn't supported by the current architecture, skip it. */
+ if (! (opcode->architecture & current_arch_mask))
+ continue;
+
if ((opcode->match & insn) == opcode->match
&& (opcode->lose & insn) == 0)
{
&& strchr (opcode->args, 'r') != 0)
/* Can't do simple format if source and dest are different. */
continue;
+ if (X_RS2 (insn) != X_RD (insn)
+ && strchr (opcode->args, 'O') != 0)
+ /* Can't do simple format if source and dest are different. */
+ continue;
(*info->fprintf_func) (stream, opcode->name);
is_annulled = 1;
++s;
continue;
-#ifndef NO_V9
case 'N':
(*info->fprintf_func) (stream, "pn");
++s;
(*info->fprintf_func) (stream, "pt");
++s;
continue;
-#endif /* NO_V9 */
default:
break;
break;
case '2':
+ case 'O':
reg (X_RS2 (insn));
break;
}
break;
-#ifndef NO_V9
case 'I': /* 11 bit immediate. */
case 'j': /* 10 bit immediate. */
{
}
break;
+ case 'K':
+ {
+ int mask = X_MEMBAR (insn);
+ int bit = 0x40, printed_one = 0;
+ char *name;
+
+ if (mask == 0)
+ (info->fprintf_func) (stream, "0");
+ else
+ while (bit)
+ {
+ if (mask & bit)
+ {
+ if (printed_one)
+ (info->fprintf_func) (stream, "|");
+ name = sparc_decode_membar (bit);
+ (info->fprintf_func) (stream, "%s", name);
+ printed_one = 1;
+ }
+ bit >>= 1;
+ }
+ break;
+ }
+
case 'k':
- info->target = memaddr + (SEX (X_DISP16 (insn), 16)) * 4;
+ info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
(*info->print_address_func) (info->target, info);
break;
case 'G':
- info->target = memaddr + (SEX (X_DISP22 (insn), 19)) * 4;
+ info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
(*info->print_address_func) (info->target, info);
break;
else
(*info->fprintf_func) (stream, "%%reserved");
break;
- break;
-#endif /* NO_V9 */
+
+ case '*':
+ {
+ char *name = sparc_decode_prefetch (X_RD (insn));
+
+ if (name)
+ (*info->fprintf_func) (stream, "%s", name);
+ else
+ (*info->fprintf_func) (stream, "%d", X_RD (insn));
+ break;
+ }
case 'M':
(*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
break;
case 'L':
- info->target = memaddr + X_DISP30 (insn) * 4;
+ info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
(*info->print_address_func) (info->target, info);
break;
case 'n':
(*info->fprintf_func)
- (stream, "%#x", (SEX (X_DISP22 (insn), 22)));
+ (stream, "%#x", SEX (X_DISP22 (insn), 22));
break;
case 'l':
- info->target = memaddr + (SEX (X_DISP22 (insn), 22)) * 4;
+ info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
(*info->print_address_func) (info->target, info);
break;
case 'A':
- (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
- break;
+ {
+ char *name = sparc_decode_asi (X_ASI (insn));
+
+ if (name)
+ (*info->fprintf_func) (stream, "%s", name);
+ else
+ (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
+ break;
+ }
case 'C':
(*info->fprintf_func) (stream, "%%csr");
case 'y':
(*info->fprintf_func) (stream, "%%y");
break;
+
+ case 'u':
+ case 'U':
+ {
+ int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
+ char *name = sparc_decode_sparclet_cpreg (val);
+
+ if (name)
+ (*info->fprintf_func) (stream, "%s", name);
+ else
+ (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
+ break;
+ }
}
}
}
}
info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
- (*info->fprintf_func) (stream, "%#8x", insn);
+ (*info->fprintf_func) (stream, "unknown");
return sizeof (buffer);
}
+/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
+
+static int
+compute_arch_mask (mach)
+ unsigned long mach;
+{
+ switch (mach)
+ {
+ case 0 :
+ case bfd_mach_sparc :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
+ case bfd_mach_sparc_sparclet :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
+ case bfd_mach_sparc_sparclite :
+ /* sparclites insns are recognized by default (because that's how
+ they've always been treated, for better or worse). Kludge this by
+ indicating generic v8 is also selected. */
+ return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
+ | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
+ case bfd_mach_sparc_v8plus :
+ case bfd_mach_sparc_v9 :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
+ case bfd_mach_sparc_v8plusa :
+ case bfd_mach_sparc_v9a :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
+ }
+ abort ();
+}
+
/* Compare opcodes A and B. */
static int
unsigned long int lose0 = op0->lose, lose1 = op1->lose;
register unsigned int i;
+ /* If one (and only one) insn isn't supported by the current architecture,
+ prefer the one that is. If neither are supported, but they're both for
+ the same architecture, continue processing. Otherwise (both unsupported
+ and for different architectures), prefer lower numbered arch's (fudged
+ by comparing the bitmasks). */
+ if (op0->architecture & current_arch_mask)
+ {
+ if (! (op1->architecture & current_arch_mask))
+ return -1;
+ }
+ else
+ {
+ if (op1->architecture & current_arch_mask)
+ return 1;
+ else if (op0->architecture != op1->architecture)
+ return op0->architecture - op1->architecture;
+ }
+
/* If a bit is set in both match and lose, there is something
wrong with the opcode table. */
if (match0 & lose0)
lose1 = op1->lose;
}
- /* If the current architecture isn't sparc64, move v9 insns to the end.
- Only do this when one isn't v9 and one is. If both are v9 we still
- need to properly sort them.
- This must be done before checking match and lose. */
- if (!sparc64_p
- && (op0->architecture == v9) != (op1->architecture == v9))
- return (op0->architecture == v9) - (op1->architecture == v9);
-
- /* If the current architecture is sparc64, move non-v9 insns to the end.
- This must be done before checking match and lose. */
- if (sparc64_p
- && (op0->flags & F_NOTV9) != (op1->flags & F_NOTV9))
- return (op0->flags & F_NOTV9) - (op1->flags & F_NOTV9);
-
/* Because the bits that are variable in one opcode are constant in
another, it is important to order the opcodes in the right order. */
for (i = 0; i < 32; ++i)
better have the same opcode. This is a sanity check on the table. */
i = strcmp (op0->name, op1->name);
if (i)
+ {
if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
- return i;
+ return i;
else
- fprintf (stderr,
- "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
- op0->name, op1->name);
+ fprintf (stderr,
+ "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
+ op0->name, op1->name);
+ }
/* Fewer arguments are preferred. */
{
}
}
+ /* Put 1,i before i,1. */
+ {
+ int i0 = strncmp (op0->args, "i,1", 3) == 0;
+ int i1 = strncmp (op1->args, "i,1", 3) == 0;
+
+ if (i0 ^ i1)
+ return i0 - i1;
+ }
+
/* They are, as far as we can tell, identical.
Since qsort may have rearranged the table partially, there is
no way to tell which one was first in the opcode table as
}
#endif
}
-
-int
-print_insn_sparc (memaddr, info)
- bfd_vma memaddr;
- disassemble_info *info;
-{
- /* It could happen that we'll switch cpus in a running program.
- Consider objdump or gdb. The frequency of occurrence is expected
- to be low enough that our clumsy approach is not a problem. */
- if (sparc64_p)
- opcodes_initialized = 0;
- sparc64_p = 0;
- return print_insn (memaddr, info);
-}
-
-int
-print_insn_sparc64 (memaddr, info)
- bfd_vma memaddr;
- disassemble_info *info;
-{
- /* It could happen that we'll switch cpus in a running program.
- Consider objdump or gdb. The frequency of occurrence is expected
- to be low enough that our clumsy approach is not a problem. */
- if (!sparc64_p)
- opcodes_initialized = 0;
- sparc64_p = 1;
- return print_insn (memaddr, info);
-}
projects / binutils.git / blobdiff