* v850-opc.c (v850_operands): "not" is a two byte insn.

[binutils.git] / opcodes / v850-opc.c

diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index 91bfcbec0fb4d3f0cc3b631a44844fef6bff4736..2bb8c07d0a3f501e38da91102ac309a6045e67fd 100644 (file)
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -17,7 +17,7 @@ static long extract_d9 PARAMS ((unsigned long, int *));
 #define one(x)         ((unsigned int) (x))
 
 /* two-word opcodes */
-#define two(x,y)       ((unsigned int) (y) | ((unsigned int) (x) << 16))
+#define two(x,y)       ((unsigned int) (x) | ((unsigned int) (y) << 16))
 
 
 \f
@@ -42,7 +42,7 @@ const struct v850_operand v850_operands[] = {
 
 /* The IMM16 field in a format 6 insn. */
 #define I16    (I5U+1)
-  { 16, 0, 0, 0, 0 }, 
+  { 16, 16, 0, 0, 0 }, 
 
 /* The signed DISP7 field in a format 4 insn. */
 #define D7S    (I16+1)
@@ -54,7 +54,7 @@ const struct v850_operand v850_operands[] = {
 
 /* The DISP16 field in a format 6 insn. */
 #define D16    (D9+1)
-  { 16, 0, 0, 0, V850_OPERAND_SIGNED }, 
+  { 16, 16, 0, 0, V850_OPERAND_SIGNED }, 
 
 /* The DISP22 field in a format 4 insn. */
 #define D22    (D16+1)
@@ -72,6 +72,12 @@ const struct v850_operand v850_operands[] = {
 #define D8     (CCCC+1)
   { 8, 0, 0, 0, 0 },
 
+/* System register operands.  */
+#define SR1    (D8+1)
+  { 5, 0, 0, 0, V850_OPERAND_SRG }, 
+
+#define SR2    (SR1+1)
+  { 5, 11, 0, 0, V850_OPERAND_SRG },
 } ; 
 
 \f
@@ -153,7 +159,7 @@ const struct v850_opcode v850_opcodes[] = {
 { "divh",      OP(0x02),               OP_MASK,        IF1, 2 },
 { "cmp",       OP(0x0f),               OP_MASK,        IF1, 2 },
 { "cmp",       OP(0x13),               OP_MASK,        IF2, 2 },
-{ "setf",      two(0x0000,0x0000),     two(0x0000,0xffff), {CCCC,R2}, 4 },
+{ "setf",      two(0x07e0,0x0000),     two(0x07f0,0xffff), {CCCC,R2}, 4 },
 
 /* saturated operation instructions */
 { "satadd",    OP(0x06),               OP_MASK,        IF1, 2 },
@@ -170,7 +176,7 @@ const struct v850_opcode v850_opcodes[] = {
 { "andi",      OP(0x36),               OP_MASK,        IF6, 4 },
 { "xor",       OP(0x09),               OP_MASK,        IF1, 2 },
 { "xori",      OP(0x35),               OP_MASK,        IF6, 4 },
-{ "not",       OP(0x01),               OP_MASK,        IF1, 4 },
+{ "not",       OP(0x01),               OP_MASK,        IF1, 2 },
 { "sar",       OP(0x15),               OP_MASK,        {I5U, R2}, 2 },
 { "sar",       two(0x07e0,0x00a0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 { "shl",       OP(0x16),               OP_MASK,                {I5U, R2}, 2 },
@@ -204,7 +210,7 @@ const struct v850_opcode v850_opcodes[] = {
 { "br",                BOP(0x5),               BOP_MASK,       IF3, 2 },
 { "bsa",       BOP(0xd),               BOP_MASK,       IF3, 2 },
 
-{ "jmp",       one(0x0060),            one(0xffe0),    R1, 2 },
+{ "jmp",       one(0x0060),            one(0xffe0),    { R1}, 2 },
 { "jarl",      one(0x0780),            one(0xf83f),    { D22, R2 }, 4 }, 
 { "jr",                one(0x0780),            one(0xffe0),    { D22 }, 4 },
 
@@ -219,9 +225,9 @@ const struct v850_opcode v850_opcodes[] = {
 { "ei",                two(0x87e0,0x0160),     two(0xffff,0xffff),     {0}, 4 },
 { "halt",      two(0x07e0,0x0120),     two(0xffff,0xffff),     {0}, 4 },
 { "reti",      two(0x07e0,0x0140),     two(0xffff,0xffff),     {0}, 4 },
-{ "trap",      two(0x07e0,0x0100),     two(0xffe0,0xffff),     I5U, 4 },
-{ "ldsr",      two(0x07e0,0x0020),     two(0x07e0,0xffff),     IF1, 4 },
-{ "stsr",      two(0x07e0,0x0040),     two(0x07e0,0xffff),     IF1, 4 },
+{ "trap",      two(0x07e0,0x0100),     two(0xffe0,0xffff),     {I5U}, 4 },
+{ "ldsr",      two(0x07e0,0x0020),     two(0x07e0,0xffff),     {R1,SR2}, 4 },
+{ "stsr",      two(0x07e0,0x0040),     two(0x07e0,0xffff),     {SR1,R2}, 4 },
 { "nop",       one(0x00),              one(0xff),              {0}, 2 },
 
 } ;