GNU/Linux.
Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
- 2009, 2010 Free Software Foundation, Inc.
+ 2009, 2010, 2011 Free Software Foundation, Inc.
This file is part of GDB.
#include <asm/ptrace_offsets.h>
#include <sys/procfs.h>
-/* Prototypes for supply_gregset etc. */
+/* Prototypes for supply_gregset etc. */
#include "gregset.h"
/* These must match the order of the register names.
static int u_offsets[] =
{
/* general registers */
- -1, /* gr0 not available; i.e, it's always zero */
+ -1, /* gr0 not available; i.e, it's always zero. */
PT_R1,
PT_R2,
PT_R3,
PT_R29,
PT_R30,
PT_R31,
- /* gr32 through gr127 not directly available via the ptrace interface */
+ /* gr32 through gr127 not directly available via the ptrace interface. */
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
/* Floating point registers */
- -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
+ -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
PT_F2,
PT_F3,
PT_F4,
PT_F125,
PT_F126,
PT_F127,
- /* predicate registers - we don't fetch these individually */
+ /* Predicate registers - we don't fetch these individually. */
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
PT_B5,
PT_B6,
PT_B7,
- /* virtual frame pointer and virtual return address pointer */
+ /* Virtual frame pointer and virtual return address pointer. */
-1, -1,
/* other registers */
PT_PR,
PT_CR_IIP, /* ip */
PT_CR_IPSR, /* psr */
PT_CFM, /* cfm */
- /* kernel registers not visible via ptrace interface (?) */
+ /* kernel registers not visible via ptrace interface (?) */
-1, -1, -1, -1, -1, -1, -1, -1,
/* hole */
-1, -1, -1, -1, -1, -1, -1, -1,
PT_AR_BSPSTORE,
PT_AR_RNAT,
-1,
- -1, /* Not available: FCR, IA32 floating control register */
+ -1, /* Not available: FCR, IA32 floating control register. */
-1, -1,
-1, /* Not available: EFLAG */
-1, /* Not available: CSD */
-1, -1, -1, -1, -1, -1, -1, -1, -1,
PT_AR_PFS,
PT_AR_LC,
- -1, /* Not available: EC, the Epilog Count register */
+ -1, /* Not available: EC, the Epilog Count register. */
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1,
/* nat bits - not fetched directly; instead we obtain these bits from
- either rnat or unat or from memory. */
+ either rnat or unat or from memory. */
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
}
/* FIXME: NAT collection bits are at index 32; gotta deal with these
- somehow... */
+ somehow... */
regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
COPY_REG (regi - IA64_GR0_REGNUM, regi);
}
- /* FIXME: NAT collection bits at index 32? */
+ /* FIXME: NAT collection bits at index 32? */
COPY_REG (33, IA64_PR_REGNUM);
/* Given a pointer to a floating point register set in /proc format
(fpregset_t *), unpack the register contents and supply them as gdb's
- idea of the current floating point register values. */
+ idea of the current floating point register values. */
void
supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
/* Given a pointer to a floating point register set in /proc format
(fpregset_t *), update the register specified by REGNO from gdb's idea
of the current floating point register set. If REGNO is -1, update
- them all. */
+ them all. */
void
fill_fpregset (const struct regcache *regcache,
if (!(psr & IA64_PSR_DB))
{
psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
- watchpoints and breakpoints. */
+ watchpoints and breakpoints. */
regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
}
}
}
static void
-store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
+store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
+ long *dbr_mask)
{
if (dbr_addr)
store_debug_register (ptid, 2 * idx, *dbr_addr);
dbr_mask = debug_registers[idx * 2 + 1];
if ((dbr_mask & (0x3UL << 62)) == 0)
{
- /* Exit loop if both r and w bits clear */
+ /* Exit loop if both r and w bits clear. */
break;
}
}
regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
- for the next instruction */
+ for the next instruction. */
regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
*addr_p = (CORE_ADDR)siginfo_p->si_addr;
static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
- const char *, gdb_byte *, const gdb_byte *,
- ULONGEST, LONGEST);
+ const char *, gdb_byte *,
+ const gdb_byte *, ULONGEST, LONGEST);
static LONGEST
ia64_linux_xfer_partial (struct target_ops *ops,
This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
code there has determined that a hardware watchpoint has indeed
been hit. The CPU will then be able to execute one instruction
- without triggering a watchpoint. */
+ without triggering a watchpoint. */
t->to_have_steppable_watchpoint = 1;
t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
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