Fix GAS testsuite failures for COFF/PE based ARM targets.

[binutils.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1b77b64ba015aafbdd27928a7426972604ed777e..a676b7116cb30bdd04c0637268493fa4fe721a5d 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,189 @@
+2015-12-04  Nick Clifton  <[email protected]>
+
+       PR gas/19276
+       * config/tc-arm.h (SUB_SEGMENT_ALIGN): Do not define for COFF/PE
+       targets.
+
+2015-12-04  Claudiu Zissulescu  <[email protected]>
+
+       * config/tc-arc.c (arc_option): Sets all internal gas options when
+       parsing .cpu directive.
+       (declare_register_set): Declare all 64 registers.
+       (md_section_align): Refactor.
+       (md_pcrel_from_section): Remove assert.
+       (pseudo_operand_match): Fix pseudo operand match.
+       (find_reloc): Use flags filed, extend matching.
+       * config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT
+       relocation.
+
+2015-12-01  Alan Modra  <[email protected]>
+
+       * config/aout_gnu.h: Invoke aout N_* macros with pointer to
+       struct internal_exec.
+
+2015-11-27  Matthew Wahab  <[email protected]>
+
+       * config/tc-aarch64.c (aarch64_features): Add "fp16".
+       * doc/c-aarch64.texi (Architecture Extensions): Add "fp16".
+
+2015-11-24  Christophe Monat <[email protected]>
+
+       * config/tc-arm.c (move_or_literal_pool): Do not transform ldr
+       ri,=imm into movs when ri is a high register in T1.
+
+2015-11-20  Nick Clifton  <[email protected]>
+
+       * po/fr.po: Updated French translation.
+       * po/uk.po: Updated Ukraninan translation.
+       * po/zh_CN.po: New simplified Chinese translation.
+       * configure.ac (ALL_LINGUAS): Add zh_CN.
+       * configure: Regenerate.
+
+2015-11-19  Matthew Wahab  <[email protected]>
+
+       * config/tc-arm.c (arm_archs): Add "armv8.2-a".
+       * doc/c-arm.texi (-march): Add "armv8.2-a".
+
+2015-11-19  Matthew Wahab  <[email protected]>
+
+       * config/tc-aarch64.c (aarch64_archs): Add "armv8.2-a".
+       * doc/c-aarch64.texi (-march): Likewise.
+
+2015-11-19  Alan Modra  <[email protected]>
+
+       * read.c (output_big_leb128): Describe "sign" parameter.
+
+2015-11-19  Alan Modra  <[email protected]>
+
+       * config/tc-ppc.h (SUB_SEGMENT_ALIGN): Define only for ELF.
+
+2015-11-16  Mike Frysinger  <[email protected]>
+
+       * config/tc-microblaze.c (parse_imm): Add an offsetT cast.
+
+2015-11-13  Tristan Gingold  <[email protected]>
+
+       * configure: Regenerate.
+
+2015-11-13  Tristan Gingold  <[email protected]>
+
+       * NEWS: Add marker for 2.26.
+
+2015-11-12  James Greenhalgh  <[email protected]>
+
+       * config/tc-aarch64.c (aarch64_cpus): Add cortex-a35.
+       * doc/c-aarch64.texi (-mcpu=): Likewise.
+
+2015-11-12  James Greenhalgh  <[email protected]>
+
+       * config/tc-arm.c (arm_cpus): Likewise.
+       * doc/c-arm.texi (-mcpu=): Likewise.
+
+2015-11-12  Matthew Wahab  <[email protected]>
+
+       PR gas/19217
+       * config/tc-arm.c (move_or_literal_pool): Remove redundant feature
+       check.  Fix some code formatting.  Drop use of MOVT.  Add some
+       comments.
+
+2015-11-11  Alan Modra  <[email protected]>
+           Peter Bergner <[email protected]>
+
+       * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
+       * doc/c-ppc.texi (PowerPC-Opts):  Likewise.
+       * config/tc-ppc.c (md_show_usage): Likewise.
+       (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
+       (md_apply_fix): Likewise.
+       (ppc_handle_align): Handle power9's group ending nop.
+
+2015-11-09  Jim Wilson  <[email protected]>
+
+       * config/tc-aarch64.c (aarch64_cpus): Add qdf24xx.
+       * config/tc-arm.c (arm_cpus): Likewise.
+       * doc/c-arm.texi, doc/c-aarch64.texi: Likewise.
+
+2015-11-09  Dominik Vogt  <[email protected]>
+
+       * read.c (parse_bitfield_cons): Fix left shift of negative value.
+       * config/tc-xstormy16.c (md_section_align): Likewise.
+       * config/tc-xgate.c (md_section_align): Likewise.
+       * config/tc-visium.c (md_section_align): Likewise.
+       * config/tc-v850.c (md_section_align): Likewise.
+       * config/tc-tic6x.c (md_section_align): Likewise.
+       * config/tc-sh.c (SH64PCREL32_M, SH64PCREL48_M, SH64PCREL32_M)
+       (MOVI_32_M, MOVI_48_M, MOVI_32_M, md_section_align): Likewise.
+       * config/tc-sh64.c (shmedia_md_estimate_size_before_relax): Likewise.
+       * config/tc-score.c (s3_section_align): Likewise.
+       * config/tc-score7.c (s7_section_align): Likewise.
+       * config/tc-s390.c (md_section_align): Likewise.
+       * config/tc-rx.c (md_section_align): Likewise.
+       * config/tc-rl78.c (md_section_align): Likewise.
+       * config/tc-ppc.c (md_section_align): Likewise.
+       * config/tc-or1k.c (md_section_align): Likewise.
+       * config/tc-nds32.c (md_section_align): Likewise.
+       * config/tc-mt.c (md_section_align): Likewise.
+       * config/tc-msp430.c (md_section_align): Likewise.
+       * config/tc-mn10300.c (md_section_align): Likewise.
+       * config/tc-mn10200.c (md_section_align): Likewise.
+       * config/tc-mips.c (md_section_align): Likewise.
+       * config/tc-microblaze.c (parse_imm): Likewise.
+       * config/tc-mep.c (md_section_align): Likewise.
+       * config/tc-m68k.c (md_section_align): Likewise.
+       * config/tc-m68hc11.c (md_section_align): Likewise.
+       * config/tc-m32r.c (md_section_align): Likewise.
+       * config/tc-m32c.c (md_section_align): Likewise.
+       * config/tc-lm32.c (md_section_align): Likewise.
+       * config/tc-iq2000.c (md_section_align): Likewise.
+       * config/tc-ip2k.c (md_section_align): Likewise.
+       * config/tc-ia64.c (dot_save, dot_vframe): Likewise.
+       * config/tc-i960.c (md_number_to_field, md_section_align): Likewise.
+       * config/tc-i386.c (md_section_align): Likewise.
+       * config/tc-i370.c (md_section_align): Likewise.
+       * config/tc-frv.c (md_section_align): Likewise.
+       * config/tc-fr30.c (md_section_align): Likewise.
+       * config/tc-epiphany.c (md_section_align): Likewise.
+       * config/tc-d30v.c (md_section_align): Likewise.
+       * config/tc-d10v.c (md_section_align): Likewise.
+       * config/tc-cr16.c (l_cons): Likewise.
+       * config/tc-bfin.c (md_section_align): Likewise.
+       * config/tc-arm.c (md_section_align): Likewise.
+       * config/tc-arc.c (md_section_align): Likewise.
+       * config/bfin-parse.y (expr_1): Likewise.
+
+2015-11-02  Nick Clifton  <[email protected]>
+
+       * config/rx-parse.y: Allow zero value for 5-bit displacements.
+
+2015-11-02  Nick Clifton  <[email protected]>
+
+       * config/tc-rx.c (parse_rx_section): Align parameter provides a
+       multiple of n argument, not a power of n argument.
+
+2015-10-29  Nick Clifton  <[email protected]>
+
+       * config/tc-aarch64.c (elf64_aarch64_target_format): Select the
+       cloudabi format if the TARGET_OS is cloudabi.
+
+2015-10-29  Thomas Preud'homme  <[email protected]>
+
+       * config/tc-arm.c (insns): Guard cps by arm_ext_v6_notm instead of
+       arm_ext_v6_dsp.
+
+2015-10-28  Claudiu Zissulescu  <[email protected]>
+
+       * config/tc-arc.c (tokenize_arguments): Avoid creating unused
+       symbols when parsing relocation types.
+       (md_apply_fix): Handle TLS relocations. Fix BFD_RELOC_ARC_32_PCREL
+       relocation.
+       (arc_check_reloc): Emit BFD_RELOC_ARC_32_PCREL relocation.
+
+2015-10-27  Jim Wilson  <[email protected]>
+
+       * config/tc-arm.c (selected_cpu_name): Increase length of array to
+       accomodate "Samsung Exynos M1".
+       (arm_parse_cpu): Add assertion and length check to prevent
+       overfilling selected_cpu_name.
+
 2015-10-22  Nick Clifton  <[email protected]>
 
        * config/tc-msp430.c (PUSH_1X_WORKAROUND): Delete.