x86-64: don't accept supposedly disabled MOVQ forms

[binutils.git] / bfd / cpu-mips.c

diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index cb50c643719f2404d0703494bd7d6ad352b53644..5a944ceee81e97ff320016fe9096f33d26611ea4 100644 (file)
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -1,5 +1,5 @@
 /* bfd back-end for mips support
-   Copyright (C) 1990-2018 Free Software Foundation, Inc.
+   Copyright (C) 1990-2021 Free Software Foundation, Inc.
    Written by Steve Chamberlain of Cygnus Support.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -43,9 +43,9 @@ mips_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
 
 #define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT)          \
   {                                                    \
-    BITS_WORD, /*  bits in a word */                   \
-    BITS_ADDR, /* bits in an address */                        \
-    8, /* 8 bits in a byte */                          \
+    BITS_WORD,  /* Bits in a word.  */                 \
+    BITS_ADDR,  /* Bits in an address.  */             \
+    8,         /* Bits in a byte.  */                  \
     bfd_arch_mips,                                     \
     NUMBER,                                            \
     "mips",                                            \
@@ -56,6 +56,7 @@ mips_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
     bfd_default_scan,                                  \
     bfd_arch_default_fill,                             \
     NEXT,                                              \
+    0 /* Maximum offset of a reloc from the start of an insn.  */ \
   }
 
 enum
@@ -98,7 +99,9 @@ enum
   I_sb1,
   I_loongson_2e,
   I_loongson_2f,
-  I_loongson_3a,
+  I_gs464,
+  I_gs464e,
+  I_gs264e,
   I_mipsocteon,
   I_mipsocteonp,
   I_mipsocteon2,
@@ -148,17 +151,19 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mipsisa64r5,"mips:isa64r5", FALSE, NN(I_mipsisa64r5)),
   N (64, 64, bfd_mach_mipsisa64r6,"mips:isa64r6", FALSE, NN(I_mipsisa64r6)),
   N (64, 64, bfd_mach_mips_sb1, "mips:sb1",      FALSE, NN(I_sb1)),
-  N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e",      FALSE, NN(I_loongson_2e)),
-  N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f",      FALSE, NN(I_loongson_2f)),
-  N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a",      FALSE, NN(I_loongson_3a)),
+  N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
+  N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
+  N (64, 64, bfd_mach_mips_gs464, "mips:gs464",          FALSE, NN(I_gs464)),
+  N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e", FALSE, NN(I_gs464e)),
+  N (64, 64, bfd_mach_mips_gs264e, "mips:gs264e", FALSE, NN(I_gs264e)),
   N (64, 64, bfd_mach_mips_octeon,"mips:octeon",  FALSE, NN(I_mipsocteon)),
-  N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+",  FALSE, NN(I_mipsocteonp)),
-  N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2",  FALSE, NN(I_mipsocteon2)),
-  N (64, 64, bfd_mach_mips_octeon3, "mips:octeon3",  FALSE, NN(I_mipsocteon3)),
-  N (64, 64, bfd_mach_mips_xlr, "mips:xlr",      FALSE, NN(I_xlr)),
+  N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
+  N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
+  N (64, 64, bfd_mach_mips_octeon3, "mips:octeon3", FALSE, NN(I_mipsocteon3)),
+  N (64, 64, bfd_mach_mips_xlr, "mips:xlr",       FALSE, NN(I_xlr)),
   N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", FALSE,
      NN(I_interaptiv_mr2)),
-  N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
+  N (64, 64, bfd_mach_mips_micromips, "mips:micromips", FALSE, NULL)
 };
 
 /* The default architecture is mips:3000, but with a machine number of