+start-sanitize-v850
+
+ * v850-opc.c (v850_operands): "not" is a two byte insn
+
+ * v850-opc.c (v850_opcodes): Correct bit pattern for setf.
+
+ * v850-opc.c (v850_operands): D16 inserts at offset 16!
+
+ * v850-opc.c (two): Get order of words correct.
+
+ * v850-opc.c (v850_operands): I16 inserts at offset 16!
+
+ * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system
+ register source and destination operands.
+ (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr".
+
+ * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix
+ same thinko in "trap" opcode.
+
+ * v850-opc.c (v850_opcodes): Add initializer for size field
+ on all opcodes.
+
+ * v850-opc.c (v850_operands): D6 -> DS7. References changed.
+ Add D8 for 8-bit unsigned field in short load/store insns.
+ (IF4A, IF4D): These both need two registers.
+ (IF4C, IF4D): Define. Use 8-bit unsigned field.
+ (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
+ IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand
+ for "ldsr" and "stsr".
+ * v850-opc.c (v850_operands): 3-bit immediate for bit insns
+ is unsigned.
+
+ * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and
+ short store word (sst.w).
+
+
+ * v850-opc.c (v850_operands): Added insert and extract fields,
+ pointers to functions that handle unusual operand encodings.
+
+
+ * v850-opc.c (v850_opcodes): Enable "trap".
+
+ * v850-opc.c (v850_opcodes): Fix order of displacement
+ and register for "set1", "clr1", "not1", and "tst1".
+
+
+ * v850-opc.c (v850_operands): Add "B3" support.
+ (v850_opcodes): Fix and enable "set1", "clr1", "not1"
+ and "tst1".
+
+ * v850-opc.c (v850_opcodes): "jmp" has only an R1 operand.
+
+ * v850-opc.c: Close unterminated comment.
+
+
+ * v850-opc.c (v850_operands): Add flags field.
+ (v850_opcodes): add move opcodes.
+
+
+ * Makefile.in (ALL_MACHINES): Add v850-opc.o.
+ * configure: (bfd_v850v_arch) Add new case.
+ * configure.in: (bfd_v850_arch) Add new case.
+ * v850-opc.c: New file.
+
+end-sanitize-v850
+
+ * sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
+
+start-sanitize-d10v
+
+ * d10v-opc.c: Add additional information to the opcode
+ table to help determinine which instructions can be done
+ in parallel.
+
+end-sanitize-d10v
+
+ * mpw-make.sed: Update editing of include pathnames to be
+ more general.
+
+
+ * arm-opc.h: Added "bx" instruction definition.
+
+
+ * alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
+
+start-sanitize-d10v
+
+ * d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
+
+
+ * d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
+
+end-sanitize-d10v
+
+ * makefile.vms: Update for alpha-opc changes.
+
+
+ * i386-dis.c (print_insn_i386): Actually return the correct value.
+ (ONE, OP_ONE): #ifdef out; not used.
+
+start-sanitize-d10v
+
+ * d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions.
+ Changed subi operand type to treat 0 as 16.
+
+end-sanitize-d10v
+
+ * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose
+
+
+ * arm-opc.h: (arm_opcodes): Added halfword and sign-extension
+ memory transfer instructions. Add new format string entries %h and %s.
+ * arm-dis.c: (print_insn_arm): Provide decoding of the new
+ formats %h and %s.
+
+start-sanitize-d10v
+
+ * d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
+ (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
+
+end-sanitize-d10v
+
+ * alpha-dis.c (print_insn_alpha_osf): Remove.
+ (print_insn_alpha_vms): Remove.
+ (print_insn_alpha): Make globally visible. Chose the register
+ names based on info->flavour.
+ * disassemble.c: Always return print_insn_alpha for the alpha.
+
+start-sanitize-d10v
+
+ * d10v-dis.c (dis_long): Handle unknown opcodes.
+
+
+ * d10v-opc.c: Changes to support signed and unsigned numbers.
+ All instructions with the same name that have long and short forms
+ now end in ".l" or ".s". Divs added.
+ * d10v-dis.c: Changes to support signed and unsigned numbers.
+
+
+ * d10v-dis.c: Change all functions to use info->print_address_func.
+
+end-sanitize-d10v
+
+ * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
+ move ccr/sr insns more strict so that the disassembler only
+ selects them when the addressing mode is data register.
+
+start-sanitize-d10v
+ * d10v-opc.c (pre_defined_registers): Declare.
+ * d10v-dis.c (print_operand): Now uses pre_defined_registers
+ to pick a better name for the registers.
+
+end-sanitize-d10v
+
+ * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix
+ operands for fexpand and fpmerge. From Christian Kuehnke
+
+
+ * alpha-dis.c (print_insn_alpha): No longer the user-visible
+ print routine. Take new regnames and cpumask arguments.
+ Kill the environment variable nonsense.
+ (print_insn_alpha_osf): New function. Do OSF/1 style regnames.
+ (print_insn_alpha_vms): New function. Do VMS style regnames.
+ * disassemble.c (disassembler): Test bfd flavour to pick
+ between OSF and VMS routines. Default to OSF.
+
+
+ * configure.in: Call AC_SUBST (INSTALL_SHLIB).
+ * configure: Rebuild.
+ * Makefile.in (install): Use @INSTALL_SHLIB@.
+
+start-sanitize-d10v
+
+ * configure: (bfd_d10v_arch) Add new case.
+ * configure.in: (bfd_d10v_arch) Add new case.
+ * d10v-dis.c: New file.
+ * d10v-opc.c: New file.
+ * disassemble.c (disassembler) Add entry for d10v.
+
+end-sanitize-d10v
+
+ * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
+ to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
+
+
+ * i386-dis.c: Get rid of print_insn_i8086. Use info.mach to
+ distinguish between variants of the instruction set.
+ * sparc-dis.c: Get rid of print_insn_sparclite. Use info.mach to
+ distinguish between variants of the instruction set.
+
+
+ * i386-dis.c (print_insn_i8086): New routine to disassemble using
+ the 8086 instruction set.
+ * i386-dis.c: General cleanups. Make most things static. Add
+ prototypes. Get rid of static variables aflags and dflags. Pass
+ them as args (to almost everything).
+
+ * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns.
+
+ * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l".
+
+ * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two
+ if the next arg is marked with SRC_IN_DST. Gross.
+
+ * h8300-dis.c (bfd_h8_disassemble): Print "exr" when
+ we're looking for and find EXR.
+
+ * h8300-dis.c (bfd_h8_disassemble): We don't have a match
+ if we're looking for KBIT and we don't find it.
+
+ * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits
+ for L_3 and L_2.
+
* h8300-dis.c (bfd_h8_disassemble): Don't set plen for
3bit immediate operands.
projects / binutils.git / blobdiff