End tic80 sanitization regions with "end-sanitize-tic80", not

[binutils.git] / opcodes / v850-opc.c

diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index 7b4534e026940944e7c80782cf068b6eecd4ca3a..59270ed3ea013e668bd9e7d4147124aa93de84ac 100644 (file)
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -1,3 +1,20 @@
+/* Assemble V850 instructions.
+   Copyright (C) 1996 Free Software Foundation, Inc.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
 #include "ansidecl.h"
 #include "opcode/v850.h"
 
@@ -57,19 +74,11 @@ const struct v850_operand v850_operands[] = {
 #define D7     (I16+1)
   { 7, 0, 0, 0, 0},
 
-/* The DISP9 field in a format 3 insn. */
-#define D9     (D7+1)
-  { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
-
 /* The DISP16 field in a format 6 insn. */
-#define D16_15 (D9+1)
+#define D16_15 (D7+1)
   { 16, 16, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, 
 
-/* The DISP22 field in a format 4 insn. */
-#define D22    (D16_15+1)
-  { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED },
-
-#define B3     (D22+1)
+#define B3     (D16_15+1)
 /* The 3 bit immediate field in format 8 insn.  */
   { 3, 11, 0, 0, 0 },
 
@@ -105,6 +114,17 @@ const struct v850_operand v850_operands[] = {
 #define D16    (SR2+1)
   { 16, 16, 0, 0, V850_OPERAND_SIGNED }, 
 
+/* The DISP22 field in a format 4 insn, relaxable. */
+#define D9_RELAX       (D16+1)
+  { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP },
+
+/* The DISP22 field in a format 4 insn.
+
+   This _must_ follow D9_RELAX; the assembler assumes that the longer
+   version immediately follows the shorter version for relaxing.  */
+#define D22    (D9_RELAX+1)
+  { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
+
 } ; 
 
 \f
@@ -115,7 +135,7 @@ const struct v850_operand v850_operands[] = {
 #define IF2    {I5, R2}
 
 /* conditional branch instruction format (Format III) */
-#define IF3    {D9}
+#define IF3    {D9_RELAX}
 
 /* 16-bit load/store instruction (Format IV) */
 #define IF4A   {D7, EP, R2}
@@ -164,6 +184,7 @@ const struct v850_operand v850_operands[] = {
    sorted by major opcode.  */
 
 const struct v850_opcode v850_opcodes[] = {
+{ "breakpoint",        0xffff,                 0xffff,         0,    0 },
 /* load/store instructions */
 { "sld.b",     one(0x0300),            one(0x0780),    IF4A, 1 },
 { "sld.h",     one(0x0400),            one(0x0780),    IF4C, 1 },
@@ -247,6 +268,35 @@ const struct v850_opcode v850_opcodes[] = {
 { "br",                BOP(0x5),               BOP_MASK,       IF3, 0 },
 { "bsa",       BOP(0xd),               BOP_MASK,       IF3, 0 },
 
+/* Branch macros.
+
+   We use the short form in the opcode/mask fields.  The assembler
+   will twiddle bits as necessary if the long form is needed.  */
+
+       /* signed integer */
+{ "jgt",       BOP(0xf),               BOP_MASK,       IF3, 0 },
+{ "jge",       BOP(0xe),               BOP_MASK,       IF3, 0 },
+{ "jlt",       BOP(0x6),               BOP_MASK,       IF3, 0 },
+{ "jle",       BOP(0x7),               BOP_MASK,       IF3, 0 },
+       /* unsigned integer */
+{ "jh",                BOP(0xb),               BOP_MASK,       IF3, 0 },
+{ "jnh",       BOP(0x3),               BOP_MASK,       IF3, 0 },
+{ "jl",                BOP(0x1),               BOP_MASK,       IF3, 0 },
+{ "jnl",       BOP(0x9),               BOP_MASK,       IF3, 0 },
+       /* common */
+{ "je",                BOP(0x2),               BOP_MASK,       IF3, 0 },
+{ "jne",       BOP(0xa),               BOP_MASK,       IF3, 0 },
+       /* others */
+{ "jv",                BOP(0x0),               BOP_MASK,       IF3, 0 },
+{ "jnv",       BOP(0x8),               BOP_MASK,       IF3, 0 },
+{ "jn",                BOP(0x4),               BOP_MASK,       IF3, 0 },
+{ "jp",                BOP(0xc),               BOP_MASK,       IF3, 0 },
+{ "jc",                BOP(0x1),               BOP_MASK,       IF3, 0 },
+{ "jnc",       BOP(0x9),               BOP_MASK,       IF3, 0 },
+{ "jz",                BOP(0x2),               BOP_MASK,       IF3, 0 },
+{ "jnz",       BOP(0xa),               BOP_MASK,       IF3, 0 },
+{ "jsa",       BOP(0xd),               BOP_MASK,       IF3, 0 },
+
 { "jmp",       one(0x0060),            one(0xffe0),    { R1}, 1 },
 { "jr",                one(0x0780),            two(0xffc0,0x0001),{ D22 }, 0 },
 { "jarl",      one(0x0780),            two(0x07c0,0x0001),{ D22, R2 }, 0 }, 
@@ -281,7 +331,7 @@ insert_d9 (insn, value, errmsg)
      long value;
      const char **errmsg;
 {
-  if (value > 255 || value <= -256)
+  if (value > 0xff || value < -0x100)
     *errmsg = "branch value out of range";
 
   if ((value % 2) != 0)
@@ -309,7 +359,7 @@ insert_d22 (insn, value, errmsg)
      long value;
      const char **errmsg;
 {
-  if (value > 0xfffff || value <= -0x100000)
+  if (value > 0x1fffff || value < -0x200000)
     *errmsg = "branch value out of range";
 
   if ((value % 2) != 0)
@@ -334,7 +384,7 @@ insert_d16_15 (insn, value, errmsg)
      long value;
      const char **errmsg;
 {
-  if (value > 0x7fff || value <= -0x8000)
+  if (value > 0x7fff || value < -0x8000)
     *errmsg = "value out of range";
 
   if ((value % 2) != 0)