+
+ * elf32-spu.g (struct spu_elf_params, enum _ovly_flavour): New.
+ (spu_elf_setup): Declare.
+ (spu_elf_create_sections, spu_elf_size_stubs): Update prototype.
+ (spu_elf_build_stubs, spu_elf_check_vma): Likewise.
+ * elf32-spu.c (struct spu_link_hash_table): Add "params". Remove
+ various other fields now in "params". Adjust code throughout.
+ (struct call_info, struct function_info): Move earlier in file.
+ (struct spu_elf_stack_info): Likewise.
+ (spu_elf_setup): New function.
+ (spu_elf_create_sections): Remove args other than "info".
+ (spu_elf_size_stubs, spu_elf_build_stubs, spu_elf_check_vma): Likewise.
+ (maybe_needs_stubs): Remove "output_bfd" arg. Adjust all calls.
+ (interesting_section): Similarly with "obfd" arg.
+ (needs_ovl_stub): Adjust output_section test.
+ (allocate_spuear_stubs): Likewise.
+ (OVL_STUB_SIZE): Don't define.
+ (ovl_stub_size): New function, use in place of OVL_STUB_SIZE.
+ (build_stub): Test params->ovly_flavour rather than OVL_STUB_SIZE.
+ (spu_elf_auto_overlay): Remove args other than "info". Make use
+ of size returned from spu_elf_load_ovl_mgr.
+ (spu_elf_stack_analysis): Remove args other than "info".
+ (spu_elf_relocate_section): Tidy setting of "ea".
+
+
+ * elf32-spu.c (find_function_stack_adjust): Don't limit number
+ of insns scanned. Correct sp tests. Handle "fsmbi" and "andbi".
+ (mark_detached_root): New function.
+ (build_call_tree): Call it.
+ (sort_calls): Don't do void* arithmetic.
+ (define_ovtab_symbol): Don't abort on symbols defined in linker scripts.
+ (discover_functions): Consider STT_SECTION symbols too.
+ (collect_lib_sections): Don't cut short call tree traversal
+ when function size is too large.
+
+
+ * pef.c (bfd_pef_parse_traceback_table): Add parens to placate gcc
+ 4.4.
+
+
+ * cpu-avr.c (compatible): Makes avr-6 compatible only with itself.
+
+
+ * elf64-s390.c (elf_s390_check_relocs): Initialize
+ htab->elf.dynobj if necessary.
+
+
+ * syms.c (struct bfd_symbol): Add new flag BSF_INDIRECT_FUNCTION.
+ Remove redundant flag BFD_FORT_COMM_DEFAULT_VALUE. Renumber flags
+ to remove gaps.
+ (bfd_print_symbol_vandf): Return 'i' for BSF_INDIRECT_FUNCTION.
+ (bfd_decode_symclass): Likewise.
+ * elf.c (swap_out_syms): Translate BSF_INDIRECT_FUNCTION into
+ STT_IFUNC.
+ (elf_find_function): Treat STT_IFUNC in the same way as STT_FUNC.
+ (_bfd_elf_is_function_type): Likewise.
+ * elf32-arm.c (arm_elf_find_function): Likewise.
+ (elf32_arm_adjust_dynamic_symbol): Likewise.
+ (elf32_arm_swap_symbol_in): Likewise.
+ (elf32_arm_additional_program_headers): Likewise.
+ * elf32-i386.c (is_indirect_symbol): New function.
+ (elf_i386_check_relocs): Also generate dynamic relocs for
+ relocations against STT_IFUNC symbols.
+ (allocate_dynrelocs): Likewise.
+ (elf_i386_relocate_section): Likewise.
+ * elf64-x86-64.c (is_indirect_symbol): New function.
+ (elf64_x86_64_check_relocs): Also generate dynamic relocs for
+ relocations against STT_IFUNC symbols.
+ (allocate_dynrelocs): Likewise.
+ (elf64_x86_64_relocate_section): Likewise.
+ * elfcode.h (elf_slurp_symbol_table): Translate STT_IFUNC into
+ BSF_INDIRECT_FUNCTION.
+ * elflink.c (_bfd_elf_adjust_dynamic_reloc_section): Add support
+ for STT_IFUNC symbols.
+ (get_ifunc_reloc_section_name): New function.
+ (_bfd_elf_make_ifunc_reloc_section): New function.
+ * elf-bfd.h (struct bfd_elf_section_data): Add indirect_relocs field.
+ * bfd-in2.h: Regenerate.
+
+
+ * config.bfd: Add x86_64-*-darwin*
+
+
+ * hpux-core.c: Don't include sys/file.h.
+
+
+ * aoutx.h (NAME): Add case statements for bfd_mach_mips14000,
+ bfd_mach_mips16000.
+ * archures.c (bfd_architecture): Add .#defines for bfd_mach_mips14000,
+ bfd_mach_mips16000.
+ * bfd-in2.h: Regenerate.
+ * cpu-mips.c: Add enums I_mips14000, I_mips16000.
+ (arch_info_struct): Add refs to R14000, R16000.
+ * elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips14000,
+ bfd_mach_mips16000.
+ (mips_mach_extensions): Map R14000, R16000 to R10000.
+
+
+ * Add PIC support for CR16 target.
+ * elf32-cr16.c (R_CR16_GOT_REGREL20, R_CR16_GOTC_REGREL20 and
+ R_CR16_GLOB_DAT): New macros
+ (cr16_elf_howto_table): Add entries for for R_CR16_GOT_REGREL20,
+ R_CR16_GOTC_REGREL20 and R_CR16_GLOB_DAT.
+ (cr16_reloc_map): Ditto
+ (_bfd_cr16_elf_create_got_section): New function to create GOT section.
+ (_bfd_cr16_elf_create_dynamic_sections): New function to create dynamic
+ section.
+ (_bfd_cr16_elf_adjust_dynamic_symbol): New function to adjust symbol
+ defined by dynamic object.
+ (_bfd_cr16_elf_size_dynamic_sections): New function to find the size of
+ dynamic sections.
+ (_bfd_cr16_elf_finish_dynamic_symbol): New function to handle dynamic
+ symbols.
+ (_bfd_cr16_elf_finish_dynamic_symbol): New function to handle dynamic
+ sections.
+ (bfd_cr16_elf32_create_embedded_relocs): New function to create
+ embedded relocs in .emreloc section in memory for .data.rel section.
+ (_bfd_cr16_elf_reloc_type_class): New function for classify reloc types.
+ (cr16_elf_check_relocs): New function for checking reloc types in first
+ phase.
+ (cr16_elf_final_link_relocate): Update for handling the new reloc types
+ R_CR16_GOT_REGREL20 and R_CR16_GOTC_REGREL20.
+ (elf32_cr16_relax_section): Update relax implementation.
+ * reloc.c (bfd_reloc_code_type): Add entries for R_CR16_GOT_REGREL20,
+ R_CR16_GOTC_REGREL20 and R_CR16_GLOB_DAT.
+ * bfd-in.h (bfd_boolean bfd_cr16_elf32_create_embedded_relocs): Declared
+ * libbfd.h, bfd-in2.h: Regenerate.
+
+
+ PR 7047
+ * configure.in: Bump version.
+ * configure: Regenerate.
+ * elflink.c (_bfd_elf_link_assign_sym_version): Continue matching
+ against version nodes when a global match is a wildcard. Similarly
+ continue matching on local wildcard matches, rather than only
+ continuing for "*". Have any global wildcard match override a
+ local wildcard match. Correct logic hiding unversioned symbol.
+ (bfd_elf_size_dynamic_sections): Update for changes to struct
+ bfd_elf_version_expr.
+
+
+ * configure.in: Deactivate large-file support on native x86-solaris
+ as well unless the user explicitly requested it.
+ * configure: Regenerate.
+
+
+ * elf32-arm.c (elf32_arm_final_link_relocate): Do not turn
+ branches to undefine weak symbols into branches to the next
+ instruction if creating PLT entries for those symbols.
+
+
+ * elflink.c (is_reloc_section): New function. Returns true if the
+ given name matches the name of the reloc-containing section
+ associated with the given section.
+ (get_dynamic_reloc_section_name): New function. Computes the name
+ of the section that contains the dynamic relocs associated with
+ the given section.
+ (_bfd_elf_get_dynamic_reloc_section): New function. Returns a
+ pointer to the section containing the dynamic relocs associated
+ with the given section.
+ (_bfd_elf_make_dynamic_reloc_section): New function. Creates a
+ section to contain the dynamic relocs associated with a given
+ section.
+ * elf-bfd.h: Prototype the new functions.
+ * elf-m10300.c (mn10300_elf_check_relocs): Use new functions.
+ (mn10300_elf_final_link_relocs): Likewise.
+ * elf32-arm.c (reloc_section_p): Delete - replaced by new
+ functions.
+ (elf32_arm_final_link_relocate): Use new functions.
+ (elf32_arm_check_relocs): Likewise.
+ * elf32-cris.c (cris_elf_relocate_section): Likewise.
+ (elf_cris_check_relocs): Likewise.
+ * elf32-hppa.c (elf32_hppa_check_relocs): Likewise.
+ * elf32-i370.c (i370_elf_check_relocs): Likewise.
+ (i370_elf_relocate_section): Likewise.
+ * elf32-i386.c (elf_i386_check_relocs): Likewise.
+ * elf32-m32r.c (m32r_elf_relocate_section): Likewise.
+ (m32r_elf_check_relocs): Likewise.
+ * elf32-m68k.c (elf_m68k_check_relocs): Likewise.
+ * elf32_ppc.c (ppc_elf_check_relocs): Likewise.
+ (ppc_elf_relocate_section): Likewise.
+ * elf32-s390.c (elf_s390_check_relocs): Likewise.
+ * elf32-sh.c (sh_elf_relocate_section): Likewise.
+ (sh_elf_check_relocs): Likewise.
+ * elf32-vax.c (elf_vax_check_relocs): Likewise.
+ (elf_vax_relocate_section): Likewise.
+ * elf64-alpha.c (elf64_alpha_check_relocs): Likewise.
+ * elf64-ppc.c (ppc64_elf_check_relocs): Likewise.
+ * elf64-s390.c (elf_s390_check_relocs): Likewise.
+ * elf64-sh64.c (sh_elf64_relocate_section): Likewise.
+ * elf64-x86-64.c (elf64_x86_64_check_relocs): Likewise.
+ * elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise.
+ * elf32-bfin.c (bfin_check_relocs): Remove redundant local
+ variable 'sreloc'.
+ (bfin_relocate_section): Likewise.
+ * elf32-v850.c (v850_elf_check_relocs): Likewise.
+
+
+ Implement TLS for CRIS.
+ * elf32-cris.c: Include limits.h.
+ (TLSHOWTO16): Redefine in terms of and move contents to...
+ (TLSHOWTO16X): New macro.
+ (TLSHOWTO16S, LGOT_REG_NDX, LGOT_DTP_NDX, LGOT_ALLOC_NELTS_FOR)
+ (elf_cris_hash_entry): New macros.
+ (cris_elf_howto_table): Make R_CRIS_16_DTPREL,
+ R_CRIS_16_GOT_TPREL, R_CRIS_16_TPREL check overflow for signed,
+ not unsigned values.
+ (cris_info_to_howto_rela): Make r_type a enum elf_cris_reloc_type,
+ not unsigned int.
+ (struct elf_cris_link_hash_entry): New members reg_got_refcount,
+ tprel_refcount, and dtp_refcount.
+ (struct elf_cris_link_hash_table): New member dtpmod_refcount.
+ (elf_cris_link_hash_newfunc): Initialize new members.
+ (elf_cris_link_hash_table_create): Similar.
+ (cris_final_link_relocate, elf_cris_reloc_type_class): Use a
+ temporary variable when testing the relocation type.
+ (cris_elf_gc_mark_hook): Ditto. Add default case where needed.
+ (cris_elf_gc_sweep_hook): Ditto. Handle reference-counting for
+ the new assembly-generated relocs. Rewrite refcount handling to
+ set temporary variables to pointers to reloc-specific variables
+ and entry size and common code for the update.
+ (additional_relocation_error_msg_count): New variable.
+ (cris_elf_relocate_section): Use a function-local variable srelgot
+ for the .rela.got section instead of looking it up for every need.
+ Make r_type a enum elf_cris_reloc_type, not int. Actually set
+ symname for non-local symbols. Handle new assembly-generated
+ relocs. For overflow, emit additional messages for the new 16-bit
+ relocs as well as R_CRIS_16_GOTPLT and R_CRIS_16_GOT.
+ (elf_cris_finish_dynamic_symbol): Use elf_cris_finish_dynamic_symbol
+ instead of plain casts. Check new hash entry member
+ reg_got_refcount when checking whether to emit a GOT entry.
+ (elf_cris_finish_dynamic_sections): Update head comment to warn
+ about emitting relocs here. Use a temporary variable when testing
+ the relocation type.
+ (elf_cris_discard_excess_program_dynamics)
+ (elf_cris_adjust_gotplt_to_got): Handle reference counting change
+ regarding h->reg_got_refcount.
+ (cris_elf_check_relocs): Rewrite refcount handling to set
+ temporary variables and entry size and common code for the update
+ for local symbols. Use new macro elf_cris_hash_entry. Adjust
+ allocation for change in reference counting of GOT entries for
+ local symbols.
+ (elf_cris_size_dynamic_sections): Adjust calculated size of
+ .got.plt and .rela.got if we need a GOT entry for a
+ R_CRIS_DTPMOD relocation.
+ (elf_cris_got_elt_size): New function.
+ (elf_backend_got_elt_size): Define.
+
+
+ * xtensa-isa.c (xtensa_state_is_shared_or): New function.
+
+
+ * elf-bfd.h (struct elf_backend_data): New member got_elt_size.
+ (_bfd_elf_default_got_elt_size): Declare.
+ * elflink.c (struct alloc_got_off_arg): Replace member got_elt_size
+ by new member info.
+ (elf_gc_allocate_got_offsets): Adjust for calling bed->got_elt_size
+ to get the element size instead of using a gofarg entry.
+ (bfd_elf_gc_common_finalize_got_offsets): Similar.
+ (_bfd_elf_default_got_elt_size): New function.
+ * elfxx-target.h: New macro elf_backend_got_elt_size.
+ (elfNN_bed): Use it.
+
+
+ * bfdwin.c: Fix comment.
+
+
+ * bfd.c (is32bit): Use architecture information for non-ELF
+ targets.
+
+
+ * elf32-ppc.c (allocate_dynrelocs): Always use tlsld_got for
+ TLS_LD even when symbol is used with other TLS reloc types.
+ (ppc_elf_relocate_section): Bypass symbol checks when using tlsld_got.
+ Leave addend zero on LD DTPMOD dynamic reloc.
+
+
+ * xtensa-modules.c (sysregs): Add MMID, VECBASE, EPC5, EPC6, EPC7,
+ EXCSAVE5, EXCSAVE6, EXCSAVE7, EPS5, EPS6, EPS7, CPENABLE,
+ SCOMPARE1, and THREADPTR registers.
+ (NUM_SYSREGS, MAX_USER_REG): Update.
+ (states): Change width of INTERRUPT, WindowBase, WindowStart, and
+ INTENABLE. Add VECBASE, EPC5, EPC6, EPC7, EXCSAVE5, EXCSAVE6,
+ EXCSAVE7, EPS6, EPS6, EPS7, THREADPTR, CPENABLE, and SCOMPARE1 states.
+ (NUM_STATES): Update.
+ (enum xtensa_state_id): Add entries for new states.
+ (enum xtensa_field_id): Add entries for xt_wbr15_imm and xt_wbr18_imm
+ fields, along with functions to extract and set them.
+ (regfiles): Change number of AR registers to 32.
+ (Operand_ar0_encode, Operand_ar4_encode, Operand_ar8_encode,
+ Operand_ar12_encode, Operand_ars_entry_encode): Update register mask.
+ (operands): Add entries for tp7, xt_wbr15_label, xt_wbr18_label,
+ xt_wbr15_imm, and xt_wbr18_imm operands, along with functions to
+ encode and decode them.
+ (enum xtensa_operand_id): Add entries for new operands.
+ (Iclass_xt_iclass_rfi_stateArgs): Add EPC5, EPC6, EPC7, EPS5, EPS6, and
+ EPC7 states.
+ (Iclass_xt_iclass_rfdo_stateArgs): Replace EPC4 and EPS4 by EPC6 and
+ EPS6, respectively.
+ (iclasses): Add entries for rur_threadptr, wur_threadptr,
+ xt_iclass_wsr_176, xt_iclass_rsr_epc5, xt_iclass_wsr_epc5,
+ xt_iclass_xsr_epc5, xt_iclass_rsr_excsave5, xt_iclass_wsr_excsave5,
+ xt_iclass_xsr_excsave5, xt_iclass_rsr_epc6, xt_iclass_wsr_epc6,
+ xt_iclass_xsr_epc6, xt_iclass_rsr_excsave6, xt_iclass_wsr_excsave6,
+ xt_iclass_xsr_excsave6, xt_iclass_rsr_epc7, xt_iclass_wsr_epc7,
+ xt_iclass_xsr_epc7, xt_iclass_rsr_excsave7, xt_iclass_wsr_excsave7,
+ xt_iclass_xsr_excsave7, xt_iclass_rsr_eps5, xt_iclass_wsr_eps5,
+ xt_iclass_xsr_eps5, xt_iclass_rsr_eps6, xt_iclass_wsr_eps6,
+ xt_iclass_xsr_eps6, xt_iclass_rsr_eps7, xt_iclass_wsr_eps7,
+ xt_iclass_xsr_eps7, xt_iclass_rsr_vecbase, xt_iclass_wsr_vecbase,
+ xt_iclass_xsr_vecbase, xt_iclass_mul16, xt_iclass_wsr_mmid,
+ xt_iclass_icache_lock, xt_iclass_dcache_lock, xt_iclass_rsr_cpenable,
+ xt_iclass_wsr_cpenable, xt_iclass_xsr_cpenable, xt_iclass_clamp,
+ xt_iclass_minmax, xt_iclass_sx, xt_iclass_l32ai, xt_iclass_s32ri,
+ xt_iclass_s32c1i, xt_iclass_rsr_scompare1, xt_iclass_wsr_scompare1,
+ xt_iclass_xsr_scompare1, xt_iclass_div, and xt_iclass_mul32, along
+ with corresponding argument and state argument arrays. Change
+ number of state arguments for xt_iclass_rfi. Add arguments for
+ xt_iclass_rfdo.
+ (enum xtensa_iclass_id): Add entries for new iclasses.
+ (opcodes): Add entries for RUR_THREADPTR, WUR_THREADPTR, WSR_176,
+ RSR_EPC5, WSR_EPC5, XSR_EPC5, RSR_EXCSAVE5, WSR_EXCSAVE5, XSR_EXCSAVE5,
+ RSR_EPC6, WSR_EPC6, XSR_EPC6, RSR_EXCSAVE6, WSR_EXCSAVE6, XSR_EXCSAVE6,
+ RSR_EPC7, WSR_EPC7, XSR_EPC7, RSR_EXCSAVE7, WSR_EXCSAVE7, XSR_EXCSAVE7,
+ RSR_EPS5, WSR_EPS5, XSR_EPS5, RSR_EPS6, WSR_EPS6, XSR_EPS6, RSR_EPS7,
+ WSR_EPS7, XSR_EPS7, RSR_VECBASE, WSR_VECBASE, XSR_VECBASE, MUL16U,
+ MUL16S, WSR_MMID, IPFL, IHU, IIU, DPFL, DHU, DIU, RSR_CPENABLE,
+ WSR_CPENABLE, XSR_CPENABLE, CLAMPS, MIN, MAX, MINU, MAXU, SEXT, L32AI,
+ S32RI, S32C1I, RSR_SCOMPARE1, WSR_SCOMPARE1, XSR_SCOMPARE1, QUOU, QUOS,
+ REMU, REMS, and MULL opcodes, along with the corresponding functions
+ to encode them.
+ (enum xtensa_opcode_id): Add entries for new opcodes.
+ (Slot_inst_decode): Handle new opcodes.
+ (Slot_inst_get_field_fns, Slot_inst_set_field_fns): Add entries for
+ xt_wbr15_imm and xt_wbr18_imm fields.
+ (Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns): Likewise.
+ (Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns): Likewise.
+ (xtensa_modules): Update number of fields, operands, iclasses and
+ opcodes.
+
+
+ * elf.c (swap_out_syms) [USE_STT_COMMON]: Fix syntax error.
+
+
+ PR 7027
+ * elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Treat WPLT30 relocs
+ against local symbols in 64-bit binaries as if they were WDISP30
+ relocs.
+ (_bfd_sparc_elf_relocate_section): Likewise.
+
+
+ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Merge
+ half-precision attributes.
+ (elf32_arm_copy_one_eabi_other_attribute): New.
+ (elf32_arm_copy_other_attribute_list): New.
+
+
+ * dwarf2.c (read_section): Fix formatting.
+ (read_n_bytes): Remove unhelpful comment.
+ (read_indirect_string): Pass symbol table to read_section in case
+ the .debug_str section needs relocating.
+
+ PR 7037
+ * elf32-cr16.c (cr16_elf_howto_table): Zero the src_mask field of
+ the reloc descriptions.
+
+
+ PR 7022
+ * elf32-avr.c (bfd_elf_avr_final_write_processing):
+ Add missing break statements.
+
+
+ * xtensa-modules.c (xtensa_state_id): New enum, replacing STATE macros.
+ (xtensa_field_id, xtensa_regfile_id, xtensa_operand_id)
+ (xtensa_iclass_id, xtensa_opcode_id): New enums.
+ Replace hardcoded constants throughout this file with enum values.
+
+
+ * elf.c (assign_file_positions_for_load_sections): Use header_size
+ to avoid moving the load address of file headers.
+ (assign_file_positions_for_load_sections): Set header_size for
+ segments containing the file header.
+
+
+ * configure.com: Handle bfd_default_target_size, BFD_HOST_LONG_LONG,
+ BFD_HOST_64BIT_LONG_LONG, BFD_HOSTPTR_T, bfd_file_ptr.
+ Generate bfdver.h.
+ * vms-hdr.c (_bfd_vms_write_hdr): Use strdup/free instead of alloca.
+ * hosts/alphavms.h: Defines macros to bypass i18n.
+ * makefile.vms (OBJS): Update file list.
+ (DEFS): Remove VMS_DEBUG, const, add DEBUGDIR.
+ (CFLAGS): Update flags.
+ * bfdio.c (real_fopen): Add code specific to VMS: extract attributes
+ from modes.
+
* configure.in: Deactivate large-file support on native 32bit
PR 7023
* elf.c (bfd_section_from_shdr <SHT_SYMTAB>): Fail on invalid sh_info.
-
- * bfd.c (bfd_get_sign_extend_vma): Return 0 for mach-o.
-
* elf.c (assign_file_positions_for_non_load_sections): Consolidate
projects / binutils.git / blobdiff