End tic80 sanitization regions with "end-sanitize-tic80", not

[binutils.git] / opcodes / v850-opc.c

diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index aa358379d37f221f587b76f980ae43c9120e66be..59270ed3ea013e668bd9e7d4147124aa93de84ac 100644 (file)
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -74,19 +74,11 @@ const struct v850_operand v850_operands[] = {
 #define D7     (I16+1)
   { 7, 0, 0, 0, 0},
 
-/* The DISP9 field in a format 3 insn. */
-#define D9     (D7+1)
-  { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
-
 /* The DISP16 field in a format 6 insn. */
-#define D16_15 (D9+1)
+#define D16_15 (D7+1)
   { 16, 16, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, 
 
-/* The DISP22 field in a format 4 insn. */
-#define D22    (D16_15+1)
-  { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
-
-#define B3     (D22+1)
+#define B3     (D16_15+1)
 /* The 3 bit immediate field in format 8 insn.  */
   { 3, 11, 0, 0, 0 },
 
@@ -122,6 +114,17 @@ const struct v850_operand v850_operands[] = {
 #define D16    (SR2+1)
   { 16, 16, 0, 0, V850_OPERAND_SIGNED }, 
 
+/* The DISP22 field in a format 4 insn, relaxable. */
+#define D9_RELAX       (D16+1)
+  { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP },
+
+/* The DISP22 field in a format 4 insn.
+
+   This _must_ follow D9_RELAX; the assembler assumes that the longer
+   version immediately follows the shorter version for relaxing.  */
+#define D22    (D9_RELAX+1)
+  { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
+
 } ; 
 
 \f
@@ -132,7 +135,7 @@ const struct v850_operand v850_operands[] = {
 #define IF2    {I5, R2}
 
 /* conditional branch instruction format (Format III) */
-#define IF3    {D9}
+#define IF3    {D9_RELAX}
 
 /* 16-bit load/store instruction (Format IV) */
 #define IF4A   {D7, EP, R2}
@@ -265,6 +268,35 @@ const struct v850_opcode v850_opcodes[] = {
 { "br",                BOP(0x5),               BOP_MASK,       IF3, 0 },
 { "bsa",       BOP(0xd),               BOP_MASK,       IF3, 0 },
 
+/* Branch macros.
+
+   We use the short form in the opcode/mask fields.  The assembler
+   will twiddle bits as necessary if the long form is needed.  */
+
+       /* signed integer */
+{ "jgt",       BOP(0xf),               BOP_MASK,       IF3, 0 },
+{ "jge",       BOP(0xe),               BOP_MASK,       IF3, 0 },
+{ "jlt",       BOP(0x6),               BOP_MASK,       IF3, 0 },
+{ "jle",       BOP(0x7),               BOP_MASK,       IF3, 0 },
+       /* unsigned integer */
+{ "jh",                BOP(0xb),               BOP_MASK,       IF3, 0 },
+{ "jnh",       BOP(0x3),               BOP_MASK,       IF3, 0 },
+{ "jl",                BOP(0x1),               BOP_MASK,       IF3, 0 },
+{ "jnl",       BOP(0x9),               BOP_MASK,       IF3, 0 },
+       /* common */
+{ "je",                BOP(0x2),               BOP_MASK,       IF3, 0 },
+{ "jne",       BOP(0xa),               BOP_MASK,       IF3, 0 },
+       /* others */
+{ "jv",                BOP(0x0),               BOP_MASK,       IF3, 0 },
+{ "jnv",       BOP(0x8),               BOP_MASK,       IF3, 0 },
+{ "jn",                BOP(0x4),               BOP_MASK,       IF3, 0 },
+{ "jp",                BOP(0xc),               BOP_MASK,       IF3, 0 },
+{ "jc",                BOP(0x1),               BOP_MASK,       IF3, 0 },
+{ "jnc",       BOP(0x9),               BOP_MASK,       IF3, 0 },
+{ "jz",                BOP(0x2),               BOP_MASK,       IF3, 0 },
+{ "jnz",       BOP(0xa),               BOP_MASK,       IF3, 0 },
+{ "jsa",       BOP(0xd),               BOP_MASK,       IF3, 0 },
+
 { "jmp",       one(0x0060),            one(0xffe0),    { R1}, 1 },
 { "jr",                one(0x0780),            two(0xffc0,0x0001),{ D22 }, 0 },
 { "jarl",      one(0x0780),            two(0x07c0,0x0001),{ D22, R2 }, 0 },