/* Target-dependent code for Moxie.
- Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ Copyright (C) 2009-2017 Free Software Foundation, Inc.
This file is part of GDB.
/* Moxie register names. */
-char *moxie_register_names[] = {
+static const char *moxie_register_names[] = {
"$fp", "$sp", "$r0", "$r1", "$r2",
"$r3", "$r4", "$r5", "$r6", "$r7",
"$r8", "$r9", "$r10", "$r11", "$r12",
/* Insert a single step breakpoint. */
-static int
-moxie_software_single_step (struct frame_info *frame)
+static VEC (CORE_ADDR) *
+moxie_software_single_step (struct regcache *regcache)
{
- struct gdbarch *gdbarch = get_frame_arch (frame);
- struct address_space *aspace = get_frame_address_space (frame);
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
CORE_ADDR addr;
gdb_byte buf[4];
uint16_t inst;
uint32_t tmpu32;
ULONGEST fp;
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- struct regcache *regcache = get_current_regcache ();
+ VEC (CORE_ADDR) *next_pcs = NULL;
- addr = get_frame_pc (frame);
+ addr = regcache_read_pc (regcache);
inst = (uint16_t) moxie_process_readu (addr, buf, 2, byte_order);
case 0x09: /* bleu */
/* Insert breaks on both branches, because we can't currently tell
which way things will go. */
- insert_single_step_breakpoint (gdbarch, aspace, addr + 2);
- insert_single_step_breakpoint (gdbarch, aspace, addr + 2 + INST2OFFSET(inst));
+ VEC_safe_push (CORE_ADDR, next_pcs, addr + 2);
+ VEC_safe_push (CORE_ADDR, next_pcs,
+ addr + 2 + INST2OFFSET(inst));
break;
default:
{
else
{
/* This is a Form 2 instruction. They are all 16 bits. */
- insert_single_step_breakpoint (gdbarch, aspace, addr + 2);
+ VEC_safe_push (CORE_ADDR, next_pcs, addr + 2);
}
}
else
case 0x32: /* udiv.l */
case 0x33: /* mod.l */
case 0x34: /* umod.l */
- insert_single_step_breakpoint (gdbarch, aspace, addr + 2);
+ VEC_safe_push (CORE_ADDR, next_pcs, addr + 2);
break;
/* 32-bit instructions. */
case 0x37: /* sto.b */
case 0x38: /* ldo.s */
case 0x39: /* sto.s */
- insert_single_step_breakpoint (gdbarch, aspace, addr + 4);
+ VEC_safe_push (CORE_ADDR, next_pcs, addr + 4);
break;
/* 48-bit instructions. */
case 0x20: /* ldi.s (immediate) */
case 0x22: /* lda.s */
case 0x24: /* sta.s */
- insert_single_step_breakpoint (gdbarch, aspace, addr + 6);
+ VEC_safe_push (CORE_ADDR, next_pcs, addr + 6);
break;
/* Control flow instructions. */
case 0x03: /* jsra */
case 0x1a: /* jmpa */
- insert_single_step_breakpoint (gdbarch, aspace,
- moxie_process_readu (addr + 2,
- buf, 4,
- byte_order));
+ VEC_safe_push (CORE_ADDR, next_pcs,
+ moxie_process_readu (addr + 2, buf, 4, byte_order));
break;
case 0x04: /* ret */
regcache_cooked_read_unsigned (regcache, MOXIE_FP_REGNUM, &fp);
- insert_single_step_breakpoint (gdbarch, aspace,
- moxie_process_readu (fp + 4,
- buf, 4,
- byte_order));
+ VEC_safe_push (CORE_ADDR, next_pcs,
+ moxie_process_readu (fp + 4, buf, 4, byte_order));
break;
case 0x19: /* jsr */
case 0x25: /* jmp */
regcache_raw_read (regcache,
(inst >> 4) & 0xf, (gdb_byte *) & tmpu32);
- insert_single_step_breakpoint (gdbarch, aspace,
- tmpu32);
+ VEC_safe_push (CORE_ADDR, next_pcs, tmpu32);
break;
case 0x30: /* swi */
}
}
- return 1;
+ return next_pcs;
}
/* Implement the "read_pc" gdbarch method. */