4 * txvu.h (txvu_opcode): insert/extract/print take pointer to
5 instruction rather than instruction itself. Result of insert is
6 `void'. Add decls for dma, pke, gpuif support.
11 * cgen.h: Add prototypes for cgen_save_fixups(),
12 cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype
13 of cgen_asm_finish_insn() to return a char *.
17 * cgen.h: Formatting changes to improve readability.
21 * cgen.h (*): Clean up pass over `struct foo' usage.
22 (CGEN_ATTR): Make unsigned char.
23 (CGEN_ATTR_TYPE): Update.
24 (CGEN_ATTR_{ENTRY,TABLE}): New types.
25 (cgen_base): Move member `attrs' to cgen_insn.
26 (CGEN_KEYWORD): New member `null_entry'.
27 (CGEN_{SYNTAX,FORMAT}): New types.
28 (cgen_insn): Format and syntax separated from each other.
39 * d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for
40 2 word load/store, ADDppp/SUBppp, 16/32 bit multiply. Make
41 flags_{used,set} long.
42 (d30v_operand): Make flags field long.
47 * m68k.h: Fix comment describing operand types.
52 * d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move
53 everything else after down.
58 * d10v.h (OPERAND_FLAG): Split into:
59 (OPERAND_FFLAG, OPERAND_CFLAG) .
63 * mips.h (struct mips_opcode): Changed comments to reflect new
69 * mips.h (INSN_4900): Added.
74 * mips.h: Added to comments a quick-ref list of all assigned
75 operand type characters.
76 (OP_{MASK,SH}_PERFREG): New macros.
78 (OP_{MASK,SH}_{VECBYTE,VECALIGN}): New macros for VR5400
84 * sparc.h: Add '_' and '/' for v9a asr's.
89 * h8300.h: Bit ops with absolute addresses not in the 8 bit
90 area are not available in the base model (H8/300).
94 * m68k.h: Remove documentation of ` operand specifier.
98 * m68k.h: Document q and v operand specifiers.
102 * v850.h (struct v850_opcode): Add processors field.
103 (PROCESSOR_V850, PROCESSOR_ALL): New bit constants.
105 (PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants.
106 (PROCESSOR_V850EA): New bit constants.
112 Merge changes from Martin Hunt:
114 * d30v.h: Allow up to 64 control registers. Add
117 * d30v.h (LONG_Db): New form for delayed branches.
119 * d30v.h: (LONG_Db): New form for repeati.
121 * d30v.h (SHORT_D2B): New form.
123 * d30v.h (SHORT_A2): New form.
125 * d30v.h (OPERAND_2REG): Add new operand to indicate 2
126 registers are used. Needed for VLIW optimization.
131 * cgen.h: Move assembler interface section
132 up so cgen_parse_operand_result is defined for cgen_parse_address.
133 (cgen_parse_address): Update prototype.
137 * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed.
141 * i386.h (two_byte_segment_defaults): Correct base register 5 in
142 modes 1 and 2 to be ss rather than ds. From Gabriel Paubert
145 * i386.h: Set ud2 to 0x0f0b. From Gabriel Paubert
148 * i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert
151 * i386.h (JUMP_ON_CX_ZERO): Uncomment (define again).
152 (JUMP_ON_ECX_ZERO): Remove commented out macro.
156 * v850.h (V850_NOT_R0): New flag.
160 * v850.h (struct v850_opcode): Remove flags field.
164 * v850.h (struct v850_opcode): Add flags field.
165 (struct v850_operand): Extend meaning of 'bits' and 'shift'
169 (V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags.
170 (V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags.
179 * sparc.h (sparc_opcodes): Declare as const.
183 * mips.h (FP_S, FP_D): Define. Bitmasks indicating if an insn
184 uses single or double precision floating point resources.
185 (INSN_NO_ISA, INSN_ISA1): Define.
186 (cpu specific INSN macros): Tweak into bitmasks outside the range
191 * i386.h: Fix pand opcode.
195 * mips.h: Widen INSN_ISA and move it to a more convenient
196 bit position. Add INSN_3900.
200 * mips.h (struct mips_opcode): added new field membership.
204 * i386.h (movd): only Reg32 is allowed.
206 * i386.h: add fcomp and ud2. From Wayne Scott
211 * i386.h: Add MMX instructions.
215 * i386.h: Remove W modifier from conditional move instructions.
219 * i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp
220 with no arguments to match that generated by the UnixWare
225 * cgen.h (<cpu>_cgen_assemble_insn): New arg for errmsg.
226 (cgen_parse_operand_fn): Declare.
227 (cgen_init_parse_operand): Declare.
228 (cgen_parse_operand): Renamed from cgen_asm_parse_operand,
230 (enum cgen_parse_operand_result): Renamed from cgen_asm_result.
231 (enum cgen_parse_operand_type): New enum.
235 * i386.h: Revert last patch for the NON_BROKEN_OPCODES cases.
243 * i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and
248 * v850.h (extract): Make unsigned.
256 * i386.h: Change DW to W for cmpxchg and xadd, since they don't
257 take a direction bit.
259 start-sanitize-coldfire
262 * m68k.h (mcfmac, mcfdiv): New macros.
264 end-sanitize-coldfire
267 * sparc.h (sparc_opcode_lookup_arch): Use full prototype.
271 * sparc.h: Include <ansidecl.h>. Update function declarations to
272 use prototypes, and to use const when appropriate.
276 * mn10300.h (MN10300_OPERAND_RELAX): Define.
280 * d10v.h: Change pre_defined_registers to
281 d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
285 * mips.h: Add macros for cop0, cop1 cop2 and cop3.
286 Change mips_opcodes from const array to a pointer,
287 and change bfd_mips_num_opcodes from const int to int,
288 so that we can increase the size of the mips opcodes table
294 * d30v.h (FLAG_X): Remove unused flag.
304 * tic80.h (PDS_NAME): Macro to access name field of predefined symbols.
305 (PDS_VALUE): Macro to access value field of predefined symbols.
306 (tic80_next_predefined_symbol): Add prototype.
318 * tic80.h (tic80_symbol_to_value): Change prototype to match
319 change in function, added class parameter.
323 * tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80
324 endmask fields, which are somewhat weird in that 0 and 32 are
325 treated exactly the same.
329 * tic80.h: Change all the OPERAND defines to use the form (1 << X)
330 rather than a constant that is 2**X. Reorder them to put bits for
331 operands that have symbolic names in the upper bits, so they can
332 be packed into an int where the lower bits contain the value that
333 corresponds to that symbolic name.
334 (predefined_symbo): Add struct.
335 (tic80_predefined_symbols): Declare array of translations.
336 (tic80_num_predefined_symbols): Declare size of that array.
337 (tic80_value_to_symbol): Declare function.
338 (tic80_symbol_to_value): Declare function.
343 * mn10200.h (MN10200_OPERAND_RELAX): Define.
348 * tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot
349 be the destination register.
353 * tic80.h (struct tic80_opcode): Change "format" field to "flags".
354 (FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete.
355 (TIC80_VECTOR): Define a flag bit for the flags. This one means
356 that the opcode can have two vector instructions in a single
357 32 bit word and we have to encode/decode both.
361 * tic80.h (TIC80_OPERAND_PCREL): Renamed from
362 TIC80_OPERAND_RELATIVE for PC relative.
363 (TIC80_OPERAND_BASEREL): New flag bit for register
368 * tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands.
372 * tic80.h (TIC80_OPERAND_SCALED): Operand may have optional
373 ":s" modifier for scaling.
377 * tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m".
378 (TIC80_OPERAND_M_LI): Ditto
382 * tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ.
383 (TIC80_OPERAND_CC): New define for condition code operand.
384 (TIC80_OPERAND_CR): New define for control register operand.
388 * tic80.h (struct tic80_opcode): Name changed.
389 (struct tic80_opcode): Remove format field.
390 (struct tic80_operand): Add insertion and extraction functions.
391 (TIC80_OPERAND_*): Remove old bogus values, start adding new
398 * v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust
399 type IV instruction offsets.
409 * mn10200.h (MN10200_OPERAND_NOCHECK): Define.
413 * mn10200.h: Fix comment, mn10200_operand not powerpc_operand.
414 * mn10300.h: Fix comment, mn10300_operand not powerpc_operand.
415 * v850.h: Fix comment, v850_operand not powerpc_operand.
419 * mn10200.h: Flesh out structures and definitions needed by
420 the mn10200 assembler & disassembler.
424 * mips.h: Add mips16 definitions.
428 * m68k.h: Document new <, >, m, n, o and p operand specifiers.
432 * mn10300.h (MN10300_OPERAND_PCREL): Define.
433 (MN10300_OPERAND_MEMADDR): Define.
437 * mn10300.h (MN10300_OPERAND_REG_LIST): Define.
441 * mn10300.h (MN10300_OPERAND_SPLIT): Define.
445 * mn10300.h (MN10300_OPERAND_EXTENDED): Define.
449 * mn10300.h (MN10300_OPERAND_REPEATED): Define.
453 * alpha.h: Don't include "bfd.h"; private relocation types are now
454 negative to minimize problems with shared libraries. Organize
455 instruction subsets by AMASK extensions and PALcode
457 (struct alpha_operand): Move flags slot for better packing.
461 * v850.h (V850_OPERAND_RELAX): New operand flag.
465 * mn10300.h (FMT_*): Move operand format definitions
470 * mn10300.h (MN10300_OPERAND_PAREN): Define.
474 * mn10300.h (mn10300_opcode): Add "format" field.
475 (MN10300_OPERAND_*): Define.
480 * mn10200.h, mn10300.h: New files.
484 * mn10x00.h: New file.
488 * v850.h: Add new flag to indicate this instruction uses a PC
493 * h8300.h (stmac): Add missing instruction.
497 * v850.h (v850_opcode): Remove "size" field. Add "memop"
502 * v850.h (V850_OPERAND_EP): Define.
504 * v850.h (v850_opcode): Add size field.
508 * v850.h (v850_operands): Add insert and extract fields, pointers
509 to functions used to handle unusual operand encoding.
510 (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC,
511 V850_OPERAND_SIGNED): Defined.
515 * v850.h (v850_operands): Add flags field.
516 (OPERAND_REG, OPERAND_NUM): Defined.
524 * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
525 OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
526 OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
527 OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
528 OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
533 * hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept
534 a 3 bit space id instead of a 2 bit space id.
538 * d10v.h: Add some additional defines to support the
539 assembler in determining which operations can be done in parallel.
543 * h8300.h (SN): Define.
544 (eepmov.b): Renamed from "eepmov"
545 (nop, bpt, rte, rts, sleep, clrmac): These have no size associated
550 * d10v.h (OPERAND_SHIFT): New operand flag.
554 * d10v.h: Changes for divs, parallel-only instructions, and
559 * d10v.h (pd_reg): Define. Putting the definition here allows
560 the assembler and disassembler to share the same struct.
564 * i960.h (i960_opcodes): "halt" takes an argument. From Stephen
573 * h8300.h (band, bclr): Force high bit of immediate nibble to zero.
577 * m68k.h (mcf5200): New macro.
578 Document names of coldfire control registers.
582 * h8300.h (SRC_IN_DST): Define.
584 * h8300.h (UNOP3): Mark the register operand in this insn
585 as a source operand, not a destination operand.
586 (SHIFT_2, SHIFT_IMM): Remove. Eliminate all references.
587 (UNOP3): Change SHIFT_IMM to IMM for H8/S bitops. Mark
588 register operand with SRC_IN_DST.
596 * rs6k.h: Remove obsolete file.
600 * i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp,
601 fdivp, and fdivrp. Add ffreep.
605 * h8300.h: Reorder various #defines for readability.
606 (ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define.
607 (BITOP): Accept additional (unused) argument. All callers changed.
610 (ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes.
612 * h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define.
613 (O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define.
614 (BITOP, EBITOP): Handle new H8/S addressing modes for
616 (UNOP3): Handle new shift/rotate insns on the H8/S.
617 (insns using exr): New instructions.
618 (tas, mac, ldmac, clrmac, ldm, stm): New instructions.
622 * h8300.h (add.l): Undo Apr 5th change. The manual I had
627 * h8300.h (START): Remove.
628 (MEMRELAX): Define. Mark absolute memory operands in mov.b, mov.w
629 and mov.l insns that can be relaxed.
633 * i386.h: Remove Abs32 from lcall.
637 * sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro.
639 Mark X,Y opcode letters as in use.
643 * sparc.h (F_FLOAT, F_FBR): Define.
647 * h8300.h (ABS8MEM): Renamed from ABSMOV. Remove ABSMOV
649 (ABS8SRC,ABS8DST): Add ABS8MEM.
650 (add.l): Fix reg+reg variant.
651 (eepmov.w): Renamed from eepmovw.
652 (ldc,stc): Fix many cases.
656 * sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.
660 * sparc.h (O): Mark operand letter as in use.
664 * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare.
665 Mark operand letters uU as in use.
669 * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET.
670 (sparc_opcode_arch): Delete member `conflicts'. Add `supported'.
671 (SPARC_OPCODE_SUPPORTED): New macro.
672 (SPARC_OPCODE_CONFLICT_P): Rewrite.
677 * sparc.h (sparc_opcode_lookup_arch) Make return type in
678 declaration consistent with return type in definition.
682 * i386.h (i386_optab): Remove Data32 from pushf and popf.
686 * i386.h (i386_regtab): Add 80486 test registers.
690 * i960.h (I_HX): Define.
691 (i960_opcodes): Add HX instruction.
695 * i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw,
700 * sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture.
701 (SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P.
702 (bfd_* defines): Delete.
703 (sparc_opcode_archs): Replaces architecture_pname.
704 (sparc_opcode_lookup_arch): Declare.
705 (NUMOPCODES): Delete.
709 * sparc.h (enum sparc_architecture): Add v9a.
710 (ARCHITECTURES_CONFLICT_P): Update.
714 * i386.h: Added Pentium Pro instructions.
718 * m68k.h: Document new 'W' operand place.
722 * hppa.h: Add lci and syncdma instructions.
726 * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific
731 * ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for
732 assembler's -mcom and -many switches.
736 * i386.h: Fix cmpxchg8b extension opcode description.
740 * i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b,
745 * m68k.h: Change comment: split type P into types 0, 1 and 2.
749 * sparc.h (sparc_{encode,decode}_prefetch): Declare.
753 * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare.
759 * m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the
760 declarations. Remove F_ALIAS and flag field of struct
761 m68k_opcode. Change arch field of struct m68k_opcode to unsigned
762 int. Make name and args fields of struct m68k_opcode const.
766 * sparc.h (F_NOTV9): Define.
770 * mips.h (INSN_4010): Define.
774 * m68k.h (TBL1): Reverse sense of "round" argument in result.
777 * m68k.h: Fix argument descriptions of coprocessor
778 instructions to allow only alterable operands where appropriate.
779 [!NO_DEFAULT_SIZES]: An omitted size defaults to `w'.
780 (m68k_opcode_aliases): Add more aliases.
784 * m68k.h: Added explcitly short-sized conditional branches, and a
785 bunch of aliases (fmov*, ftest*, tdivul) to support gcc's
786 svr4-based configurations.
791 * i386.h: added missing Data16/Data32 flags to a few instructions.
795 * mips.h (OP_MASK_FR, OP_SH_FR): Define.
796 (OP_MASK_BCC, OP_SH_BCC): Define.
797 (OP_MASK_PREFX, OP_SH_PREFX): Define.
798 (OP_MASK_CCC, OP_SH_CCC): Define.
799 (INSN_READ_FPR_R): Define.
804 * m68k.h (enum m68k_architecture): Deleted.
805 (struct m68k_opcode_alias): New type.
806 (m68k_opcodes): Now const. Deleted opcode aliases with exactly
807 matching constraints, values and flags. As a side effect of this,
808 the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far
809 as I know were never used, now may need re-examining.
810 (numopcodes): Now const.
811 (m68k_opcode_aliases, numaliases): New variables.
813 [DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and
814 m68k_opcode_aliases; update declaration of m68k_opcodes.
818 * hppa.h (delay_type): Delete unused enumeration.
819 (pa_opcode): Replace unused delayed field with an architecture
821 (pa_opcodes): Mark each instruction as either PA1.0 or PA1.1.
825 * mips.h (INSN_ISA4): Define.
829 * mips.h (M_DLA_AB, M_DLI): Define.
833 * hppa.h (fstwx): Fix single-bit error.
837 * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define.
841 * i386.h: added cpuid instruction , and dr[0-7] aliases for the
848 * i386.h (MOV_AX_DISP32): New macro.
849 (i386_optab): Added Data16 and Data32 as needed. Added "w" forms
850 of several call/return instructions.
851 (ADDR_PREFIX_OPCODE): New macro.
857 * ../include/opcode/vax.h (struct vot_wot, field `args'): make
858 it pointer to const char;
859 (struct vot, field `name'): ditto.
863 * vax.h: Supply and properly group all values in end sentinel.
867 * mips.h (INSN_ISA, INSN_4650): Define.
871 * a29k.h: Add operand type 'I' for `inv' and `iretinv'. On
872 systems with a separate instruction and data cache, such as the
873 29040, these instructions take an optional argument.
877 * mips.h (INSN_STORE_MEMORY): Correct value to not conflict with
882 * mips.h (INSN_STORE_MEMORY): Define.
886 * sparc.h: Document new operand type 'x'.
890 * i960.h (I_CX2): New instruction category. It includes
891 instructions available on Cx and Jx processors.
892 (I_JX): New instruction category, for JX-only instructions.
893 (i960_opcodes): Put eshro and sysctl in I_CX2 category. Added
894 Jx-only instructions, in I_JX category.
898 * ns32k.h (endop): Made pointer const too.
902 * ns32k.h: Drop Q operand type as there is no correct use
903 for it. Add I and Z operand types which allow better checking.
907 * h8300.h (xor.l) :fix bit pattern.
908 (L_2): New size of operand.
913 * m68k.h: Move "trap" before "tpcc" to change disassembly.
917 * sparc.h: Include v9 definitions.
921 * m68k.h (m68060): Defined.
922 (m68040up, mfloat, mmmu): Include it.
923 (struct m68k_opcode): Widen `arch' field.
924 (m68k_opcodes): Updated for M68060. Removed comments that were
925 instructions commented out by "JF" years ago.
929 * m68k.h (struct m68k_opcode): Shorten `arch' field to 8 bits, and
930 add a one-bit `flags' field.
931 (F_ALIAS): New macro.
935 * h8300.h (dec, inc): Get encoding right.
939 * ppc.h (struct powerpc_operand): Removed signedp field; just use
941 (PPC_OPERAND_SIGNED): Define.
942 (PPC_OPERAND_SIGNOPT): Define.
946 * i386.h (IS_JUMP_ON_ECX_ZERO, "jcxz" pattern): Operand size
951 * i386.h: Reverse last change. It'll be handled in gas instead.
955 * i386.h (sar): Disabled the two-operand Imm1 form, since it was
956 slower on the 486 and used the implicit shift count despite the
957 explicit operand. The one-operand form is still available to get
958 the shorter form with the implicit shift count.
962 * hppa.h: Fix typo in fstws arg string.
966 * ppc.h (struct powerpc_opcode): Make operands field unsigned.
970 * ppc.h (PPC_OPCODE_601): Define.
974 * hppa.h (addb): Use '@' for addb and addib pseudo ops.
975 (so we can determine valid completers for both addb and addb[tf].)
977 * hppa.h (xmpyu): No floating point format specifier for the
982 * ppc.h (PPC_OPERAND_NEXT): Define.
983 (PPC_OPERAND_NEGATIVE): Change value to make room for above.
984 (struct powerpc_macro): Define.
985 (powerpc_macros, powerpc_num_macros): Declare.
989 * ppc.h: New file. Header file for PowerPC opcode table.
993 * hppa.h: More minor template fixes for sfu and copr (to allow
994 for easier disassembly).
996 * hppa.h: Fix templates for all the sfu and copr instructions.
1000 * i386.h (push): Permit Imm16 operand too.
1004 * h8300.h (andc): Exists in base arch.
1009 * hppa.h: #undef NONE to avoid conflict with hiux include files.
1013 * hppa.h: Add FP quadword store instructions.
1017 * mips.h: (M_J_A): Added.
1022 * mips.h (OP_MASK_CACHE, OP_SH_CACHE): Define. From Ted Lemon
1027 * hppa.h: Immediate field in probei instructions is unsigned,
1028 not low-sign extended.
1032 * m88k.h (RRI10MASK): Change from 0xfc00ffe0 to 0xfc00fc00.
1036 * i386.h: Add "fxch" without operand.
1040 * mips.h (M_JAL_1, M_JAL_2, M_JAL_A): Added.
1044 * hppa.h: Add gfw and gfr to the opcode table.
1048 * m88k.h: extended to handle m88110.
1052 * hppa.h (be, ble): Use operand type 'z' to denote absolute branch
1057 * i960.h (i960_opcodes): Properly bracket initializers.
1061 * m88k.h (BOFLAG): rewrite to avoid nested comment.
1065 * m68k.h (two): Protect second argument with parentheses.
1069 * i386.h (i386_optab): Added new instruction "rsm" (for i386sl).
1070 Deleted old in/out instructions in "#if 0" section.
1074 * i386.h (i386_optab): Properly bracket initializers.
1078 * hppa.h (pa_opcode): Use '|' for movb and movib insns. (From
1083 * i386.h (lcall): Accept Imm32 operand also.
1087 * mips.h (M_ABSU): Removed (absolute value of unsigned number??).
1092 * mips.h (INSN_*): Changed values. Removed unused definitions.
1093 Added INSN_COND_BRANCH_LIKELY, INSN_ISA2 and INSN_ISA3. Split
1094 INSN_LOAD_DELAY into INSN_LOAD_MEMORY_DELAY and
1095 INSN_LOAD_COPROC_DELAY. Split INSN_COPROC_DELAY into
1096 INSN_COPROC_MOVE_DELAY and INSN_COPROC_MEMORY_DELAY.
1097 (M_*): Added new values for r6000 and r4000 macros.
1098 (ANY_DELAY): Removed.
1102 * mips.h: Added M_LI_S and M_LI_SS.
1106 * h8300.h: Get some rare mov.bs correct.
1110 * sparc.h: Don't define const ourself; rely on ansidecl.h having
1115 * sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark
1116 jump instructions, for use in disassemblers.
1120 * m88k.h: Make bitfields just unsigned, not unsigned long or
1125 * hppa.h: New argument type 'y'. Use in various float instructions.
1129 * hppa.h (break): First immediate field is unsigned.
1131 * hppa.h: Add rfir instruction.
1135 * mips.h: Split the actual table out into ../../opcodes/mips-opc.c.
1139 * mips.h: Reworked the hazard information somewhat, and fixed some
1140 bugs in the instruction hazard descriptions.
1144 * m88k.h: Corrected a couple of opcodes.
1148 * mips.h: Replaced with version from Ralph Campbell and OSF. The
1149 new version includes instruction hazard information, but is
1150 otherwise reasonably similar.
1154 * h8300.h: Fix typo in UNOP3 (affected sh[al][lr].l).
1159 * hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage.
1160 Make the tables be the same for the following instructions:
1161 "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco",
1162 "sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o",
1163 "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio",
1164 "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs",
1165 "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt",
1166 "fcmp", and "ftest".
1168 * hppa.h: Make new and old tables the same for "break", "mtctl",
1169 "mfctl", "bb", "ssm", "rsm", "xmpyu", "fmpyadd", "fmpysub".
1170 Fix typo in last patch. Collapse several #ifdefs into a
1173 * hppa.h: Delete remaining OLD_TABLE code. Bring some
1174 of the comments up-to-date.
1176 * hppa.h: Update "free list" of letters and update
1177 comments describing each letter's function.
1181 * h8300.h: checkpoint, includes H8/300-H opcodes.
1186 * hppa.h: Rework single precision FP
1187 instructions so that they correctly disassemble code
1192 * i386.h (i386_optab, mov pattern): Remove Mem16 restriction from
1193 mov to allow instructions like mov ss,xyz(ecx) to assemble.
1197 * hppa.h: Use new version from Utah if OLD_TABLE isn't defined;
1198 gdb will define it for now.
1202 * sparc.h: Don't end enumerator list with comma.
1207 * mips.h (OP_MASK_COPZ, OP_SH_COPZ): Define.
1208 ("bc2t"): Correct typo.
1209 ("[ls]wc[023]"): Use T rather than t.
1210 ("c[0123]"): Define general coprocessor instructions.
1214 * m68k.h: Move split point for gcc compilation more towards
1219 * rs6k.h: Clean up instructions for primary opcode 19 (many were
1220 simply wrong, ics, rfi, & rfsvc were missing).
1221 Add "a" to opr_ext for "bb". Doc fix.
1226 * mips.h: Add casts, to suppress warnings about shifting too much.
1227 * m68k.h: Document the placement code '9'.
1231 * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which
1232 allows callers to break up the large initialized struct full of
1233 opcodes into two half-sized ones. This permits GCC to compile
1234 this module, since it takes exponential space for initializers.
1235 (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs.
1239 * a29k.h: Remove RCS crud, update GPL to v2, update copyrights.
1240 * convex.h: Added, from GDB's convx-opcode.h. Added CONST to all
1241 initialized structs in it.
1246 * m88k.h (PMEM): Avoid previous definition from <sys/param.h>.
1247 (AND): Change to AND_ to avoid ansidecl.h `AND' conflict.
1251 * mips.h: document "i" and "j" operands correctly.
1255 * mips.h: Removed endianness dependency.
1259 * h8300.h: include info on number of cycles per instruction.
1261 Mon Dec 21 21:29:08 1992 Stu Grossman (grossman at cygnus.com)
1263 * hppa.h: Move handy aliases to the front. Fix masks for extract
1264 and deposit instructions.
1268 * i386.h: accept shld and shrd both with and without the shift
1269 count argument, which is always %cl.
1271 Fri Nov 27 17:13:18 1992 Ken Raeburn (raeburn at cygnus.com)
1273 * i386.h (i386_optab_end, i386_regtab_end): Now const.
1274 (one_byte_segment_defaults, two_byte_segment_defaults,
1275 i386_prefixtab_end): Ditto.
1279 * vax.h (bb*): Use "v" (bitfield type), not "a" (address operand)
1284 * m68k.h: Define FIXED_SIZE_BRANCH, so bsr and bra instructions
1285 always use 16-bit offsets. Makes calculated-size jump tables
1290 * i386.h: Fix one-operand forms of in* and out* patterns.
1294 * m68k.h: Added CPU32 support.
1298 * mips.h (break): Disassemble the argument. Patch from
1303 * m68k.h: merged Motorola and MIT syntax.
1307 * m68k.h (pmove): make the tests less strict, the 68k book is
1312 * m68k.h (m68ec030): Defined as alias for 68030.
1313 (m68k_opcodes): New type characters "3" for 68030 MMU regs and "t"
1314 for immediate 0-7 added. Set up some opcodes (ptest, bkpt) to use
1315 them. Tightened description of "fmovex" to distinguish it from
1316 some "pmove" encodings. Added "pmove" for 68030 MMU regs, cleaned
1317 up descriptions that claimed versions were available for chips not
1318 supporting them. Added "pmovefd".
1322 * m68k.h: fix where the . goes in divull
1326 * m68k.h: the cas2 instruction is supposed to be written with
1327 indirection on the last two operands, which can be either data or
1328 address registers. Added a new operand type 'r' which accepts
1329 either register type. Added new cases for cas2l and cas2w which
1330 use them. Corrected masks for cas2 which failed to recognize use
1331 of address register.
1335 * m68k.h: Merged in patches (mostly m68040-specific) from
1338 * m68k.h: Merged m68kmri.h and m68k.h (using the former as a
1339 base). Also cleaned up duplicates, re-ordered instructions for
1340 the sake of dis-assembling (so aliases come after standard names).
1341 * m68kmri.h: Now just defines some macros, and #includes m68k.h.
1345 * m68kmri.h: added various opcodes. Moved jbxx to bxxes. Filled in
1350 * sparc.h: Moved tables to BFD library.
1352 * i386.h (i386_optab): Add fildq, fistpq aliases used by gcc.
1356 * h8300.h: Finish filling in all the holes in the opcode table,
1357 so that the Lucid C compiler can digest this as well...
1359 Fri Jun 26 21:27:17 1992 John Gilmore (gnu at cygnus.com)
1361 * i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases.
1362 Fix opcodes on various sizes of fild/fist instructions
1363 (16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix).
1364 Use tabs to indent for comments. Fixes suggested by Minh Tran-Le.
1366 Thu Jun 25 16:13:26 1992 Stu Grossman (grossman at cygnus.com)
1368 * h8300.h: Fill in all the holes in the opcode table so that the
1369 losing HPUX C compiler can digest this...
1371 Thu Jun 11 12:15:25 1992 John Gilmore (gnu at cygnus.com)
1373 * mips.h: Fix decoding of coprocessor instructions, somewhat.
1378 * sparc.h: Add new architecture variant sparclite; add its scan
1379 and divscc opcodes. Define ARCHITECTURES_CONFLICT_P macro.
1383 * mips.h: Add some more opcode synonyms (from Frank Yellin,
1388 * rs6k.h: New version from IBM (Metin).
1392 * rs6k.h: Fix incorrect extended opcode for instructions `fm'
1395 Tue Apr 7 13:38:47 1992 Stu Grossman (grossman at cygnus.com)
1397 * rs6k.h: Move from ../../gdb/rs6k-opcode.h.
1401 * m68k.h (one, two): Cast macro args to unsigned to suppress
1402 complaints from compiler and lint about integer overflow during
1405 Sun Mar 29 12:22:08 1992 John Gilmore (gnu at cygnus.com)
1407 * sparc.h (OP): Avoid signed overflow when shifting to high order bit.
1409 Fri Mar 6 00:22:38 1992 John Gilmore (gnu at cygnus.com)
1411 * mips.h: Make bitfield layout depend on the HOST compiler,
1412 not on the TARGET system.
1416 * i386.h: added inb, inw, outb, outw opcodes, added att syntax for
1417 scmp, slod, smov, ssca, ssto. Curtesy Minh Tran-Le
1420 Thu Jan 30 07:31:44 1992 Steve Chamberlain (sac at rtl.cygnus.com)
1422 * h8300.h: turned op_type enum into #define list
1424 Thu Jan 30 01:07:24 1992 John Gilmore (gnu at cygnus.com)
1426 * sparc.h: Remove "cypress" architecture. Remove "fitox" and
1427 similar instructions -- they've been renamed to "fitoq", etc.
1428 REALLY fix tsubcctv. Fix "fcmpeq" and "fcmpq" which had wrong
1429 number of arguments.
1430 * h8300.h: Remove extra ; which produces compiler warning.
1432 Tue Jan 28 22:59:22 1992 Stu Grossman (grossman at cygnus.com)
1434 * sparc.h: fix opcode for tsubcctv.
1436 Tue Jan 7 17:19:39 1992 K. Richard Pixley (rich at cygnus.com)
1438 * sparc.h: fba and cba are now aliases for fb and cb respectively.
1440 Fri Dec 27 10:55:50 1991 Per Bothner (bothner at cygnus.com)
1442 * sparc.h (nop): Made the 'lose' field be even tighter,
1443 so only a standard 'nop' is disassembled as a nop.
1445 Sun Dec 22 12:18:18 1991 Michael Tiemann (tiemann at cygnus.com)
1447 * sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is
1448 disassembled as a nop.
1450 Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com)
1452 * sparc.h: fix a typo.
1454 Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com)
1456 * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h,
1457 m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h,
1458 vax.h, ChangeLog: renamed from ../<foo>-opcode.h
1462 version-control: never