1 /* Simulator header for cgen parallel support.
2 Copyright (C) 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of the GNU instruction set simulator.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* Kinds of writes stored on the write queue. */
25 enum cgen_write_queue_kind {
26 CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
28 CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_SF_WRITE,
29 CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
30 CGEN_FN_XI_WRITE, CGEN_FN_PC_WRITE,
31 CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE,
32 CGEN_MEM_DF_WRITE, CGEN_MEM_XI_WRITE,
33 CGEN_FN_MEM_QI_WRITE, CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE,
34 CGEN_FN_MEM_DI_WRITE, CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE,
38 /* Element of the write queue. */
40 enum cgen_write_queue_kind kind; /* Used to select union member below. */
41 IADDR insn_address; /* Address of the insn performing the write. */
42 unsigned32 flags; /* Target specific flags. */
43 long word1; /* Target specific field. */
67 void (*function)(SIM_CPU *, UINT, UHI);
72 void (*function)(SIM_CPU *, UINT, USI);
77 void (*function)(SIM_CPU *, UINT, SF);
82 void (*function)(SIM_CPU *, UINT, DI);
87 void (*function)(SIM_CPU *, UINT, DF);
92 void (*function)(SIM_CPU *, UINT, SI *);
96 void (*function)(SIM_CPU *, USI);
125 void (*function)(SIM_CPU *, IADDR, SI, QI);
130 void (*function)(SIM_CPU *, IADDR, SI, HI);
135 void (*function)(SIM_CPU *, IADDR, SI, SI);
140 void (*function)(SIM_CPU *, IADDR, SI, DI);
145 void (*function)(SIM_CPU *, IADDR, SI, DF);
150 void (*function)(SIM_CPU *, IADDR, SI, SI *);
153 } CGEN_WRITE_QUEUE_ELEMENT;
155 #define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
156 #define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address)
157 #define CGEN_WRITE_QUEUE_ELEMENT_FLAGS(element) ((element)->flags)
158 #define CGEN_WRITE_QUEUE_ELEMENT_WORD1(element) ((element)->word1)
160 extern void cgen_write_queue_element_execute (
161 SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
164 /* Instance of the queue for parallel write-after support. */
165 /* FIXME: Should be dynamic? */
166 #define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now. */
170 CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
173 #define CGEN_WRITE_QUEUE_CLEAR(queue) ((queue)->index = 0)
174 #define CGEN_WRITE_QUEUE_INDEX(queue) ((queue)->index)
175 #define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
177 #define CGEN_WRITE_QUEUE_NEXT(queue) ( \
178 (queue)->index < CGEN_WRITE_QUEUE_SIZE \
179 ? &(queue)->q[(queue)->index++] \
180 : cgen_write_queue_overflow (queue) \
183 extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);
185 /* Functions for queuing writes. Used by semantic code. */
186 extern void sim_queue_bi_write (SIM_CPU *, BI *, BI);
187 extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
188 extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
189 extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);
191 extern void sim_queue_pc_write (SIM_CPU *, USI);
193 extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI);
194 extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, USI);
195 extern void sim_queue_fn_sf_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SF), UINT, SF);
196 extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
197 extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DF), UINT, DF);
198 extern void sim_queue_fn_xi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SI *), UINT, SI *);
199 extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI);
201 extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
202 extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
203 extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
204 extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI);
205 extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF);
206 extern void sim_queue_mem_xi_write (SIM_CPU *, SI, SI *);
208 extern void sim_queue_fn_mem_qi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, QI), SI, QI);
209 extern void sim_queue_fn_mem_hi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, HI), SI, HI);
210 extern void sim_queue_fn_mem_si_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI), SI, SI);
211 extern void sim_queue_fn_mem_di_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DI), SI, DI);
212 extern void sim_queue_fn_mem_df_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DF), SI, DF);
213 extern void sim_queue_fn_mem_xi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI *), SI, SI *);
215 #endif /* CGEN_PAR_H */