]>
Commit | Line | Data |
---|---|---|
1 | 2021-04-02 Mike Frysinger <[email protected]> | |
2 | ||
3 | * aclocal.m4, configure: Regenerate. | |
4 | ||
5 | 2021-02-28 Mike Frysinger <[email protected]> | |
6 | ||
7 | * configure: Regenerate. | |
8 | ||
9 | 2021-02-21 Mike Frysinger <[email protected]> | |
10 | ||
11 | * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4. | |
12 | * aclocal.m4, configure: Regenerate. | |
13 | ||
14 | 2021-02-13 Mike Frysinger <[email protected]> | |
15 | ||
16 | * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS. | |
17 | * aclocal.m4, configure: Regenerate. | |
18 | ||
19 | 2021-02-06 Mike Frysinger <[email protected]> | |
20 | ||
21 | * configure: Regenerate. | |
22 | ||
23 | 2021-01-31 Mike Frysinger <[email protected]> | |
24 | ||
25 | * decode.c (or1k32bf_decode): Change TRACE_EXTRACT to | |
26 | CGEN_TRACE_EXTRACT. | |
27 | ||
28 | 2021-01-12 Mike Frysinger <[email protected]> | |
29 | ||
30 | * traps.c (or1k32bf_exception): Move handler_pc decl to top of scope. | |
31 | (or1k32bf_mfspr): Move val decl to top of function body. | |
32 | ||
33 | 2021-01-12 Mike Frysinger <[email protected]> | |
34 | ||
35 | * Makefile.in (SIM_OBJS): Delete redundant sim-cpu.o, sim-hload.o, | |
36 | sim-hrw.o, sim-reg.o, sim-reason.o, sim-engine.o, sim-model.o, | |
37 | sim-stop.o, and $(TRAPS_OBJ) entries. | |
38 | (SIM_RUN_OBJS): Delete. | |
39 | ||
40 | 2021-01-12 Mike Frysinger <[email protected]> | |
41 | ||
42 | * configure.ac (SIM_AC_OPTION_INLINE): Delete call. | |
43 | * configure: Regenerate. | |
44 | ||
45 | 2021-01-11 Mike Frysinger <[email protected]> | |
46 | ||
47 | * configure.ac: Call SIM_AC_OPTION_WARNINGS. | |
48 | * configure: Regenerate. | |
49 | ||
50 | 2021-01-11 Mike Frysinger <[email protected]> | |
51 | ||
52 | * sim-main.h: Include config.h. | |
53 | ||
54 | 2021-01-11 Mike Frysinger <[email protected]> | |
55 | ||
56 | * config.in, configure: Regenerate. | |
57 | * sim-if.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H, | |
58 | and strings.h include. | |
59 | ||
60 | 2021-01-09 Mike Frysinger <[email protected]> | |
61 | ||
62 | * configure: Regenerate. | |
63 | ||
64 | 2021-01-08 Mike Frysinger <[email protected]> | |
65 | ||
66 | * configure: Regenerate. | |
67 | ||
68 | 2019-06-13 Stafford Horne <[email protected]> | |
69 | ||
70 | * cpu.c: Regenerate. | |
71 | * cpu.h: Regenerate. | |
72 | * decode.c: Regenerate. | |
73 | * decode.h: Regenerate. | |
74 | * model.c: Regenerate. | |
75 | * sem-switch.c: Regenerate. | |
76 | * sem.c: Regenerate. | |
77 | ||
78 | 2018-10-05 Stafford Horne <[email protected]> | |
79 | ||
80 | * cpu.h: Regenerate. | |
81 | * decode.c: Regenerate. | |
82 | * decode.h: Regenerate. | |
83 | * model.c: Regenerate. | |
84 | * sem-switch.c: Regenerate. | |
85 | * sem.c: Regenerate: | |
86 | ||
87 | 2017-12-12 Stafford Horne <[email protected]> | |
88 | Peter Gavin <[email protected]> | |
89 | ||
90 | * aclocal.m4: Generated. | |
91 | * config.in: Generated. | |
92 | * configure: Generated. | |
93 | ||
94 | 2017-12-12 Stafford Horne <[email protected]> | |
95 | Peter Gavin <[email protected]> | |
96 | ||
97 | * arch.c: Generated. | |
98 | * arch.h: Generated. | |
99 | * cpu.c: Generated. | |
100 | * cpu.h: Generated. | |
101 | * cpuall.h: Generated. | |
102 | * decode.c: Generated. | |
103 | * decode.h: Generated. | |
104 | * model.c: Generated. | |
105 | * sem-switch.c: Generated. | |
106 | * sem.c: Generated. | |
107 | ||
108 | 2017-12-12 Stafford Horne <[email protected]> | |
109 | Peter Gavin <[email protected]> | |
110 | ||
111 | * README: New file. | |
112 | * Makefile.in: New file. | |
113 | * configure.ac: New file. | |
114 | * mloop.in: New file. | |
115 | * or1k-sim.h: New file. | |
116 | * or1k.c: New file. | |
117 | * sim-if.c: New file. | |
118 | * sim-main.h: New file. | |
119 | * traps.c: New file. |