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* mn10300_sim.h (struct _state): Put all registers into a single
[binutils.git] / sim / mn10300 / simops.c
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CommitLineData
1#include "config.h"
2
3#include <signal.h>
4#ifdef HAVE_UNISTD_H
5#include <unistd.h>
6#endif
7#include "mn10300_sim.h"
8#include "simops.h"
9#include "sys/syscall.h"
10#include "bfd.h"
11#include <errno.h>
12#include <sys/stat.h>
13#include <sys/times.h>
14#include <sys/time.h>
15
16#define REG0(X) ((X) & 0x3)
17#define REG1(X) (((X) & 0xc) >> 2)
18#define REG0_4(X) (((X) & 0x30) >> 4)
19#define REG0_8(X) (((X) & 0x300) >> 8)
20#define REG1_8(X) (((X) & 0xc00) >> 10)
21#define REG0_16(X) (((X) & 0x30000) >> 16)
22#define REG1_16(X) (((X) & 0xc0000) >> 18)
23\f
24/* mov imm8, dn */
25void OP_8000 (insn, extension)
26 unsigned long insn, extension;
27{
28 State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff);
29}
30
31/* mov dm, dn */
32void OP_80 (insn, extension)
33 unsigned long insn, extension;
34{
35 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
36}
37
38/* mov dm, an */
39void OP_F1E0 (insn, extension)
40 unsigned long insn, extension;
41{
42 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
43}
44
45/* mov am, dn */
46void OP_F1D0 (insn, extension)
47 unsigned long insn, extension;
48{
49 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
50}
51
52/* mov imm8, an */
53void OP_9000 (insn, extension)
54 unsigned long insn, extension;
55{
56 State.regs[REG_A0 + REG0_8 (insn)] = insn & 0xff;
57}
58
59/* mov am, an */
60void OP_90 (insn, extension)
61 unsigned long insn, extension;
62{
63 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
64}
65
66/* mov sp, an */
67void OP_3C (insn, extension)
68 unsigned long insn, extension;
69{
70 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_SP];
71}
72
73/* mov am, sp */
74void OP_F2F0 (insn, extension)
75 unsigned long insn, extension;
76{
77 State.regs[REG_SP] = State.regs[REG_A0 + REG1 (insn)];
78}
79
80/* mov psw, dn */
81void OP_F2E4 (insn, extension)
82 unsigned long insn, extension;
83{
84 State.regs[REG_D0 + REG0 (insn)] = PSW;
85}
86
87/* mov dm, psw */
88void OP_F2F3 (insn, extension)
89 unsigned long insn, extension;
90{
91 PSW = State.regs[REG_D0 + REG1 (insn)];
92}
93
94/* mov mdr, dn */
95void OP_F2E0 (insn, extension)
96 unsigned long insn, extension;
97{
98 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR];
99}
100
101/* mov dm, mdr */
102void OP_F2F2 (insn, extension)
103 unsigned long insn, extension;
104{
105 State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)];
106}
107
108/* mov (am), dn */
109void OP_70 (insn, extension)
110 unsigned long insn, extension;
111{
112 State.regs[REG_D0 + REG1 (insn)]
113 = load_mem (State.regs[REG_A0 + REG0 (insn)], 4);
114}
115
116/* mov (d8,am), dn */
117void OP_F80000 (insn, extension)
118 unsigned long insn, extension;
119{
120 State.regs[REG_D0 + REG1_8 (insn)]
121 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
122 + SEXT8 (insn & 0xff)), 4);
123}
124
125/* mov (d16,am), dn */
126void OP_FA000000 (insn, extension)
127 unsigned long insn, extension;
128{
129 State.regs[REG_D0 + REG1_16 (insn)]
130 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
131 + SEXT16 (insn & 0xffff)), 4);
132}
133
134/* mov (d32,am), dn */
135void OP_FC000000 (insn, extension)
136 unsigned long insn, extension;
137{
138 State.regs[REG_D0 + REG1_16 (insn)]
139 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
140 + ((insn & 0xffff) << 16) + extension), 4);
141}
142
143/* mov (d8,sp), dn */
144void OP_5800 (insn, extension)
145 unsigned long insn, extension;
146{
147 State.regs[REG_D0 + REG0_8 (insn)]
148 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
149}
150
151/* mov (d16,sp), dn */
152void OP_FAB40000 (insn, extension)
153 unsigned long insn, extension;
154{
155 State.regs[REG_D0 + REG0_16 (insn)]
156 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
157}
158
159/* mov (d32,sp), dn */
160void OP_FCB40000 (insn, extension)
161 unsigned long insn, extension;
162{
163 State.regs[REG_D0 + REG0_16 (insn)]
164 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
165}
166
167/* mov (di,am), dn */
168void OP_F300 (insn, extension)
169 unsigned long insn, extension;
170{
171 State.regs[REG_D0 + REG0_4 (insn)]
172 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
173 + State.regs[REG_D0 + REG1 (insn)]), 4);
174}
175
176/* mov (abs16), dn */
177void OP_300000 (insn, extension)
178 unsigned long insn, extension;
179{
180 State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4);
181}
182
183/* mov (abs32), dn */
184void OP_FCA40000 (insn, extension)
185 unsigned long insn, extension;
186{
187 State.regs[REG_D0 + REG0_16 (insn)]
188 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
189}
190
191/* mov (am), an */
192void OP_F000 (insn, extension)
193 unsigned long insn, extension;
194{
195 State.regs[REG_A0 + REG1 (insn)]
196 = load_mem (State.regs[REG_A0 + REG0 (insn)], 4);
197}
198
199/* mov (d8,am), an */
200void OP_F82000 (insn, extension)
201 unsigned long insn, extension;
202{
203 State.regs[REG_A0 + REG1_8 (insn)]
204 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
205 + SEXT8 (insn & 0xff)), 4);
206}
207
208/* mov (d16,am), an */
209void OP_FA200000 (insn, extension)
210 unsigned long insn, extension;
211{
212 State.regs[REG_A0 + REG1_16 (insn)]
213 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
214 + SEXT16 (insn & 0xffff)), 4);
215}
216
217/* mov (d32,am), an */
218void OP_FC200000 (insn, extension)
219 unsigned long insn, extension;
220{
221 State.regs[REG_A0 + REG1_16 (insn)]
222 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
223 + ((insn & 0xffff) << 16) + extension), 4);
224}
225
226/* mov (d8,sp), an */
227void OP_5C00 (insn, extension)
228 unsigned long insn, extension;
229{
230 State.regs[REG_A0 + REG0_8 (insn)]
231 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
232}
233
234/* mov (d16,sp), an */
235void OP_FAB00000 (insn, extension)
236 unsigned long insn, extension;
237{
238 State.regs[REG_A0 + REG0_16 (insn)]
239 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
240}
241
242/* mov (d32,sp), an */
243void OP_FCB00000 (insn, extension)
244 unsigned long insn, extension;
245{
246 State.regs[REG_A0 + REG0_16 (insn)]
247 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
248}
249
250/* mov (di,am), an */
251void OP_F380 (insn, extension)
252 unsigned long insn, extension;
253{
254 State.regs[REG_A0 + REG0_4 (insn)]
255 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
256 + State.regs[REG_D0 + REG1 (insn)]), 4);
257}
258
259/* mov (abs16), an */
260void OP_FAA00000 (insn, extension)
261 unsigned long insn, extension;
262{
263 State.regs[REG_A0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4);
264}
265
266/* mov (abs32), an */
267void OP_FCA00000 (insn, extension)
268 unsigned long insn, extension;
269{
270 State.regs[REG_A0 + REG0_16 (insn)]
271 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
272}
273
274/* mov (d8,am), sp */
275void OP_F8F000 (insn, extension)
276 unsigned long insn, extension;
277{
278 State.regs[REG_SP]
279 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
280 + SEXT8 (insn & 0xff)), 4);
281}
282
283/* mov dm, (an) */
284void OP_60 (insn, extension)
285 unsigned long insn, extension;
286{
287 store_mem (State.regs[REG_A0 + REG0 (insn)], 4,
288 State.regs[REG_D0 + REG1 (insn)]);
289}
290
291/* mov dm, (d8,an) */
292void OP_F81000 (insn, extension)
293 unsigned long insn, extension;
294{
295 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
296 + SEXT8 (insn & 0xff)), 4,
297 State.regs[REG_D0 + REG1_8 (insn)]);
298}
299
300/* mov dm (d16,an) */
301void OP_FA100000 (insn, extension)
302 unsigned long insn, extension;
303{
304 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
305 + SEXT16 (insn & 0xffff)), 4,
306 State.regs[REG_D0 + REG1_16 (insn)]);
307}
308
309/* mov dm (d32,an) */
310void OP_FC100000 (insn, extension)
311 unsigned long insn, extension;
312{
313 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
314 + ((insn & 0xffff) << 16) + extension), 4,
315 State.regs[REG_D0 + REG1_16 (insn)]);
316}
317
318/* mov dm, (d8,sp) */
319void OP_4200 (insn, extension)
320 unsigned long insn, extension;
321{
322 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
323 State.regs[REG_D0 + REG1_8 (insn)]);
324}
325
326/* mov dm, (d16,sp) */
327void OP_FA910000 (insn, extension)
328 unsigned long insn, extension;
329{
330 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
331 State.regs[REG_D0 + REG1_16 (insn)]);
332}
333
334/* mov dm, (d32,sp) */
335void OP_FC910000 (insn, extension)
336 unsigned long insn, extension;
337{
338 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
339 State.regs[REG_D0 + REG1_16 (insn)]);
340}
341
342/* mov dm, (di,an) */
343void OP_F340 (insn, extension)
344 unsigned long insn, extension;
345{
346 store_mem ((State.regs[REG_A0 + REG0 (insn)]
347 + State.regs[REG_D0 + REG1 (insn)]), 4,
348 State.regs[REG_D0 + REG0_4 (insn)]);
349}
350
351/* mov dm, (abs16) */
352void OP_10000 (insn, extension)
353 unsigned long insn, extension;
354{
355 store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + REG1_16 (insn)]);
356}
357
358/* mov dm, (abs32) */
359void OP_FC810000 (insn, extension)
360 unsigned long insn, extension;
361{
362 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + REG1_16 (insn)]);
363}
364
365/* mov am, (an) */
366void OP_F010 (insn, extension)
367 unsigned long insn, extension;
368{
369 store_mem (State.regs[REG_A0 + REG0 (insn)], 4,
370 State.regs[REG_A0 + REG1 (insn)]);
371}
372
373/* mov am, (d8,an) */
374void OP_F83000 (insn, extension)
375 unsigned long insn, extension;
376{
377 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
378 + SEXT8 (insn & 0xff)), 4,
379 State.regs[REG_A0 + REG1_8 (insn)]);
380}
381
382/* mov am, (d16,an) */
383void OP_FA300000 (insn, extension)
384 unsigned long insn, extension;
385{
386 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
387 + SEXT16 (insn & 0xffff)), 4,
388 State.regs[REG_A0 + REG1_16 (insn)]);
389}
390
391/* mov am, (d32,an) */
392void OP_FC300000 (insn, extension)
393 unsigned long insn, extension;
394{
395 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
396 + ((insn & 0xffff) << 16) + extension), 4,
397 State.regs[REG_A0 + REG1_16 (insn)]);
398}
399
400/* mov am, (d8,sp) */
401void OP_4300 (insn, extension)
402 unsigned long insn, extension;
403{
404 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
405 State.regs[REG_A0 + REG1_8 (insn)]);
406}
407
408/* mov am, (d16,sp) */
409void OP_FA900000 (insn, extension)
410 unsigned long insn, extension;
411{
412 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
413 State.regs[REG_A0 + REG1_16 (insn)]);
414}
415
416/* mov am, (d32,sp) */
417void OP_FC900000 (insn, extension)
418 unsigned long insn, extension;
419{
420 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
421 State.regs[REG_A0 + REG1_16 (insn)]);
422}
423
424/* mov am, (di,an) */
425void OP_F3C0 (insn, extension)
426 unsigned long insn, extension;
427{
428 store_mem ((State.regs[REG_A0 + REG0 (insn)]
429 + State.regs[REG_D0 + REG1 (insn)]), 4,
430 State.regs[REG_A0 + REG0_4 (insn)]);
431}
432
433/* mov am, (abs16) */
434void OP_FA800000 (insn, extension)
435 unsigned long insn, extension;
436{
437 store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + REG1_16 (insn)]);
438}
439
440/* mov am, (abs32) */
441void OP_FC800000 (insn, extension)
442 unsigned long insn, extension;
443{
444 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + REG1_16 (insn)]);
445}
446
447/* mov sp, (d8,an) */
448void OP_F8F400 (insn, extension)
449 unsigned long insn, extension;
450{
451 store_mem (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
452 4, State.regs[REG_SP]);
453}
454
455/* mov imm16, dn */
456void OP_2C0000 (insn, extension)
457 unsigned long insn, extension;
458{
459 unsigned long value;
460
461 value = SEXT16 (insn & 0xffff);
462 State.regs[REG_D0 + REG0_16 (insn)] = value;
463}
464
465/* mov imm32,dn */
466void OP_FCCC0000 (insn, extension)
467 unsigned long insn, extension;
468{
469 unsigned long value;
470
471 value = ((insn & 0xffff) << 16) + extension;
472 State.regs[REG_D0 + REG0_16 (insn)] = value;
473}
474
475/* mov imm16, an */
476void OP_240000 (insn, extension)
477 unsigned long insn, extension;
478{
479 unsigned long value;
480
481 value = insn & 0xffff;
482 State.regs[REG_A0 + REG0_16 (insn)] = value;
483}
484
485/* mov imm32, an */
486void OP_FCDC0000 (insn, extension)
487 unsigned long insn, extension;
488{
489 unsigned long value;
490
491 value = ((insn & 0xffff) << 16) + extension;
492 State.regs[REG_A0 + REG0_16 (insn)] = value;
493}
494
495/* movbu (am), dn */
496void OP_F040 (insn, extension)
497 unsigned long insn, extension;
498{
499 State.regs[REG_D0 + REG1 (insn)]
500 = load_mem (State.regs[REG_A0 + REG0 (insn)], 1);
501}
502
503/* movbu (d8,am), dn */
504void OP_F84000 (insn, extension)
505 unsigned long insn, extension;
506{
507 State.regs[REG_D0 + REG1_8 (insn)]
508 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
509 + SEXT8 (insn & 0xff)), 1);
510}
511
512/* movbu (d16,am), dn */
513void OP_FA400000 (insn, extension)
514 unsigned long insn, extension;
515{
516 State.regs[REG_D0 + REG1_16 (insn)]
517 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
518 + SEXT16 (insn & 0xffff)), 1);
519}
520
521/* movbu (d32,am), dn */
522void OP_FC400000 (insn, extension)
523 unsigned long insn, extension;
524{
525 State.regs[REG_D0 + REG1_16 (insn)]
526 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
527 + ((insn & 0xffff) << 16) + extension), 1);
528}
529
530/* movbu (d8,sp), dn */
531void OP_F8B800 (insn, extension)
532 unsigned long insn, extension;
533{
534 State.regs[REG_D0 + REG0_8 (insn)]
535 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
536}
537
538/* movbu (d16,sp), dn */
539void OP_FAB80000 (insn, extension)
540 unsigned long insn, extension;
541{
542 State.regs[REG_D0 + REG0_16 (insn)]
543 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
544}
545
546/* movbu (d32,sp), dn */
547void OP_FCB80000 (insn, extension)
548 unsigned long insn, extension;
549{
550 State.regs[REG_D0 + REG0_16 (insn)]
551 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
552}
553
554/* movbu (di,am), dn */
555void OP_F400 (insn, extension)
556 unsigned long insn, extension;
557{
558 State.regs[REG_D0 + REG0_4 (insn)]
559 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
560 + State.regs[REG_D0 + REG1 (insn)]), 1);
561}
562
563/* movbu (abs16), dn */
564void OP_340000 (insn, extension)
565 unsigned long insn, extension;
566{
567 State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 1);
568}
569
570/* movbu (abs32), dn */
571void OP_FCA80000 (insn, extension)
572 unsigned long insn, extension;
573{
574 State.regs[REG_D0 + REG0_16 (insn)]
575 = load_mem ((((insn & 0xffff) << 16) + extension), 1);
576}
577
578/* movbu dm, (an) */
579void OP_F050 (insn, extension)
580 unsigned long insn, extension;
581{
582 store_mem (State.regs[REG_A0 + REG0 (insn)], 1,
583 State.regs[REG_D0 + REG1 (insn)]);
584}
585
586/* movbu dm, (d8,an) */
587void OP_F85000 (insn, extension)
588 unsigned long insn, extension;
589{
590 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
591 + SEXT8 (insn & 0xff)), 1,
592 State.regs[REG_D0 + REG1_8 (insn)]);
593}
594
595/* movbu dm, (d16,an) */
596void OP_FA500000 (insn, extension)
597 unsigned long insn, extension;
598{
599 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
600 + SEXT16 (insn & 0xffff)), 1,
601 State.regs[REG_D0 + REG1_16 (insn)]);
602}
603
604/* movbu dm, (d32,an) */
605void OP_FC500000 (insn, extension)
606 unsigned long insn, extension;
607{
608 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
609 + ((insn & 0xffff) << 16) + extension), 1,
610 State.regs[REG_D0 + REG1_16 (insn)]);
611}
612
613/* movbu dm, (d8,sp) */
614void OP_F89200 (insn, extension)
615 unsigned long insn, extension;
616{
617 store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
618 State.regs[REG_D0 + REG1_8 (insn)]);
619}
620
621/* movbu dm, (d16,sp) */
622void OP_FA920000 (insn, extension)
623 unsigned long insn, extension;
624{
625 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
626 State.regs[REG_D0 + REG1_8 (insn)]);
627}
628
629/* movbu dm (d32,sp) */
630void OP_FC920000 (insn, extension)
631 unsigned long insn, extension;
632{
633 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
634 State.regs[REG_D0 + REG1_8 (insn)]);
635}
636
637/* movbu dm, (di,an) */
638void OP_F440 (insn, extension)
639 unsigned long insn, extension;
640{
641 store_mem ((State.regs[REG_A0 + REG0 (insn)]
642 + State.regs[REG_D0 + REG1 (insn)]), 1,
643 State.regs[REG_D0 + REG0_4 (insn)]);
644}
645
646/* movbu dm, (abs16) */
647void OP_20000 (insn, extension)
648 unsigned long insn, extension;
649{
650 store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + REG1_16 (insn)]);
651}
652
653/* movbu dm, (abs32) */
654void OP_FC820000 (insn, extension)
655 unsigned long insn, extension;
656{
657 store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + REG1_16 (insn)]);
658}
659
660/* movhu (am), dn */
661void OP_F060 (insn, extension)
662 unsigned long insn, extension;
663{
664 State.regs[REG_D0 + REG1 (insn)]
665 = load_mem (State.regs[REG_A0 + REG0 (insn)], 2);
666}
667
668/* movhu (d8,am), dn */
669void OP_F86000 (insn, extension)
670 unsigned long insn, extension;
671{
672 State.regs[REG_D0 + REG1_8 (insn)]
673 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
674 + SEXT8 (insn & 0xff)), 2);
675}
676
677/* movhu (d16,am), dn */
678void OP_FA600000 (insn, extension)
679 unsigned long insn, extension;
680{
681 State.regs[REG_D0 + REG1_16 (insn)]
682 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
683 + SEXT16 (insn & 0xffff)), 2);
684}
685
686/* movhu (d32,am), dn */
687void OP_FC600000 (insn, extension)
688 unsigned long insn, extension;
689{
690 State.regs[REG_D0 + REG1_16 (insn)]
691 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
692 + ((insn & 0xffff) << 16) + extension), 2);
693}
694
695/* movhu (d8,sp) dn */
696void OP_F8BC00 (insn, extension)
697 unsigned long insn, extension;
698{
699 State.regs[REG_D0 + REG0_8 (insn)]
700 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
701}
702
703/* movhu (d16,sp), dn */
704void OP_FABC0000 (insn, extension)
705 unsigned long insn, extension;
706{
707 State.regs[REG_D0 + REG0_16 (insn)]
708 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
709}
710
711/* movhu (d32,sp), dn */
712void OP_FCBC0000 (insn, extension)
713 unsigned long insn, extension;
714{
715 State.regs[REG_D0 + REG0_16 (insn)]
716 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
717}
718
719/* movhu (di,am), dn */
720void OP_F480 (insn, extension)
721 unsigned long insn, extension;
722{
723 State.regs[REG_D0 + REG0_4 (insn)]
724 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
725 + State.regs[REG_D0 + REG1 (insn)]), 2);
726}
727
728/* movhu (abs16), dn */
729void OP_380000 (insn, extension)
730 unsigned long insn, extension;
731{
732 State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 2);
733}
734
735/* movhu (abs32), dn */
736void OP_FCAC0000 (insn, extension)
737 unsigned long insn, extension;
738{
739 State.regs[REG_D0 + REG0_16 (insn)]
740 = load_mem ((((insn & 0xffff) << 16) + extension), 2);
741}
742
743/* movhu dm, (an) */
744void OP_F070 (insn, extension)
745 unsigned long insn, extension;
746{
747 store_mem (State.regs[REG_A0 + REG0 (insn)], 2,
748 State.regs[REG_D0 + REG1 (insn)]);
749}
750
751/* movhu dm, (d8,an) */
752void OP_F87000 (insn, extension)
753 unsigned long insn, extension;
754{
755 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
756 + SEXT8 (insn & 0xff)), 2,
757 State.regs[REG_D0 + REG1_8 (insn)]);
758}
759
760/* movhu dm, (d16,an) */
761void OP_FA700000 (insn, extension)
762 unsigned long insn, extension;
763{
764 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
765 + SEXT16 (insn & 0xffff)), 2,
766 State.regs[REG_D0 + REG1_16 (insn)]);
767}
768
769/* movhu dm, (d32,an) */
770void OP_FC700000 (insn, extension)
771 unsigned long insn, extension;
772{
773 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
774 + ((insn & 0xffff) << 16) + extension), 2,
775 State.regs[REG_D0 + REG1_16 (insn)]);
776}
777
778/* movhu dm,(d8,sp) */
779void OP_F89300 (insn, extension)
780 unsigned long insn, extension;
781{
782 store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
783 State.regs[REG_D0 + REG1_8 (insn)]);
784}
785
786/* movhu dm,(d16,sp) */
787void OP_FA930000 (insn, extension)
788 unsigned long insn, extension;
789{
790 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
791 State.regs[REG_D0 + REG1_16 (insn)]);
792}
793
794/* movhu dm,(d32,sp) */
795void OP_FC930000 (insn, extension)
796 unsigned long insn, extension;
797{
798 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
799 State.regs[REG_D0 + REG1_16 (insn)]);
800}
801
802/* movhu dm, (di,an) */
803void OP_F4C0 (insn, extension)
804 unsigned long insn, extension;
805{
806 store_mem ((State.regs[REG_A0 + REG0 (insn)]
807 + State.regs[REG_D0 + REG1 (insn)]), 2,
808 State.regs[REG_D0 + REG0_4 (insn)]);
809}
810
811/* movhu dm, (abs16) */
812void OP_30000 (insn, extension)
813 unsigned long insn, extension;
814{
815 store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + REG1_16 (insn)]);
816}
817
818/* movhu dm, (abs32) */
819void OP_FC830000 (insn, extension)
820 unsigned long insn, extension;
821{
822 store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + REG1_16 (insn)]);
823}
824
825/* ext dn */
826void OP_F2D0 (insn, extension)
827 unsigned long insn, extension;
828{
829 if (State.regs[REG_D0 + REG0 (insn)] & 0x80000000)
830 State.regs[REG_MDR] = -1;
831 else
832 State.regs[REG_MDR] = 0;
833}
834
835/* extb dn */
836void OP_10 (insn, extension)
837 unsigned long insn, extension;
838{
839 State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]);
840}
841
842/* extbu dn */
843void OP_14 (insn, extension)
844 unsigned long insn, extension;
845{
846 State.regs[REG_D0 + REG0 (insn)] &= 0xff;
847}
848
849/* exth dn */
850void OP_18 (insn, extension)
851 unsigned long insn, extension;
852{
853 State.regs[REG_D0 + REG0 (insn)]
854 = SEXT16 (State.regs[REG_D0 + REG0 (insn)]);
855}
856
857/* exthu dn */
858void OP_1C (insn, extension)
859 unsigned long insn, extension;
860{
861 State.regs[REG_D0 + REG0 (insn)] &= 0xffff;
862}
863
864/* movm (sp), reg_list */
865void OP_CE00 (insn, extension)
866 unsigned long insn, extension;
867{
868 unsigned long sp = State.regs[REG_SP];
869 unsigned long mask;
870
871 mask = insn & 0xff;
872
873 if (mask & 0x8)
874 {
875 sp += 4;
876 State.regs[REG_LAR] = load_mem (sp, 4);
877 sp += 4;
878 State.regs[REG_LIR] = load_mem (sp, 4);
879 sp += 4;
880 State.regs[REG_MDR] = load_mem (sp, 4);
881 sp += 4;
882 State.regs[REG_A0 + 1] = load_mem (sp, 4);
883 sp += 4;
884 State.regs[REG_A0] = load_mem (sp, 4);
885 sp += 4;
886 State.regs[REG_D0 + 1] = load_mem (sp, 4);
887 sp += 4;
888 State.regs[REG_D0] = load_mem (sp, 4);
889 sp += 4;
890 }
891
892 if (mask & 0x10)
893 {
894 State.regs[REG_A0 + 3] = load_mem (sp, 4);
895 sp += 4;
896 }
897
898 if (mask & 0x20)
899 {
900 State.regs[REG_A0 + 2] = load_mem (sp, 4);
901 sp += 4;
902 }
903
904 if (mask & 0x40)
905 {
906 State.regs[REG_D0 + 3] = load_mem (sp, 4);
907 sp += 4;
908 }
909
910 if (mask & 0x80)
911 {
912 State.regs[REG_D0 + 2] = load_mem (sp, 4);
913 sp += 4;
914 }
915
916 /* And make sure to update the stack pointer. */
917 State.regs[REG_SP] = sp;
918}
919
920/* movm reg_list, (sp) */
921void OP_CF00 (insn, extension)
922 unsigned long insn, extension;
923{
924 unsigned long sp = State.regs[REG_SP];
925 unsigned long mask;
926
927 mask = insn & 0xff;
928
929 if (mask & 0x80)
930 {
931 sp -= 4;
932 store_mem (sp, 4, State.regs[REG_D0 + 2]);
933 }
934
935 if (mask & 0x40)
936 {
937 sp -= 4;
938 store_mem (sp, 4, State.regs[REG_D0 + 3]);
939 }
940
941 if (mask & 0x20)
942 {
943 sp -= 4;
944 store_mem (sp, 4, State.regs[REG_A0 + 2]);
945 }
946
947 if (mask & 0x10)
948 {
949 sp -= 4;
950 store_mem (sp, 4, State.regs[REG_A0 + 3]);
951 }
952
953 if (mask & 0x8)
954 {
955 sp -= 4;
956 store_mem (sp, 4, State.regs[REG_D0]);
957 sp -= 4;
958 store_mem (sp, 4, State.regs[REG_D0 + 1]);
959 sp -= 4;
960 store_mem (sp, 4, State.regs[REG_A0]);
961 sp -= 4;
962 store_mem (sp, 4, State.regs[REG_A0 + 1]);
963 sp -= 4;
964 store_mem (sp, 4, State.regs[REG_MDR]);
965 sp -= 4;
966 store_mem (sp, 4, State.regs[REG_LIR]);
967 sp -= 4;
968 store_mem (sp, 4, State.regs[REG_LAR]);
969 sp -= 4;
970 }
971
972 /* And make sure to update the stack pointer. */
973 State.regs[REG_SP] = sp;
974}
975
976/* clr dn */
977void OP_0 (insn, extension)
978 unsigned long insn, extension;
979{
980 State.regs[REG_D0 + REG1 (insn)] = 0;
981
982 PSW |= PSW_Z;
983 PSW &= ~(PSW_V | PSW_C | PSW_N);
984}
985
986/* add dm,dn */
987void OP_E0 (insn, extension)
988 unsigned long insn, extension;
989{
990 int z, c, n, v;
991 unsigned long reg1, reg2, value;
992
993 reg1 = State.regs[REG_D0 + REG1 (insn)];
994 reg2 = State.regs[REG_D0 + REG0 (insn)];
995 value = reg1 + reg2;
996 State.regs[REG_D0 + REG0 (insn)] = value;
997
998 z = (value == 0);
999 n = (value & 0x80000000);
1000 c = (reg1 < reg2);
1001 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1002 && (reg2 & 0x80000000) != (value & 0x80000000));
1003
1004 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1005 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1006 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1007}
1008
1009/* add dm, an */
1010void OP_F160 (insn, extension)
1011 unsigned long insn, extension;
1012{
1013 int z, c, n, v;
1014 unsigned long reg1, reg2, value;
1015
1016 reg1 = State.regs[REG_D0 + REG1 (insn)];
1017 reg2 = State.regs[REG_A0 + REG0 (insn)];
1018 value = reg1 + reg2;
1019 State.regs[REG_A0 + REG0 (insn)] = value;
1020
1021 z = (value == 0);
1022 n = (value & 0x80000000);
1023 c = (reg1 < reg2);
1024 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1025 && (reg2 & 0x80000000) != (value & 0x80000000));
1026
1027 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1028 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1029 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1030}
1031
1032/* add am, dn */
1033void OP_F150 (insn, extension)
1034 unsigned long insn, extension;
1035{
1036 int z, c, n, v;
1037 unsigned long reg1, reg2, value;
1038
1039 reg1 = State.regs[REG_A0 + REG1 (insn)];
1040 reg2 = State.regs[REG_D0 + REG0 (insn)];
1041 value = reg1 + reg2;
1042 State.regs[REG_D0 + REG0 (insn)] = value;
1043
1044 z = (value == 0);
1045 n = (value & 0x80000000);
1046 c = (reg1 < reg2);
1047 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1048 && (reg2 & 0x80000000) != (value & 0x80000000));
1049
1050 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1051 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1052 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1053}
1054
1055/* add am,an */
1056void OP_F170 (insn, extension)
1057 unsigned long insn, extension;
1058{
1059 int z, c, n, v;
1060 unsigned long reg1, reg2, value;
1061
1062 reg1 = State.regs[REG_A0 + REG1 (insn)];
1063 reg2 = State.regs[REG_A0 + REG0 (insn)];
1064 value = reg1 + reg2;
1065 State.regs[REG_A0 + REG0 (insn)] = value;
1066
1067 z = (value == 0);
1068 n = (value & 0x80000000);
1069 c = (reg1 < reg2);
1070 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1071 && (reg2 & 0x80000000) != (value & 0x80000000));
1072
1073 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1074 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1075 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1076}
1077
1078/* add imm8, dn */
1079void OP_2800 (insn, extension)
1080 unsigned long insn, extension;
1081{
1082 int z, c, n, v;
1083 unsigned long reg1, imm, value;
1084
1085 reg1 = State.regs[REG_D0 + REG0_8 (insn)];
1086 imm = SEXT8 (insn & 0xff);
1087 value = reg1 + imm;
1088 State.regs[REG_D0 + REG0_8 (insn)] = value;
1089
1090 z = (value == 0);
1091 n = (value & 0x80000000);
1092 c = (reg1 < imm);
1093 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1094 && (reg1 & 0x80000000) != (value & 0x80000000));
1095
1096 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1097 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1098 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1099}
1100
1101/* add imm16, dn */
1102void OP_FAC00000 (insn, extension)
1103 unsigned long insn, extension;
1104{
1105 int z, c, n, v;
1106 unsigned long reg1, imm, value;
1107
1108 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1109 imm = SEXT16 (insn & 0xffff);
1110 value = reg1 + imm;
1111 State.regs[REG_D0 + REG0_16 (insn)] = value;
1112
1113 z = (value == 0);
1114 n = (value & 0x80000000);
1115 c = (reg1 < imm);
1116 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1117 && (reg1 & 0x80000000) != (value & 0x80000000));
1118
1119 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1120 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1121 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1122}
1123
1124/* add imm32,dn */
1125void OP_FCC00000 (insn, extension)
1126 unsigned long insn, extension;
1127{
1128 int z, c, n, v;
1129 unsigned long reg1, imm, value;
1130
1131 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1132 imm = ((insn & 0xffff) << 16) + extension;
1133 value = reg1 + imm;
1134 State.regs[REG_D0 + REG0_16 (insn)] = value;
1135
1136 z = (value == 0);
1137 n = (value & 0x80000000);
1138 c = (reg1 < imm);
1139 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1140 && (reg1 & 0x80000000) != (value & 0x80000000));
1141
1142 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1143 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1144 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1145}
1146
1147/* add imm8, an */
1148void OP_2000 (insn, extension)
1149 unsigned long insn, extension;
1150{
1151 int z, c, n, v;
1152 unsigned long reg1, imm, value;
1153
1154 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
1155 imm = SEXT8 (insn & 0xff);
1156 value = reg1 + imm;
1157 State.regs[REG_A0 + REG0_8 (insn)] = value;
1158
1159 z = (value == 0);
1160 n = (value & 0x80000000);
1161 c = (reg1 < imm);
1162 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1163 && (reg1 & 0x80000000) != (value & 0x80000000));
1164
1165 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1166 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1167 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1168}
1169
1170/* add imm16, an */
1171void OP_FAD00000 (insn, extension)
1172 unsigned long insn, extension;
1173{
1174 int z, c, n, v;
1175 unsigned long reg1, imm, value;
1176
1177 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1178 imm = SEXT16 (insn & 0xffff);
1179 value = reg1 + imm;
1180 State.regs[REG_A0 + REG0_16 (insn)] = value;
1181
1182 z = (value == 0);
1183 n = (value & 0x80000000);
1184 c = (reg1 < imm);
1185 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1186 && (reg1 & 0x80000000) != (value & 0x80000000));
1187
1188 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1189 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1190 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1191}
1192
1193/* add imm32, an */
1194void OP_FCD00000 (insn, extension)
1195 unsigned long insn, extension;
1196{
1197 int z, c, n, v;
1198 unsigned long reg1, imm, value;
1199
1200 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1201 imm = ((insn & 0xffff) << 16) + extension;
1202 value = reg1 + imm;
1203 State.regs[REG_A0 + REG0_16 (insn)] = value;
1204
1205 z = (value == 0);
1206 n = (value & 0x80000000);
1207 c = (reg1 < imm);
1208 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1209 && (reg1 & 0x80000000) != (value & 0x80000000));
1210
1211 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1212 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1213 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1214}
1215
1216/* add imm8, sp */
1217void OP_F8FE00 (insn, extension)
1218 unsigned long insn, extension;
1219{
1220 unsigned long reg1, imm, value;
1221
1222 reg1 = State.regs[REG_SP];
1223 imm = SEXT8 (insn & 0xff);
1224 value = reg1 + imm;
1225 State.regs[REG_SP] = value;
1226}
1227
1228/* add imm16,sp */
1229void OP_FAFE0000 (insn, extension)
1230 unsigned long insn, extension;
1231{
1232 unsigned long reg1, imm, value;
1233
1234 reg1 = State.regs[REG_SP];
1235 imm = SEXT16 (insn & 0xffff);
1236 value = reg1 + imm;
1237 State.regs[REG_SP] = value;
1238}
1239
1240/* add imm32, sp */
1241void OP_FCFE0000 (insn, extension)
1242 unsigned long insn, extension;
1243{
1244 unsigned long reg1, imm, value;
1245
1246 reg1 = State.regs[REG_SP];
1247 imm = ((insn & 0xffff) << 16) + extension;
1248 value = reg1 + imm;
1249 State.regs[REG_SP] = value;
1250}
1251
1252/* addc dm,dn */
1253void OP_F140 (insn, extension)
1254 unsigned long insn, extension;
1255{
1256 int z, c, n, v;
1257 unsigned long reg1, reg2, value;
1258
1259 reg1 = State.regs[REG_D0 + REG1 (insn)];
1260 reg2 = State.regs[REG_D0 + REG0 (insn)];
1261 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1262 State.regs[REG_D0 + REG0 (insn)] = value;
1263
1264 z = (value == 0);
1265 n = (value & 0x80000000);
1266 c = (reg1 < reg2);
1267 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1268 && (reg2 & 0x80000000) != (value & 0x80000000));
1269
1270 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1271 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1272 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1273}
1274
1275/* sub dm, dn */
1276void OP_F100 (insn, extension)
1277 unsigned long insn, extension;
1278{
1279 int z, c, n, v;
1280 unsigned long reg1, reg2, value;
1281
1282 reg1 = State.regs[REG_D0 + REG1 (insn)];
1283 reg2 = State.regs[REG_D0 + REG0 (insn)];
1284 value = reg2 - reg1;
1285
1286 z = (value == 0);
1287 n = (value & 0x80000000);
1288 c = (reg1 > reg2);
1289 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1290 && (reg2 & 0x80000000) != (value & 0x80000000));
1291
1292 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1293 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1294 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1295 State.regs[REG_D0 + REG0 (insn)] = value;
1296}
1297
1298/* sub dm, an */
1299void OP_F120 (insn, extension)
1300 unsigned long insn, extension;
1301{
1302 int z, c, n, v;
1303 unsigned long reg1, reg2, value;
1304
1305 reg1 = State.regs[REG_D0 + REG1 (insn)];
1306 reg2 = State.regs[REG_A0 + REG0 (insn)];
1307 value = reg2 - reg1;
1308
1309 z = (value == 0);
1310 n = (value & 0x80000000);
1311 c = (reg1 > reg2);
1312 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1313 && (reg2 & 0x80000000) != (value & 0x80000000));
1314
1315 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1316 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1317 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1318 State.regs[REG_A0 + REG0 (insn)] = value;
1319}
1320
1321/* sub am, dn */
1322void OP_F110 (insn, extension)
1323 unsigned long insn, extension;
1324{
1325 int z, c, n, v;
1326 unsigned long reg1, reg2, value;
1327
1328 reg1 = State.regs[REG_A0 + REG1 (insn)];
1329 reg2 = State.regs[REG_D0 + REG0 (insn)];
1330 value = reg2 - reg1;
1331
1332 z = (value == 0);
1333 n = (value & 0x80000000);
1334 c = (reg1 > reg2);
1335 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1336 && (reg2 & 0x80000000) != (value & 0x80000000));
1337
1338 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1339 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1340 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1341 State.regs[REG_D0 + REG0 (insn)] = value;
1342}
1343
1344/* sub am, an */
1345void OP_F130 (insn, extension)
1346 unsigned long insn, extension;
1347{
1348 int z, c, n, v;
1349 unsigned long reg1, reg2, value;
1350
1351 reg1 = State.regs[REG_A0 + REG1 (insn)];
1352 reg2 = State.regs[REG_A0 + REG0 (insn)];
1353 value = reg2 - reg1;
1354
1355 z = (value == 0);
1356 n = (value & 0x80000000);
1357 c = (reg1 > reg2);
1358 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1359 && (reg2 & 0x80000000) != (value & 0x80000000));
1360
1361 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1362 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1363 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1364 State.regs[REG_A0 + REG0 (insn)] = value;
1365}
1366
1367/* sub imm32, dn */
1368void OP_FCC40000 (insn, extension)
1369 unsigned long insn, extension;
1370{
1371 int z, c, n, v;
1372 unsigned long reg1, imm, value;
1373
1374 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1375 imm = ((insn & 0xffff) << 16) + extension;
1376 value = reg1 - imm;
1377
1378 z = (value == 0);
1379 n = (value & 0x80000000);
1380 c = (reg1 < imm);
1381 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1382 && (reg1 & 0x80000000) != (value & 0x80000000));
1383
1384 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1385 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1386 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1387 State.regs[REG_D0 + REG0_16 (insn)] = value;
1388}
1389
1390/* sub imm32, an */
1391void OP_FCD40000 (insn, extension)
1392 unsigned long insn, extension;
1393{
1394 int z, c, n, v;
1395 unsigned long reg1, imm, value;
1396
1397 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1398 imm = ((insn & 0xffff) << 16) + extension;
1399 value = reg1 - imm;
1400
1401 z = (value == 0);
1402 n = (value & 0x80000000);
1403 c = (reg1 < imm);
1404 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1405 && (reg1 & 0x80000000) != (value & 0x80000000));
1406
1407 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1408 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1409 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1410 State.regs[REG_A0 + REG0_16 (insn)] = value;
1411}
1412
1413/* subc dm, dn */
1414void OP_F180 (insn, extension)
1415 unsigned long insn, extension;
1416{
1417 int z, c, n, v;
1418 unsigned long reg1, reg2, value;
1419
1420 reg1 = State.regs[REG_D0 + REG1 (insn)];
1421 reg2 = State.regs[REG_D0 + REG0 (insn)];
1422 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1423
1424 z = (value == 0);
1425 n = (value & 0x80000000);
1426 c = (reg1 > reg2);
1427 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1428 && (reg2 & 0x80000000) != (value & 0x80000000));
1429
1430 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1431 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1432 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1433 State.regs[REG_D0 + REG0 (insn)] = value;
1434}
1435
1436/* mul dm, dn */
1437void OP_F240 (insn, extension)
1438 unsigned long insn, extension;
1439{
1440 unsigned long long temp;
1441 int n, z;
1442
1443 temp = (State.regs[REG_D0 + REG0 (insn)]
1444 * State.regs[REG_D0 + REG1 (insn)]);
1445 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1446 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1447 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1448 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1449 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1450 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1451}
1452
1453/* mulu dm, dn */
1454void OP_F250 (insn, extension)
1455 unsigned long insn, extension;
1456{
1457 unsigned long long temp;
1458 int n, z;
1459
1460 temp = (State.regs[REG_D0 + REG0 (insn)]
1461 * State.regs[REG_D0 + REG1 (insn)]);
1462 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1463 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1464 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1465 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1466 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1467 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1468}
1469
1470/* div dm, dn */
1471void OP_F260 (insn, extension)
1472 unsigned long insn, extension;
1473{
1474 long long temp;
1475 int n, z;
1476
1477 temp = State.regs[REG_MDR];
1478 temp <<= 32;
1479 temp |= State.regs[REG_D0 + REG0 (insn)];
1480 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + REG1 (insn)];
1481 temp /= (long)State.regs[REG_D0 + REG1 (insn)];
1482 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1483 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1484 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1485 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1486 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1487 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1488}
1489
1490/* divu dm, dn */
1491void OP_F270 (insn, extension)
1492 unsigned long insn, extension;
1493{
1494 unsigned long long temp;
1495 int n, z;
1496
1497 temp = State.regs[REG_MDR];
1498 temp <<= 32;
1499 temp |= State.regs[REG_D0 + REG0 (insn)];
1500 State.regs[REG_MDR] = temp % State.regs[REG_D0 + REG1 (insn)];
1501 temp /= State.regs[REG_D0 + REG1 (insn)];
1502 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1503 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1504 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1505 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1506 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1507 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1508}
1509
1510/* inc dn */
1511void OP_40 (insn, extension)
1512 unsigned long insn, extension;
1513{
1514 int z,n,c,v;
1515 unsigned int value, imm, reg1;
1516
1517 reg1 = State.regs[REG_D0 + REG1 (insn)];
1518 imm = 1;
1519 value = reg1 + imm;
1520 State.regs[REG_D0 + REG1 (insn)] = value;
1521
1522 z = (value == 0);
1523 n = (value & 0x80000000);
1524 c = (reg1 < imm);
1525 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1526 && (reg1 & 0x80000000) != (value & 0x80000000));
1527
1528 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1529 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1530 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1531}
1532
1533/* inc an */
1534void OP_41 (insn, extension)
1535 unsigned long insn, extension;
1536{
1537 State.regs[REG_A0 + REG1 (insn)] += 1;
1538}
1539
1540/* inc4 an */
1541void OP_50 (insn, extension)
1542 unsigned long insn, extension;
1543{
1544 State.regs[REG_A0 + REG0 (insn)] += 4;
1545}
1546
1547/* cmp imm8, dn */
1548void OP_A000 (insn, extension)
1549 unsigned long insn, extension;
1550{
1551 int z, c, n, v;
1552 unsigned long reg1, imm, value;
1553
1554 reg1 = State.regs[REG_D0 + REG0_8 (insn)];
1555 imm = SEXT8 (insn & 0xff);
1556 value = reg1 - imm;
1557
1558 z = (value == 0);
1559 n = (value & 0x80000000);
1560 c = (reg1 < imm);
1561 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1562 && (reg1 & 0x80000000) != (value & 0x80000000));
1563
1564 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1565 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1566 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1567}
1568
1569/* cmp dm, dn */
1570void OP_A0 (insn, extension)
1571 unsigned long insn, extension;
1572{
1573 int z, c, n, v;
1574 unsigned long reg1, reg2, value;
1575
1576 reg1 = State.regs[REG_D0 + REG1 (insn)];
1577 reg2 = State.regs[REG_D0 + REG0 (insn)];
1578 value = reg2 - reg1;
1579
1580 z = (value == 0);
1581 n = (value & 0x80000000);
1582 c = (reg1 > reg2);
1583 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1584 && (reg2 & 0x80000000) != (value & 0x80000000));
1585
1586 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1587 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1588 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1589}
1590
1591/* cmp dm, an */
1592void OP_F1A0 (insn, extension)
1593 unsigned long insn, extension;
1594{
1595 int z, c, n, v;
1596 unsigned long reg1, reg2, value;
1597
1598 reg1 = State.regs[REG_D0 + REG1 (insn)];
1599 reg2 = State.regs[REG_A0 + REG0 (insn)];
1600 value = reg2 - reg1;
1601
1602 z = (value == 0);
1603 n = (value & 0x80000000);
1604 c = (reg1 > reg2);
1605 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1606 && (reg2 & 0x80000000) != (value & 0x80000000));
1607
1608 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1609 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1610 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1611}
1612
1613/* cmp am, dn */
1614void OP_F190 (insn, extension)
1615 unsigned long insn, extension;
1616{
1617 int z, c, n, v;
1618 unsigned long reg1, reg2, value;
1619
1620 reg1 = State.regs[REG_A0 + REG1 (insn)];
1621 reg2 = State.regs[REG_D0 + REG0 (insn)];
1622 value = reg2 - reg1;
1623
1624 z = (value == 0);
1625 n = (value & 0x80000000);
1626 c = (reg1 > reg2);
1627 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1628 && (reg2 & 0x80000000) != (value & 0x80000000));
1629
1630 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1631 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1632 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1633}
1634
1635/* cmp imm8, an */
1636void OP_B000 (insn, extension)
1637 unsigned long insn, extension;
1638{
1639 int z, c, n, v;
1640 unsigned long reg1, imm, value;
1641
1642 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
1643 imm = insn & 0xff;
1644 value = reg1 - imm;
1645
1646 z = (value == 0);
1647 n = (value & 0x80000000);
1648 c = (reg1 < imm);
1649 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1650 && (reg1 & 0x80000000) != (value & 0x80000000));
1651
1652 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1653 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1654 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1655}
1656
1657/* cmp am, an */
1658void OP_B0 (insn, extension)
1659 unsigned long insn, extension;
1660{
1661 int z, c, n, v;
1662 unsigned long reg1, reg2, value;
1663
1664 reg1 = State.regs[REG_A0 + REG1 (insn)];
1665 reg2 = State.regs[REG_A0 + REG0 (insn)];
1666 value = reg2 - reg1;
1667
1668 z = (value == 0);
1669 n = (value & 0x80000000);
1670 c = (reg1 > reg2);
1671 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1672 && (reg2 & 0x80000000) != (value & 0x80000000));
1673
1674 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1675 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1676 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1677}
1678
1679/* cmp imm16, dn */
1680void OP_FAC80000 (insn, extension)
1681 unsigned long insn, extension;
1682{
1683 int z, c, n, v;
1684 unsigned long reg1, imm, value;
1685
1686 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1687 imm = SEXT16 (insn & 0xffff);
1688 value = reg1 - imm;
1689
1690 z = (value == 0);
1691 n = (value & 0x80000000);
1692 c = (reg1 < imm);
1693 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1694 && (reg1 & 0x80000000) != (value & 0x80000000));
1695
1696 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1697 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1698 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1699}
1700
1701/* cmp imm32, dn */
1702void OP_FCC80000 (insn, extension)
1703 unsigned long insn, extension;
1704{
1705 int z, c, n, v;
1706 unsigned long reg1, imm, value;
1707
1708 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1709 imm = ((insn & 0xffff) << 16) + extension;
1710 value = reg1 - imm;
1711
1712 z = (value == 0);
1713 n = (value & 0x80000000);
1714 c = (reg1 < imm);
1715 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1716 && (reg1 & 0x80000000) != (value & 0x80000000));
1717
1718 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1719 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1720 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1721}
1722
1723/* cmp imm16, an */
1724void OP_FAD80000 (insn, extension)
1725 unsigned long insn, extension;
1726{
1727 int z, c, n, v;
1728 unsigned long reg1, imm, value;
1729
1730 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1731 imm = insn & 0xffff;
1732 value = reg1 - imm;
1733
1734 z = (value == 0);
1735 n = (value & 0x80000000);
1736 c = (reg1 < imm);
1737 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1738 && (reg1 & 0x80000000) != (value & 0x80000000));
1739
1740 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1741 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1742 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1743}
1744
1745/* cmp imm32, an */
1746void OP_FCD80000 (insn, extension)
1747 unsigned long insn, extension;
1748{
1749 int z, c, n, v;
1750 unsigned long reg1, imm, value;
1751
1752 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1753 imm = ((insn & 0xffff) << 16) + extension;
1754 value = reg1 - imm;
1755
1756 z = (value == 0);
1757 n = (value & 0x80000000);
1758 c = (reg1 < imm);
1759 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1760 && (reg1 & 0x80000000) != (value & 0x80000000));
1761
1762 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1763 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1764 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1765}
1766
1767/* and dm, dn */
1768void OP_F200 (insn, extension)
1769 unsigned long insn, extension;
1770{
1771 int n, z;
1772
1773 State.regs[REG_D0 + REG0 (insn)] &= State.regs[REG_D0 + REG1 (insn)];
1774 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1775 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1776 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1778}
1779
1780/* and imm8, dn */
1781void OP_F8E000 (insn, extension)
1782 unsigned long insn, extension;
1783{
1784 int n, z;
1785
1786 State.regs[REG_D0 + REG0_8 (insn)] &= (insn & 0xff);
1787 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
1788 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
1789 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1790 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1791}
1792
1793/* and imm16, dn */
1794void OP_FAE00000 (insn, extension)
1795 unsigned long insn, extension;
1796{
1797 int n, z;
1798
1799 State.regs[REG_D0 + REG0_16 (insn)] &= (insn & 0xffff);
1800 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1801 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1802 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1803 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1804}
1805
1806/* and imm32, dn */
1807void OP_FCE00000 (insn, extension)
1808 unsigned long insn, extension;
1809{
1810 int n, z;
1811
1812 State.regs[REG_D0 + REG0_16 (insn)]
1813 &= ((insn & 0xffff) << 16) + extension;
1814 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1815 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1816 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1817 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1818}
1819
1820/* and imm16, psw */
1821void OP_FAFC0000 (insn, extension)
1822 unsigned long insn, extension;
1823{
1824 PSW &= (insn & 0xffff);
1825}
1826
1827/* or dm, dn*/
1828void OP_F210 (insn, extension)
1829 unsigned long insn, extension;
1830{
1831 int n, z;
1832
1833 State.regs[REG_D0 + REG0 (insn)] |= State.regs[REG_D0 + REG1 (insn)];
1834 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1835 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1836 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1837 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1838}
1839
1840/* or imm8, dn */
1841void OP_F8E400 (insn, extension)
1842 unsigned long insn, extension;
1843{
1844 int n, z;
1845
1846 State.regs[REG_D0 + REG0_8 (insn)] |= insn & 0xff;
1847 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
1848 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
1849 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1850 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1851}
1852
1853/* or imm16, dn*/
1854void OP_FAE40000 (insn, extension)
1855 unsigned long insn, extension;
1856{
1857 int n, z;
1858
1859 State.regs[REG_D0 + REG0_16 (insn)] |= insn & 0xffff;
1860 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1861 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1862 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1863 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1864}
1865
1866/* or imm32, dn */
1867void OP_FCE40000 (insn, extension)
1868 unsigned long insn, extension;
1869{
1870 int n, z;
1871
1872 State.regs[REG_D0 + REG0_16 (insn)]
1873 |= ((insn & 0xffff) << 16) + extension;
1874 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1875 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1877 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1878}
1879
1880/* or imm16,psw */
1881void OP_FAFD0000 (insn, extension)
1882 unsigned long insn, extension;
1883{
1884 PSW |= (insn & 0xffff);
1885}
1886
1887/* xor dm, dn*/
1888void OP_F220 (insn, extension)
1889 unsigned long insn, extension;
1890{
1891 int n, z;
1892
1893 State.regs[REG_D0 + REG0 (insn)] ^= State.regs[REG_D0 + REG1 (insn)];
1894 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1895 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1896 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1897 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1898}
1899
1900/* xor imm16, dn */
1901void OP_FAE80000 (insn, extension)
1902 unsigned long insn, extension;
1903{
1904 int n, z;
1905
1906 State.regs[REG_D0 + REG0_16 (insn)] ^= insn & 0xffff;
1907 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1908 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1909 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1910 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1911}
1912
1913/* xor imm32, dn */
1914void OP_FCE80000 (insn, extension)
1915 unsigned long insn, extension;
1916{
1917 int n, z;
1918
1919 State.regs[REG_D0 + REG0_16 (insn)]
1920 ^= ((insn & 0xffff) << 16) + extension;
1921 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1922 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1923 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1924 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1925}
1926
1927/* not dn */
1928void OP_F230 (insn, extension)
1929 unsigned long insn, extension;
1930{
1931 int n, z;
1932
1933 State.regs[REG_D0 + REG0 (insn)] = ~State.regs[REG_D0 + REG0 (insn)];
1934 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1935 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1936 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1937 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1938}
1939
1940/* btst imm8, dn */
1941void OP_F8EC00 (insn, extension)
1942 unsigned long insn, extension;
1943{
1944 unsigned long temp;
1945 int z, n;
1946
1947 temp = State.regs[REG_D0 + REG0_8 (insn)];
1948 temp &= (insn & 0xff);
1949 n = (temp & 0x80000000) != 0;
1950 z = (temp == 0);
1951 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1952 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1953}
1954
1955/* btst imm16, dn */
1956void OP_FAEC0000 (insn, extension)
1957 unsigned long insn, extension;
1958{
1959 unsigned long temp;
1960 int z, n;
1961
1962 temp = State.regs[REG_D0 + REG0_16 (insn)];
1963 temp &= (insn & 0xffff);
1964 n = (temp & 0x80000000) != 0;
1965 z = (temp == 0);
1966 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1967 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1968}
1969
1970/* btst imm32, dn */
1971void OP_FCEC0000 (insn, extension)
1972 unsigned long insn, extension;
1973{
1974 unsigned long temp;
1975 int z, n;
1976
1977 temp = State.regs[REG_D0 + REG0_16 (insn)];
1978 temp &= ((insn & 0xffff) << 16) + extension;
1979 n = (temp & 0x80000000) != 0;
1980 z = (temp == 0);
1981 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1982 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1983}
1984
1985/* btst imm8,(abs32) */
1986void OP_FE020000 (insn, extension)
1987 unsigned long insn, extension;
1988{
1989 unsigned long temp;
1990 int n, z;
1991
1992 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1993 temp &= (extension & 0xff);
1994 n = (temp & 0x80000000) != 0;
1995 z = (temp == 0);
1996 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1997 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1998}
1999
2000/* btst imm8,(d8,an) */
2001void OP_FAF80000 (insn, extension)
2002 unsigned long insn, extension;
2003{
2004 unsigned long temp;
2005 int n, z;
2006
2007 temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
2008 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2009 temp &= (insn & 0xff);
2010 n = (temp & 0x80000000) != 0;
2011 z = (temp == 0);
2012 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2013 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2014}
2015
2016/* bset dm, (an) */
2017void OP_F080 (insn, extension)
2018 unsigned long insn, extension;
2019{
2020 unsigned long temp;
2021 int z;
2022
2023 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
2024 z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
2025 temp |= State.regs[REG_D0 + REG1 (insn)];
2026 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
2027 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2028 PSW |= (z ? PSW_Z : 0);
2029}
2030
2031/* bset imm8, (abs32) */
2032void OP_FE000000 (insn, extension)
2033 unsigned long insn, extension;
2034{
2035 unsigned long temp;
2036 int z;
2037
2038 temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
2039 z = (temp & (extension & 0xff)) == 0;
2040 temp |= (extension & 0xff);
2041 store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
2042 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2043 PSW |= (z ? PSW_Z : 0);
2044}
2045
2046/* bset imm8,(d8,an) */
2047void OP_FAF00000 (insn, extension)
2048 unsigned long insn, extension;
2049{
2050 unsigned long temp;
2051 int z;
2052
2053 temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
2054 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2055 z = (temp & (insn & 0xff)) == 0;
2056 temp |= (insn & 0xff);
2057 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
2058 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2059 PSW |= (z ? PSW_Z : 0);
2060}
2061
2062/* bclr dm, (an) */
2063void OP_F090 (insn, extension)
2064 unsigned long insn, extension;
2065{
2066 unsigned long temp;
2067 int z;
2068
2069 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
2070 z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
2071 temp = ~temp & State.regs[REG_D0 + REG1 (insn)];
2072 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
2073 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2074 PSW |= (z ? PSW_Z : 0);
2075}
2076
2077/* bclr imm8, (abs32) */
2078void OP_FE010000 (insn, extension)
2079 unsigned long insn, extension;
2080{
2081 unsigned long temp;
2082 int z;
2083
2084 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
2085 z = (temp & (extension & 0xff)) == 0;
2086 temp = ~temp & (extension & 0xff);
2087 store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
2088 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2089 PSW |= (z ? PSW_Z : 0);
2090}
2091
2092/* bclr imm8,(d8,an) */
2093void OP_FAF40000 (insn, extension)
2094 unsigned long insn, extension;
2095{
2096 unsigned long temp;
2097 int z;
2098
2099 temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
2100 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2101 z = (temp & (insn & 0xff)) == 0;
2102 temp = ~temp & (insn & 0xff);
2103 store_mem (State.regs[REG_A0 + REG0_16 (insn)], 1, temp);
2104 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2105 PSW |= (z ? PSW_Z : 0);
2106}
2107
2108/* asr dm, dn */
2109void OP_F2B0 (insn, extension)
2110 unsigned long insn, extension;
2111{
2112 long temp;
2113 int z, n, c;
2114
2115 temp = State.regs[REG_D0 + REG0 (insn)];
2116 c = temp & 1;
2117 temp >>= State.regs[REG_D0 + REG1 (insn)];
2118 State.regs[REG_D0 + REG0 (insn)] = temp;
2119 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2120 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2121 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2122 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2123}
2124
2125/* asr imm8, dn */
2126void OP_F8C800 (insn, extension)
2127 unsigned long insn, extension;
2128{
2129 long temp;
2130 int z, n, c;
2131
2132 temp = State.regs[REG_D0 + REG0_8 (insn)];
2133 c = temp & 1;
2134 temp >>= (insn & 0xff);
2135 State.regs[REG_D0 + REG0_8 (insn)] = temp;
2136 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2137 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2138 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2139 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2140}
2141
2142/* lsr dm, dn */
2143void OP_F2A0 (insn, extension)
2144 unsigned long insn, extension;
2145{
2146 int z, n, c;
2147
2148 c = State.regs[REG_D0 + REG0 (insn)] & 1;
2149 State.regs[REG_D0 + REG0 (insn)]
2150 >>= State.regs[REG_D0 + REG1 (insn)];
2151 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2152 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2153 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2154 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2155}
2156
2157/* lsr dm, dn */
2158void OP_F8C400 (insn, extension)
2159 unsigned long insn, extension;
2160{
2161 int z, n, c;
2162
2163 c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
2164 State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff);
2165 z = (State.regs[REG_D0 + (REG0 (insn) >> 8)] == 0);
2166 n = (State.regs[REG_D0 + (REG0 (insn) >> 8)] & 0x80000000) != 0;
2167 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2168 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2169}
2170
2171/* asl dm, dn */
2172void OP_F290 (insn, extension)
2173 unsigned long insn, extension;
2174{
2175 int n, z;
2176
2177 State.regs[REG_D0 + REG0 (insn)]
2178 <<= State.regs[REG_D0 + REG1 (insn)];
2179 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2180 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2181 PSW &= ~(PSW_Z | PSW_N);
2182 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2183}
2184
2185/* asl imm8, dn */
2186void OP_F8C000 (insn, extension)
2187 unsigned long insn, extension;
2188{
2189 int n, z;
2190
2191 State.regs[REG_D0 + REG0_8 (insn)] <<= (insn & 0xff);
2192 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2193 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2194 PSW &= ~(PSW_Z | PSW_N);
2195 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2196}
2197
2198/* asl2 dn */
2199void OP_54 (insn, extension)
2200 unsigned long insn, extension;
2201{
2202 int n, z;
2203
2204 State.regs[REG_D0 + REG0 (insn)] <<= 2;
2205 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2206 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2207 PSW &= ~(PSW_Z | PSW_N);
2208 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2209}
2210
2211/* ror dn */
2212void OP_F284 (insn, extension)
2213 unsigned long insn, extension;
2214{
2215 unsigned long value;
2216 int c,n,z;
2217
2218 value = State.regs[REG_D0 + REG0 (insn)];
2219 c = (value & 0x1);
2220
2221 value >>= 1;
2222 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2223 State.regs[REG_D0 + REG0 (insn)] = value;
2224 z = (value == 0);
2225 n = (value & 0x80000000) != 0;
2226 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2227 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2228}
2229
2230/* rol dn */
2231void OP_F280 (insn, extension)
2232 unsigned long insn, extension;
2233{
2234 unsigned long value;
2235 int c,n,z;
2236
2237 value = State.regs[REG_D0 + REG0 (insn)];
2238 c = (value & 0x80000000) ? 1 : 0;
2239
2240 value <<= 1;
2241 value |= ((PSW & PSW_C) != 0);
2242 State.regs[REG_D0 + REG0 (insn)] = value;
2243 z = (value == 0);
2244 n = (value & 0x80000000) != 0;
2245 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2246 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2247}
2248
2249/* beq label:8 */
2250void OP_C800 (insn, extension)
2251 unsigned long insn, extension;
2252{
2253 /* The dispatching code will add 2 after we return, so
2254 we subtract two here to make things right. */
2255 if (PSW & PSW_Z)
2256 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2257}
2258
2259/* bne label:8 */
2260void OP_C900 (insn, extension)
2261 unsigned long insn, extension;
2262{
2263 /* The dispatching code will add 2 after we return, so
2264 we subtract two here to make things right. */
2265 if (!(PSW & PSW_Z))
2266 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2267}
2268
2269/* bgt label:8 */
2270void OP_C100 (insn, extension)
2271 unsigned long insn, extension;
2272{
2273 /* The dispatching code will add 2 after we return, so
2274 we subtract two here to make things right. */
2275 if (!((PSW & PSW_Z)
2276 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2277 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2278}
2279
2280/* bge label:8 */
2281void OP_C200 (insn, extension)
2282 unsigned long insn, extension;
2283{
2284 /* The dispatching code will add 2 after we return, so
2285 we subtract two here to make things right. */
2286 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2287 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2288}
2289
2290/* ble label:8 */
2291void OP_C300 (insn, extension)
2292 unsigned long insn, extension;
2293{
2294 /* The dispatching code will add 2 after we return, so
2295 we subtract two here to make things right. */
2296 if ((PSW & PSW_Z)
2297 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2298 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2299}
2300
2301/* blt label:8 */
2302void OP_C000 (insn, extension)
2303 unsigned long insn, extension;
2304{
2305 /* The dispatching code will add 2 after we return, so
2306 we subtract two here to make things right. */
2307 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2308 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2309}
2310
2311/* bhi label:8 */
2312void OP_C500 (insn, extension)
2313 unsigned long insn, extension;
2314{
2315 /* The dispatching code will add 2 after we return, so
2316 we subtract two here to make things right. */
2317 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2318 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2319}
2320
2321/* bcc label:8 */
2322void OP_C600 (insn, extension)
2323 unsigned long insn, extension;
2324{
2325 /* The dispatching code will add 2 after we return, so
2326 we subtract two here to make things right. */
2327 if (!(PSW & PSW_C))
2328 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2329}
2330
2331/* bls label:8 */
2332void OP_C700 (insn, extension)
2333 unsigned long insn, extension;
2334{
2335 /* The dispatching code will add 2 after we return, so
2336 we subtract two here to make things right. */
2337 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2338 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2339}
2340
2341/* bcs label:8 */
2342void OP_C400 (insn, extension)
2343 unsigned long insn, extension;
2344{
2345 /* The dispatching code will add 2 after we return, so
2346 we subtract two here to make things right. */
2347 if (PSW & PSW_C)
2348 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2349}
2350
2351/* bvc label:8 */
2352void OP_F8E800 (insn, extension)
2353 unsigned long insn, extension;
2354{
2355 /* The dispatching code will add 3 after we return, so
2356 we subtract two here to make things right. */
2357 if (!(PSW & PSW_V))
2358 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2359}
2360
2361/* bvs label:8 */
2362void OP_F8E900 (insn, extension)
2363 unsigned long insn, extension;
2364{
2365 /* The dispatching code will add 3 after we return, so
2366 we subtract two here to make things right. */
2367 if (PSW & PSW_V)
2368 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2369}
2370
2371/* bnc label:8 */
2372void OP_F8EA00 (insn, extension)
2373 unsigned long insn, extension;
2374{
2375 /* The dispatching code will add 3 after we return, so
2376 we subtract two here to make things right. */
2377 if (!(PSW & PSW_N))
2378 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2379}
2380
2381/* bns label:8 */
2382void OP_F8EB00 (insn, extension)
2383 unsigned long insn, extension;
2384{
2385 /* The dispatching code will add 3 after we return, so
2386 we subtract two here to make things right. */
2387 if (PSW & PSW_N)
2388 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2389}
2390
2391/* bra label:8 */
2392void OP_CA00 (insn, extension)
2393 unsigned long insn, extension;
2394{
2395 /* The dispatching code will add 2 after we return, so
2396 we subtract two here to make things right. */
2397 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2398}
2399
2400/* leq */
2401void OP_D8 (insn, extension)
2402 unsigned long insn, extension;
2403{
2404 abort ();
2405}
2406
2407/* lne */
2408void OP_D9 (insn, extension)
2409 unsigned long insn, extension;
2410{
2411 abort ();
2412}
2413
2414/* lgt */
2415void OP_D1 (insn, extension)
2416 unsigned long insn, extension;
2417{
2418 abort ();
2419}
2420
2421/* lge */
2422void OP_D2 (insn, extension)
2423 unsigned long insn, extension;
2424{
2425 abort ();
2426}
2427
2428/* lle */
2429void OP_D3 (insn, extension)
2430 unsigned long insn, extension;
2431{
2432 abort ();
2433}
2434
2435/* llt */
2436void OP_D0 (insn, extension)
2437 unsigned long insn, extension;
2438{
2439 abort ();
2440}
2441
2442/* lhi */
2443void OP_D5 (insn, extension)
2444 unsigned long insn, extension;
2445{
2446 abort ();
2447}
2448
2449/* lcc */
2450void OP_D6 (insn, extension)
2451 unsigned long insn, extension;
2452{
2453 abort ();
2454}
2455
2456/* lls */
2457void OP_D7 (insn, extension)
2458 unsigned long insn, extension;
2459{
2460 abort ();
2461}
2462
2463/* lcs */
2464void OP_D4 (insn, extension)
2465 unsigned long insn, extension;
2466{
2467 abort ();
2468}
2469
2470/* lra */
2471void OP_DA (insn, extension)
2472 unsigned long insn, extension;
2473{
2474 abort ();
2475}
2476
2477/* setlb */
2478void OP_DB (insn, extension)
2479 unsigned long insn, extension;
2480{
2481 abort ();
2482}
2483
2484/* jmp (an) */
2485void OP_F0F4 (insn, extension)
2486 unsigned long insn, extension;
2487{
2488 State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
2489}
2490
2491/* jmp label:16 */
2492void OP_CC0000 (insn, extension)
2493 unsigned long insn, extension;
2494{
2495 State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3;
2496}
2497
2498/* jmp label:32 */
2499void OP_DC000000 (insn, extension)
2500 unsigned long insn, extension;
2501{
2502 State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5;
2503}
2504
2505/* call label:16,reg_list,imm8 */
2506void OP_CD000000 (insn, extension)
2507 unsigned long insn, extension;
2508{
2509 unsigned int next_pc, sp, adjust;
2510 unsigned long mask;
2511
2512 sp = State.regs[REG_SP];
2513 next_pc = State.regs[REG_PC] + 2;
2514 State.mem[sp] = next_pc & 0xff;
2515 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2516 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2517 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2518
2519 mask = insn & 0xff;
2520
2521 adjust = 0;
2522 if (mask & 0x80)
2523 {
2524 adjust -= 4;
2525 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2526 }
2527
2528 if (mask & 0x40)
2529 {
2530 adjust -= 4;
2531 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2532 }
2533
2534 if (mask & 0x20)
2535 {
2536 adjust -= 4;
2537 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2538 }
2539
2540 if (mask & 0x10)
2541 {
2542 adjust -= 4;
2543 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2544 }
2545
2546 if (mask & 0x8)
2547 {
2548 adjust -= 4;
2549 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2550 adjust -= 4;
2551 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2552 adjust -= 4;
2553 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2554 adjust -= 4;
2555 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2556 adjust -= 4;
2557 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2558 adjust -= 4;
2559 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2560 adjust -= 4;
2561 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2562 adjust -= 4;
2563 }
2564
2565 /* And make sure to update the stack pointer. */
2566 State.regs[REG_SP] -= extension;
2567 State.regs[REG_MDR] = next_pc;
2568 State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2569}
2570
2571/* call label:32,reg_list,imm8*/
2572void OP_DD000000 (insn, extension)
2573 unsigned long insn, extension;
2574{
2575 unsigned int next_pc, sp, adjust;
2576 unsigned long mask;
2577
2578 sp = State.regs[REG_SP];
2579 next_pc = State.regs[REG_PC] + 2;
2580 State.mem[sp] = next_pc & 0xff;
2581 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2582 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2583 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2584
2585 mask = (extension & 0xff00) >> 8;
2586
2587 adjust = 0;
2588 if (mask & 0x80)
2589 {
2590 adjust -= 4;
2591 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2592 }
2593
2594 if (mask & 0x40)
2595 {
2596 adjust -= 4;
2597 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2598 }
2599
2600 if (mask & 0x20)
2601 {
2602 adjust -= 4;
2603 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2604 }
2605
2606 if (mask & 0x10)
2607 {
2608 adjust -= 4;
2609 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2610 }
2611
2612 if (mask & 0x8)
2613 {
2614 adjust -= 4;
2615 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2616 adjust -= 4;
2617 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2618 adjust -= 4;
2619 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2620 adjust -= 4;
2621 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2622 adjust -= 4;
2623 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2624 adjust -= 4;
2625 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2626 adjust -= 4;
2627 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2628 adjust -= 4;
2629 }
2630
2631 /* And make sure to update the stack pointer. */
2632 State.regs[REG_SP] -= (extension & 0xff);
2633 State.regs[REG_MDR] = next_pc;
2634 State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2635}
2636
2637/* calls (an) */
2638void OP_F0F0 (insn, extension)
2639 unsigned long insn, extension;
2640{
2641 unsigned int next_pc, sp;
2642
2643 sp = State.regs[REG_SP];
2644 next_pc = State.regs[REG_PC] + 2;
2645 State.mem[sp] = next_pc & 0xff;
2646 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2647 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2648 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2649 State.regs[REG_MDR] = next_pc;
2650 State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
2651}
2652
2653/* calls label:16 */
2654void OP_FAFF0000 (insn, extension)
2655 unsigned long insn, extension;
2656{
2657 unsigned int next_pc, sp;
2658
2659 sp = State.regs[REG_SP];
2660 next_pc = State.regs[REG_PC] + 4;
2661 State.mem[sp] = next_pc & 0xff;
2662 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2663 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2664 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2665 State.regs[REG_MDR] = next_pc;
2666 State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4;
2667}
2668
2669/* calls label:32 */
2670void OP_FCFF0000 (insn, extension)
2671 unsigned long insn, extension;
2672{
2673 unsigned int next_pc, sp;
2674
2675 sp = State.regs[REG_SP];
2676 next_pc = State.regs[REG_PC] + 6;
2677 State.mem[sp] = next_pc & 0xff;
2678 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2679 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2680 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2681 State.regs[REG_MDR] = next_pc;
2682 State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6;
2683}
2684
2685/* ret reg_list, imm8 */
2686void OP_DF0000 (insn, extension)
2687 unsigned long insn, extension;
2688{
2689 unsigned int sp;
2690 unsigned long mask;
2691
2692 State.regs[REG_SP] += insn & 0xff;
2693 sp = State.regs[REG_SP];
2694
2695 mask = (insn & 0xff00) >> 8;
2696
2697 if (mask & 0x8)
2698 {
2699 sp += 4;
2700 State.regs[REG_LAR] = load_mem (sp, 4);
2701 sp += 4;
2702 State.regs[REG_LIR] = load_mem (sp, 4);
2703 sp += 4;
2704 State.regs[REG_MDR] = load_mem (sp, 4);
2705 sp += 4;
2706 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2707 sp += 4;
2708 State.regs[REG_A0] = load_mem (sp, 4);
2709 sp += 4;
2710 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2711 sp += 4;
2712 State.regs[REG_D0] = load_mem (sp, 4);
2713 sp += 4;
2714 }
2715
2716 if (mask & 0x10)
2717 {
2718 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2719 sp += 4;
2720 }
2721
2722 if (mask & 0x20)
2723 {
2724 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2725 sp += 4;
2726 }
2727
2728 if (mask & 0x40)
2729 {
2730 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2731 sp += 4;
2732 }
2733
2734 if (mask & 0x80)
2735 {
2736 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2737 sp += 4;
2738 }
2739
2740 /* And make sure to update the stack pointer. */
2741 State.regs[REG_SP] = sp;
2742
2743 /* Restore the PC value. */
2744 State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
2745 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2746 State.regs[REG_PC] -= 3;
2747}
2748
2749/* retf reg_list,imm8 */
2750void OP_DE0000 (insn, extension)
2751 unsigned long insn, extension;
2752{
2753 unsigned int sp;
2754 unsigned long mask;
2755
2756 sp = State.regs[REG_SP] + (insn & 0xff);
2757 State.regs[REG_SP] = sp;
2758 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
2759
2760 sp = State.regs[REG_SP];
2761
2762 mask = (insn & 0xff00) >> 8;
2763
2764 if (mask & 0x8)
2765 {
2766 sp += 4;
2767 State.regs[REG_LAR] = load_mem (sp, 4);
2768 sp += 4;
2769 State.regs[REG_LIR] = load_mem (sp, 4);
2770 sp += 4;
2771 State.regs[REG_MDR] = load_mem (sp, 4);
2772 sp += 4;
2773 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2774 sp += 4;
2775 State.regs[REG_A0] = load_mem (sp, 4);
2776 sp += 4;
2777 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2778 sp += 4;
2779 State.regs[REG_D0] = load_mem (sp, 4);
2780 sp += 4;
2781 }
2782
2783 if (mask & 0x10)
2784 {
2785 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2786 sp += 4;
2787 }
2788
2789 if (mask & 0x20)
2790 {
2791 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2792 sp += 4;
2793 }
2794
2795 if (mask & 0x40)
2796 {
2797 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2798 sp += 4;
2799 }
2800
2801 if (mask & 0x80)
2802 {
2803 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2804 sp += 4;
2805 }
2806
2807 /* And make sure to update the stack pointer. */
2808 State.regs[REG_SP] = sp;
2809}
2810
2811/* rets */
2812void OP_F0FC (insn, extension)
2813 unsigned long insn, extension;
2814{
2815 unsigned int sp;
2816
2817 sp = State.regs[REG_SP];
2818 State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
2819 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2820 State.regs[REG_PC] -= 2;
2821}
2822
2823/* rti */
2824void OP_F0FD (insn, extension)
2825 unsigned long insn, extension;
2826{
2827 abort ();
2828}
2829
2830/* trap */
2831void OP_F0FE (insn, extension)
2832 unsigned long insn, extension;
2833{
2834 /* We use this for simulated system calls; we may need to change
2835 it to a reserved instruction if we conflict with uses at
2836 Matsushita. */
2837 int save_errno = errno;
2838 errno = 0;
2839
2840/* Registers passed to trap 0 */
2841
2842/* Function number. */
2843#define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2844
2845/* Parameters. */
2846#define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2847#define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2848#define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2849
2850/* Registers set by trap 0 */
2851
2852#define RETVAL State.regs[0] /* return value */
2853#define RETERR State.regs[1] /* return error code */
2854
2855/* Turn a pointer in a register into a pointer into real memory. */
2856
2857#define MEMPTR(x) (State.mem + x)
2858
2859 switch (FUNC)
2860 {
2861#if !defined(__GO32__) && !defined(_WIN32)
2862 case SYS_fork:
2863 RETVAL = fork ();
2864 break;
2865 case SYS_execve:
2866 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2867 (char **)MEMPTR (PARM3));
2868 break;
2869 case SYS_execv:
2870 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2871 break;
2872#endif
2873
2874 case SYS_read:
2875 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2876 MEMPTR (PARM2), PARM3);
2877 break;
2878 case SYS_write:
2879 if (PARM1 == 1)
2880 RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
2881 MEMPTR (PARM2), PARM3);
2882 else
2883 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2884 MEMPTR (PARM2), PARM3);
2885 break;
2886 case SYS_lseek:
2887 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2888 break;
2889 case SYS_close:
2890 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2891 break;
2892 case SYS_open:
2893 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2894 break;
2895 case SYS_exit:
2896 /* EXIT - caller can look in PARM1 to work out the
2897 reason */
2898 if (PARM1 == 0xdead || PARM1 == 0x1)
2899 State.exception = SIGABRT;
2900 else
2901 State.exception = SIGQUIT;
2902 break;
2903
2904 case SYS_stat: /* added at hmsi */
2905 /* stat system call */
2906 {
2907 struct stat host_stat;
2908 reg_t buf;
2909
2910 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2911
2912 buf = PARM2;
2913
2914 /* Just wild-assed guesses. */
2915 store_mem (buf, 2, host_stat.st_dev);
2916 store_mem (buf + 2, 2, host_stat.st_ino);
2917 store_mem (buf + 4, 4, host_stat.st_mode);
2918 store_mem (buf + 8, 2, host_stat.st_nlink);
2919 store_mem (buf + 10, 2, host_stat.st_uid);
2920 store_mem (buf + 12, 2, host_stat.st_gid);
2921 store_mem (buf + 14, 2, host_stat.st_rdev);
2922 store_mem (buf + 16, 4, host_stat.st_size);
2923 store_mem (buf + 20, 4, host_stat.st_atime);
2924 store_mem (buf + 28, 4, host_stat.st_mtime);
2925 store_mem (buf + 36, 4, host_stat.st_ctime);
2926 }
2927 break;
2928
2929 case SYS_chown:
2930 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2931 break;
2932 case SYS_chmod:
2933 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2934 break;
2935 case SYS_time:
2936 RETVAL = time (MEMPTR (PARM1));
2937 break;
2938 case SYS_times:
2939 {
2940 struct tms tms;
2941 RETVAL = times (&tms);
2942 store_mem (PARM1, 4, tms.tms_utime);
2943 store_mem (PARM1 + 4, 4, tms.tms_stime);
2944 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2945 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2946 break;
2947 }
2948 case SYS_gettimeofday:
2949 {
2950 struct timeval t;
2951 struct timezone tz;
2952 RETVAL = gettimeofday (&t, &tz);
2953 store_mem (PARM1, 4, t.tv_sec);
2954 store_mem (PARM1 + 4, 4, t.tv_usec);
2955 store_mem (PARM2, 4, tz.tz_minuteswest);
2956 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2957 break;
2958 }
2959 case SYS_utime:
2960 /* Cast the second argument to void *, to avoid type mismatch
2961 if a prototype is present. */
2962 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2963 break;
2964 default:
2965 abort ();
2966 }
2967 RETERR = errno;
2968 errno = save_errno;
2969}
2970
2971/* rtm */
2972void OP_F0FF (insn, extension)
2973 unsigned long insn, extension;
2974{
2975 abort ();
2976}
2977
2978/* nop */
2979void OP_CB (insn, extension)
2980 unsigned long insn, extension;
2981{
2982}
2983
2984/* putx */
2985void OP_F500 (insn, extension)
2986 unsigned long insn, extension;
2987{
2988 abort ();
2989}
2990
2991/* getx */
2992void OP_F6F0 (insn, extension)
2993 unsigned long insn, extension;
2994{
2995 abort ();
2996}
2997
2998/* mulq */
2999void OP_F600 (insn, extension)
3000 unsigned long insn, extension;
3001{
3002 abort ();
3003}
3004
3005/* mulq */
3006void OP_F90000 (insn, extension)
3007 unsigned long insn, extension;
3008{
3009 abort ();
3010}
3011
3012/* mulq */
3013void OP_FB000000 (insn, extension)
3014 unsigned long insn, extension;
3015{
3016 abort ();
3017}
3018
3019/* mulq */
3020void OP_FD000000 (insn, extension)
3021 unsigned long insn, extension;
3022{
3023 abort ();
3024}
3025
3026/* mulqu */
3027void OP_F610 (insn, extension)
3028 unsigned long insn, extension;
3029{
3030 abort ();
3031}
3032
3033/* mulqu */
3034void OP_F91400 (insn, extension)
3035 unsigned long insn, extension;
3036{
3037 abort ();
3038}
3039
3040/* mulqu */
3041void OP_FB140000 (insn, extension)
3042 unsigned long insn, extension;
3043{
3044 abort ();
3045}
3046
3047/* mulqu */
3048void OP_FD140000 (insn, extension)
3049 unsigned long insn, extension;
3050{
3051 abort ();
3052}
3053
3054/* sat16 */
3055void OP_F640 (insn, extension)
3056 unsigned long insn, extension;
3057{
3058 abort ();
3059}
3060
3061/* sat24 */
3062void OP_F650 (insn, extension)
3063 unsigned long insn, extension;
3064{
3065 abort ();
3066}
3067
3068/* bsch */
3069void OP_F670 (insn, extension)
3070 unsigned long insn, extension;
3071{
3072 abort ();
3073}
3074
3075/* breakpoint */
3076void
3077OP_FF (insn, extension)
3078 unsigned long insn, extension;
3079{
3080 State.exception = SIGTRAP;
3081 PC -= 1;
3082}
3083
Empty description
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