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import gdb-1999-08-30 snapshot
[binutils.git] / gdb / sh-stub.c
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9e086581 1/* sh-stub.c -- debugging stub for the Hitachi-SH.
c906108c
SS		 2
3 NOTE!! This code has to be compiled with optimization, otherwise the
4 function inlining which generates the exception handlers won't work.
9e086581 5
c906108c
SS		 6*/
7
8/* This is originally based on an m68k software stub written by Glenn
9 Engel at HP, but has changed quite a bit.
10
11 Modifications for the SH by Ben Lee and Steve Chamberlain
12
13*/
14
15/****************************************************************************
16
17 THIS SOFTWARE IS NOT COPYRIGHTED
18
19 HP offers the following for use in the public domain. HP makes no
20 warranty with regard to the software or it's performance and the
21 user accepts the software "AS IS" with all faults.
22
23 HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
24 TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
25 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
26
27****************************************************************************/
28
29
30/* Remote communication protocol.
31
32 A debug packet whose contents are <data>
33 is encapsulated for transmission in the form:
34
35 $ <data> # CSUM1 CSUM2
36
37 <data> must be ASCII alphanumeric and cannot include characters
38 '$' or '#'. If <data> starts with two characters followed by
39 ':', then the existing stubs interpret this as a sequence number.
40
41 CSUM1 and CSUM2 are ascii hex representation of an 8-bit
42 checksum of <data>, the most significant nibble is sent first.
43 the hex digits 0-9,a-f are used.
44
45 Receiver responds with:
46
47 + - if CSUM is correct and ready for next packet
48 - - if CSUM is incorrect
49
50 <data> is as follows:
51 All values are encoded in ascii hex digits.
52
53 Request Packet
54
55 read registers g
56 reply XX....X Each byte of register data
57 is described by two hex digits.
58 Registers are in the internal order
59 for GDB, and the bytes in a register
60 are in the same order the machine uses.
61 or ENN for an error.
62
63 write regs GXX..XX Each byte of register data
64 is described by two hex digits.
65 reply OK for success
66 ENN for an error
67
68 write reg Pn...=r... Write register n... with value r...,
69 which contains two hex digits for each
70 byte in the register (target byte
71 order).
72 reply OK for success
73 ENN for an error
74 (not supported by all stubs).
75
76 read mem mAA..AA,LLLL AA..AA is address, LLLL is length.
77 reply XX..XX XX..XX is mem contents
78 Can be fewer bytes than requested
79 if able to read only part of the data.
80 or ENN NN is errno
81
82 write mem MAA..AA,LLLL:XX..XX
83 AA..AA is address,
84 LLLL is number of bytes,
85 XX..XX is data
86 reply OK for success
87 ENN for an error (this includes the case
88 where only part of the data was
89 written).
90
91 cont cAA..AA AA..AA is address to resume
92 If AA..AA is omitted,
93 resume at same address.
94
95 step sAA..AA AA..AA is address to resume
96 If AA..AA is omitted,
97 resume at same address.
98
99 last signal ? Reply the current reason for stopping.
100 This is the same reply as is generated
101 for step or cont : SAA where AA is the
102 signal number.
103
104 There is no immediate reply to step or cont.
105 The reply comes when the machine stops.
106 It is SAA AA is the "signal number"
107
108 or... TAAn...:r...;n:r...;n...:r...;
109 AA = signal number
110 n... = register number
111 r... = register contents
112 or... WAA The process exited, and AA is
113 the exit status. This is only
114 applicable for certains sorts of
115 targets.
116 kill request k
117
118 toggle debug d toggle debug flag (see 386 & 68k stubs)
119 reset r reset -- see sparc stub.
120 reserved <other> On other requests, the stub should
121 ignore the request and send an empty
122 response ($#<checksum>). This way
123 we can extend the protocol and GDB
124 can tell whether the stub it is
125 talking to uses the old or the new.
126 search tAA:PP,MM Search backwards starting at address
127 AA for a match with pattern PP and
128 mask MM. PP and MM are 4 bytes.
129 Not supported by all stubs.
130
131 general query qXXXX Request info about XXXX.
132 general set QXXXX=yyyy Set value of XXXX to yyyy.
133 query sect offs qOffsets Get section offsets. Reply is
134 Text=xxx;Data=yyy;Bss=zzz
135 console output Otext Send text to stdout. Only comes from
136 remote target.
137
138 Responses can be run-length encoded to save space. A '*' means that
139 the next character is an ASCII encoding giving a repeat count which
140 stands for that many repititions of the character preceding the '*'.
141 The encoding is n+29, yielding a printable character where n >=3
142 (which is where rle starts to win). Don't use an n > 126.
143
144 So
145 "0* " means the same as "0000". */
146
147#include <string.h>
148#include <setjmp.h>
149
9e086581
JM		 150/* Hitachi SH architecture instruction encoding masks */
151
152#define COND_BR_MASK 0xff00
153#define UCOND_DBR_MASK 0xe000
154#define UCOND_RBR_MASK 0xf0df
155#define TRAPA_MASK 0xff00
c906108c 156
9e086581
JM		 157#define COND_DISP 0x00ff
158#define UCOND_DISP 0x0fff
159#define UCOND_REG 0x0f00
c906108c 160
9e086581 161/* Hitachi SH instruction opcodes */
c906108c 162
9e086581
JM		 163#define BF_INSTR 0x8b00
164#define BT_INSTR 0x8900
165#define BRA_INSTR 0xa000
166#define BSR_INSTR 0xb000
167#define JMP_INSTR 0x402b
168#define JSR_INSTR 0x400b
169#define RTS_INSTR 0x000b
170#define RTE_INSTR 0x002b
171#define TRAPA_INSTR 0xc300
172#define SSTEP_INSTR 0xc3ff
c906108c 173
9e086581 174/* Hitachi SH processor register masks */
c906108c 175
9e086581 176#define T_BIT_MASK 0x0001
c906108c 177
c906108c
SS		 178/*
179 * BUFMAX defines the maximum number of characters in inbound/outbound
9e086581 180 * buffers. At least NUMREGBYTES*2 are needed for register packets.
c906108c
SS		 181 */
182#define BUFMAX 1024
183
184/*
185 * Number of bytes for registers
186 */
187#define NUMREGBYTES 112 /* 92 */
188
189/*
190 * typedef
191 */
192typedef void (*Function) ();
193
194/*
195 * Forward declarations
196 */
197
198static int hex (char);
199static char *mem2hex (char *, char *, int);
200static char *hex2mem (char *, char *, int);
201static int hexToInt (char **, int *);
202static void getpacket (char *);
203static void putpacket (char *);
204static void handle_buserror (void);
205static int computeSignal (int exceptionVector);
206static void handle_exception (int exceptionVector);
207void init_serial();
208
209void putDebugChar (char);
210char getDebugChar (void);
211
212/* These are in the file but in asm statements so the compiler can't see them */
213void catch_exception_4 (void);
214void catch_exception_6 (void);
215void catch_exception_9 (void);
216void catch_exception_10 (void);
217void catch_exception_11 (void);
218void catch_exception_32 (void);
219void catch_exception_33 (void);
220void catch_exception_255 (void);
221
222
223
224#define catch_exception_random catch_exception_255 /* Treat all odd ones like 255 */
225
226void breakpoint (void);
227
228
229#define init_stack_size 8*1024 /* if you change this you should also modify BINIT */
230#define stub_stack_size 8*1024
231
232int init_stack[init_stack_size] __attribute__ ((section ("stack"))) = {0};
233int stub_stack[stub_stack_size] __attribute__ ((section ("stack"))) = {0};
234
c906108c
SS		 235
236void INIT ();
237void BINIT ();
238
c906108c
SS		 239#define CPU_BUS_ERROR_VEC 9
240#define DMA_BUS_ERROR_VEC 10
241#define NMI_VEC 11
242#define INVALID_INSN_VEC 4
243#define INVALID_SLOT_VEC 6
244#define TRAP_VEC 32
245#define IO_VEC 33
246#define USER_VEC 255
247
248
c906108c
SS		 249
250char in_nmi; /* Set when handling an NMI, so we don't reenter */
251int dofault; /* Non zero, bus errors will raise exception */
252
253int *stub_sp;
254
255/* debug > 0 prints ill-formed commands in valid packets & checksum errors */
256int remote_debug;
257
258/* jump buffer used for setjmp/longjmp */
259jmp_buf remcomEnv;
260
261enum regnames
262 {
263 R0, R1, R2, R3, R4, R5, R6, R7,
264 R8, R9, R10, R11, R12, R13, R14,
265 R15, PC, PR, GBR, VBR, MACH, MACL, SR,
266 TICKS, STALLS, CYCLES, INSTS, PLR
267 };
268
269typedef struct
270 {
271 short *memAddr;
272 short oldInstr;
273 }
274stepData;
275
276int registers[NUMREGBYTES / 4];
277stepData instrBuffer;
278char stepped;
279static const char hexchars[] = "0123456789abcdef";
280char remcomInBuffer[BUFMAX];
281char remcomOutBuffer[BUFMAX];
282
283char highhex(int x)
284{
285 return hexchars[(x >> 4) & 0xf];
286}
287
288char lowhex(int x)
289{
290 return hexchars[x & 0xf];
291}
292
293/*
294 * Assembly macros
295 */
296
297#define BREAKPOINT() asm("trapa #0x20"::);
298
299
300/*
301 * Routines to handle hex data
302 */
303
304static int
305hex (char ch)
306{
307 if ((ch >= 'a') && (ch <= 'f'))
308 return (ch - 'a' + 10);
309 if ((ch >= '0') && (ch <= '9'))
310 return (ch - '0');
311 if ((ch >= 'A') && (ch <= 'F'))
312 return (ch - 'A' + 10);
313 return (-1);
314}
315
316/* convert the memory, pointed to by mem into hex, placing result in buf */
317/* return a pointer to the last char put in buf (null) */
318static char *
319mem2hex (char *mem, char *buf, int count)
320{
321 int i;
322 int ch;
323 for (i = 0; i < count; i++)
324 {
325 ch = *mem++;
326 *buf++ = highhex (ch);
327 *buf++ = lowhex (ch);
328 }
329 *buf = 0;
330 return (buf);
331}
332
333/* convert the hex array pointed to by buf into binary, to be placed in mem */
334/* return a pointer to the character after the last byte written */
335
336static char *
337hex2mem (char *buf, char *mem, int count)
338{
339 int i;
340 unsigned char ch;
341 for (i = 0; i < count; i++)
342 {
343 ch = hex (*buf++) << 4;
344 ch = ch + hex (*buf++);
345 *mem++ = ch;
346 }
347 return (mem);
348}
349
350/**********************************************/
351/* WHILE WE FIND NICE HEX CHARS, BUILD AN INT */
352/* RETURN NUMBER OF CHARS PROCESSED */
353/**********************************************/
354static int
355hexToInt (char **ptr, int *intValue)
356{
357 int numChars = 0;
358 int hexValue;
359
360 *intValue = 0;
361
362 while (**ptr)
363 {
364 hexValue = hex (**ptr);
365 if (hexValue >= 0)
366 {
367 *intValue = (*intValue << 4) | hexValue;
368 numChars++;
369 }
370 else
371 break;
372
373 (*ptr)++;
374 }
375
376 return (numChars);
377}
378
379/*
380 * Routines to get and put packets
381 */
382
383/* scan for the sequence $<data>#<checksum> */
384
385static
386void
387getpacket (char *buffer)
388{
389 unsigned char checksum;
390 unsigned char xmitcsum;
391 int i;
392 int count;
393 char ch;
394 do
395 {
396 /* wait around for the start character, ignore all other characters */
397 while ((ch = getDebugChar ()) != '$');
398 checksum = 0;
399 xmitcsum = -1;
400
401 count = 0;
402
403 /* now, read until a # or end of buffer is found */
404 while (count < BUFMAX)
405 {
406 ch = getDebugChar ();
407 if (ch == '#')
408 break;
409 checksum = checksum + ch;
410 buffer[count] = ch;
411 count = count + 1;
412 }
413 buffer[count] = 0;
414
415 if (ch == '#')
416 {
417 xmitcsum = hex (getDebugChar ()) << 4;
418 xmitcsum += hex (getDebugChar ());
419 if (checksum != xmitcsum)
420 putDebugChar ('-'); /* failed checksum */
421 else
422 {
423 putDebugChar ('+'); /* successful transfer */
424 /* if a sequence char is present, reply the sequence ID */
425 if (buffer[2] == ':')
426 {
427 putDebugChar (buffer[0]);
428 putDebugChar (buffer[1]);
429 /* remove sequence chars from buffer */
430 count = strlen (buffer);
431 for (i = 3; i <= count; i++)
432 buffer[i - 3] = buffer[i];
433 }
434 }
435 }
436 }
437 while (checksum != xmitcsum);
438
439}
440
441
53a5351d 442/* send the packet in buffer. */
c906108c
SS		 443
444static void
445putpacket (register char *buffer)
446{
447 register int checksum;
448 register int count;
449
450 /* $<packet info>#<checksum>. */
451 do
452 {
453 char *src = buffer;
454 putDebugChar ('$');
455 checksum = 0;
456
457 while (*src)
458 {
459 int runlen;
460
461 /* Do run length encoding */
462 for (runlen = 0; runlen < 100; runlen ++)
463 {
464 if (src[0] != src[runlen])
465 {
466 if (runlen > 3)
467 {
468 int encode;
469 /* Got a useful amount */
470 putDebugChar (*src);
471 checksum += *src;
472 putDebugChar ('*');
473 checksum += '*';
474 checksum += (encode = runlen + ' ' - 4);
475 putDebugChar (encode);
476 src += runlen;
477 }
478 else
479 {
480 putDebugChar (*src);
481 checksum += *src;
482 src++;
483 }
484 break;
485 }
486 }
487 }
488
489
490 putDebugChar ('#');
491 putDebugChar (highhex(checksum));
492 putDebugChar (lowhex(checksum));
493 }
494 while (getDebugChar() != '+');
495
496}
497
498
499/* a bus error has occurred, perform a longjmp
500 to return execution and allow handling of the error */
501
502void
503handle_buserror (void)
504{
505 longjmp (remcomEnv, 1);
506}
507
508/*
509 * this function takes the SH-1 exception number and attempts to
510 * translate this number into a unix compatible signal value
511 */
512static int
513computeSignal (int exceptionVector)
514{
515 int sigval;
516 switch (exceptionVector)
517 {
518 case INVALID_INSN_VEC:
519 sigval = 4;
520 break;
521 case INVALID_SLOT_VEC:
522 sigval = 4;
523 break;
524 case CPU_BUS_ERROR_VEC:
525 sigval = 10;
526 break;
527 case DMA_BUS_ERROR_VEC:
528 sigval = 10;
529 break;
530 case NMI_VEC:
531 sigval = 2;
532 break;
533
534 case TRAP_VEC:
535 case USER_VEC:
536 sigval = 5;
537 break;
538
539 default:
540 sigval = 7; /* "software generated"*/
541 break;
542 }
543 return (sigval);
544}
545
546void
547doSStep (void)
548{
549 short *instrMem;
550 int displacement;
551 int reg;
552 unsigned short opcode;
553
554 instrMem = (short *) registers[PC];
555
556 opcode = *instrMem;
557 stepped = 1;
558
559 if ((opcode & COND_BR_MASK) == BT_INSTR)
560 {
561 if (registers[SR] & T_BIT_MASK)
562 {
563 displacement = (opcode & COND_DISP) << 1;
564 if (displacement & 0x80)
565 displacement |= 0xffffff00;
566 /*
567 * Remember PC points to second instr.
568 * after PC of branch ... so add 4
569 */
570 instrMem = (short *) (registers[PC] + displacement + 4);
571 }
572 else
573 instrMem += 1;
574 }
575 else if ((opcode & COND_BR_MASK) == BF_INSTR)
576 {
577 if (registers[SR] & T_BIT_MASK)
578 instrMem += 1;
579 else
580 {
581 displacement = (opcode & COND_DISP) << 1;
582 if (displacement & 0x80)
583 displacement |= 0xffffff00;
584 /*
585 * Remember PC points to second instr.
586 * after PC of branch ... so add 4
587 */
588 instrMem = (short *) (registers[PC] + displacement + 4);
589 }
590 }
591 else if ((opcode & UCOND_DBR_MASK) == BRA_INSTR)
592 {
593 displacement = (opcode & UCOND_DISP) << 1;
594 if (displacement & 0x0800)
595 displacement |= 0xfffff000;
596
597 /*
598 * Remember PC points to second instr.
599 * after PC of branch ... so add 4
600 */
601 instrMem = (short *) (registers[PC] + displacement + 4);
602 }
603 else if ((opcode & UCOND_RBR_MASK) == JSR_INSTR)
604 {
605 reg = (char) ((opcode & UCOND_REG) >> 8);
606
607 instrMem = (short *) registers[reg];
608 }
609 else if (opcode == RTS_INSTR)
610 instrMem = (short *) registers[PR];
611 else if (opcode == RTE_INSTR)
612 instrMem = (short *) registers[15];
613 else if ((opcode & TRAPA_MASK) == TRAPA_INSTR)
614 instrMem = (short *) ((opcode & ~TRAPA_MASK) << 2);
615 else
616 instrMem += 1;
617
618 instrBuffer.memAddr = instrMem;
619 instrBuffer.oldInstr = *instrMem;
620 *instrMem = SSTEP_INSTR;
621}
622
623
624/* Undo the effect of a previous doSStep. If we single stepped,
625 restore the old instruction. */
626
627void
628undoSStep (void)
629{
630 if (stepped)
631 { short *instrMem;
632 instrMem = instrBuffer.memAddr;
633 *instrMem = instrBuffer.oldInstr;
634 }
635 stepped = 0;
636}
637
638/*
639This function does all exception handling. It only does two things -
640it figures out why it was called and tells gdb, and then it reacts
641to gdb's requests.
642
643When in the monitor mode we talk a human on the serial line rather than gdb.
644
645*/
646
647
648void
649gdb_handle_exception (int exceptionVector)
650{
651 int sigval;
652 int addr, length;
653 char *ptr;
654
655 /* reply to host that an exception has occurred */
656 sigval = computeSignal (exceptionVector);
657 remcomOutBuffer[0] = 'S';
658 remcomOutBuffer[1] = highhex(sigval);
659 remcomOutBuffer[2] = lowhex (sigval);
660 remcomOutBuffer[3] = 0;
661
662 putpacket (remcomOutBuffer);
663
664 /*
665 * exception 255 indicates a software trap
666 * inserted in place of code ... so back up
667 * PC by one instruction, since this instruction
668 * will later be replaced by its original one!
669 */
670 if (exceptionVector == 0xff
671 || exceptionVector == 0x20)
672 registers[PC] -= 2;
673
674 /*
675 * Do the thangs needed to undo
676 * any stepping we may have done!
677 */
678 undoSStep ();
679
680 while (1)
681 {
682 remcomOutBuffer[0] = 0;
683 getpacket (remcomInBuffer);
684
685 switch (remcomInBuffer[0])
686 {
687 case '?':
688 remcomOutBuffer[0] = 'S';
689 remcomOutBuffer[1] = highhex (sigval);
690 remcomOutBuffer[2] = lowhex (sigval);
691 remcomOutBuffer[3] = 0;
692 break;
693 case 'd':
694 remote_debug = !(remote_debug); /* toggle debug flag */
695 break;
696 case 'g': /* return the value of the CPU registers */
697 mem2hex ((char *) registers, remcomOutBuffer, NUMREGBYTES);
698 break;
699 case 'G': /* set the value of the CPU registers - return OK */
700 hex2mem (&remcomInBuffer[1], (char *) registers, NUMREGBYTES);
701 strcpy (remcomOutBuffer, "OK");
702 break;
703
704 /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
705 case 'm':
706 if (setjmp (remcomEnv) == 0)
707 {
708 dofault = 0;
709 /* TRY, TO READ %x,%x. IF SUCCEED, SET PTR = 0 */
710 ptr = &remcomInBuffer[1];
711 if (hexToInt (&ptr, &addr))
712 if (*(ptr++) == ',')
713 if (hexToInt (&ptr, &length))
714 {
715 ptr = 0;
716 mem2hex ((char *) addr, remcomOutBuffer, length);
717 }
718 if (ptr)
719 strcpy (remcomOutBuffer, "E01");
720 }
721 else
722 strcpy (remcomOutBuffer, "E03");
723
724 /* restore handler for bus error */
725 dofault = 1;
726 break;
727
728 /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
729 case 'M':
730 if (setjmp (remcomEnv) == 0)
731 {
732 dofault = 0;
733
734 /* TRY, TO READ '%x,%x:'. IF SUCCEED, SET PTR = 0 */
735 ptr = &remcomInBuffer[1];
736 if (hexToInt (&ptr, &addr))
737 if (*(ptr++) == ',')
738 if (hexToInt (&ptr, &length))
739 if (*(ptr++) == ':')
740 {
741 hex2mem (ptr, (char *) addr, length);
742 ptr = 0;
743 strcpy (remcomOutBuffer, "OK");
744 }
745 if (ptr)
746 strcpy (remcomOutBuffer, "E02");
747 }
748 else
749 strcpy (remcomOutBuffer, "E03");
750
751 /* restore handler for bus error */
752 dofault = 1;
753 break;
754
755 /* cAA..AA Continue at address AA..AA(optional) */
756 /* sAA..AA Step one instruction from AA..AA(optional) */
757 case 'c':
758 case 's':
759 {
760 /* tRY, to read optional parameter, pc unchanged if no parm */
761 ptr = &remcomInBuffer[1];
762 if (hexToInt (&ptr, &addr))
763 registers[PC] = addr;
764
765 if (remcomInBuffer[0] == 's')
766 doSStep ();
767 }
768 return;
769 break;
770
771 /* kill the program */
772 case 'k': /* do nothing */
773 break;
774 } /* switch */
775
776 /* reply to the request */
777 putpacket (remcomOutBuffer);
778 }
779}
780
781
782#define GDBCOOKIE 0x5ac
783static int ingdbmode;
784/* We've had an exception - choose to go into the monitor or
785 the gdb stub */
786void handle_exception(int exceptionVector)
787{
788#ifdef MONITOR
789 if (ingdbmode != GDBCOOKIE)
790 monitor_handle_exception (exceptionVector);
791 else
792#endif
793 gdb_handle_exception (exceptionVector);
794
795}
796
797void
798gdb_mode()
799{
800 ingdbmode = GDBCOOKIE;
801 breakpoint();
802}
803/* This function will generate a breakpoint exception. It is used at the
804 beginning of a program to sync up with a debugger and can be used
805 otherwise as a quick means to stop program execution and "break" into
806 the debugger. */
807
9e086581
JM		 808void
809breakpoint (void)
810{
811 BREAKPOINT ();
812}
813
814/**** Processor-specific routines start here ****/
815/**** Processor-specific routines start here ****/
816/**** Processor-specific routines start here ****/
817
818/* Note:
819
820 The Hitachi SH family uses two exception architectures:
821
822 SH1 & SH2:
823
824 These processors utilize an exception vector table.
825 Exceptions are vectored to the address stored at VBR + (exception_num * 4)
826
827 SH3, SH3E, & SH4:
828
829 These processors have fixed entry points relative to the VBR for
830 various exception classes.
831*/
832
833#if defined(__sh1__) || defined(__sh2__)
834
835/* SH1/SH2 exception vector table format */
836
837typedef struct
838 {
839 void (*func_cold) ();
840 int *stack_cold;
841 void (*func_warm) ();
842 int *stack_warm;
843 void (*(handler[256 - 4])) ();
844 }
845vec_type;
846
847/* vectable is the SH1/SH2 vector table. It must be at address 0
848 or wherever your vbr points. */
849
850const vec_type vectable =
851{
852 &BINIT, /* 0: Power-on reset PC */
853 init_stack + init_stack_size, /* 1: Power-on reset SP */
854 &BINIT, /* 2: Manual reset PC */
855 init_stack + init_stack_size, /* 3: Manual reset SP */
856{
857 &catch_exception_4, /* 4: General invalid instruction */
858 &catch_exception_random, /* 5: Reserved for system */
859 &catch_exception_6, /* 6: Invalid slot instruction */
860 &catch_exception_random, /* 7: Reserved for system */
861 &catch_exception_random, /* 8: Reserved for system */
862 &catch_exception_9, /* 9: CPU bus error */
863 &catch_exception_10, /* 10: DMA bus error */
864 &catch_exception_11, /* 11: NMI */
865 &catch_exception_random, /* 12: User break */
866 &catch_exception_random, /* 13: Reserved for system */
867 &catch_exception_random, /* 14: Reserved for system */
868 &catch_exception_random, /* 15: Reserved for system */
869 &catch_exception_random, /* 16: Reserved for system */
870 &catch_exception_random, /* 17: Reserved for system */
871 &catch_exception_random, /* 18: Reserved for system */
872 &catch_exception_random, /* 19: Reserved for system */
873 &catch_exception_random, /* 20: Reserved for system */
874 &catch_exception_random, /* 21: Reserved for system */
875 &catch_exception_random, /* 22: Reserved for system */
876 &catch_exception_random, /* 23: Reserved for system */
877 &catch_exception_random, /* 24: Reserved for system */
878 &catch_exception_random, /* 25: Reserved for system */
879 &catch_exception_random, /* 26: Reserved for system */
880 &catch_exception_random, /* 27: Reserved for system */
881 &catch_exception_random, /* 28: Reserved for system */
882 &catch_exception_random, /* 29: Reserved for system */
883 &catch_exception_random, /* 30: Reserved for system */
884 &catch_exception_random, /* 31: Reserved for system */
885 &catch_exception_32, /* 32: Trap instr (user vectors) */
886 &catch_exception_33, /* 33: Trap instr (user vectors) */
887 &catch_exception_random, /* 34: Trap instr (user vectors) */
888 &catch_exception_random, /* 35: Trap instr (user vectors) */
889 &catch_exception_random, /* 36: Trap instr (user vectors) */
890 &catch_exception_random, /* 37: Trap instr (user vectors) */
891 &catch_exception_random, /* 38: Trap instr (user vectors) */
892 &catch_exception_random, /* 39: Trap instr (user vectors) */
893 &catch_exception_random, /* 40: Trap instr (user vectors) */
894 &catch_exception_random, /* 41: Trap instr (user vectors) */
895 &catch_exception_random, /* 42: Trap instr (user vectors) */
896 &catch_exception_random, /* 43: Trap instr (user vectors) */
897 &catch_exception_random, /* 44: Trap instr (user vectors) */
898 &catch_exception_random, /* 45: Trap instr (user vectors) */
899 &catch_exception_random, /* 46: Trap instr (user vectors) */
900 &catch_exception_random, /* 47: Trap instr (user vectors) */
901 &catch_exception_random, /* 48: Trap instr (user vectors) */
902 &catch_exception_random, /* 49: Trap instr (user vectors) */
903 &catch_exception_random, /* 50: Trap instr (user vectors) */
904 &catch_exception_random, /* 51: Trap instr (user vectors) */
905 &catch_exception_random, /* 52: Trap instr (user vectors) */
906 &catch_exception_random, /* 53: Trap instr (user vectors) */
907 &catch_exception_random, /* 54: Trap instr (user vectors) */
908 &catch_exception_random, /* 55: Trap instr (user vectors) */
909 &catch_exception_random, /* 56: Trap instr (user vectors) */
910 &catch_exception_random, /* 57: Trap instr (user vectors) */
911 &catch_exception_random, /* 58: Trap instr (user vectors) */
912 &catch_exception_random, /* 59: Trap instr (user vectors) */
913 &catch_exception_random, /* 60: Trap instr (user vectors) */
914 &catch_exception_random, /* 61: Trap instr (user vectors) */
915 &catch_exception_random, /* 62: Trap instr (user vectors) */
916 &catch_exception_random, /* 63: Trap instr (user vectors) */
917 &catch_exception_random, /* 64: IRQ0 */
918 &catch_exception_random, /* 65: IRQ1 */
919 &catch_exception_random, /* 66: IRQ2 */
920 &catch_exception_random, /* 67: IRQ3 */
921 &catch_exception_random, /* 68: IRQ4 */
922 &catch_exception_random, /* 69: IRQ5 */
923 &catch_exception_random, /* 70: IRQ6 */
924 &catch_exception_random, /* 71: IRQ7 */
925 &catch_exception_random,
926 &catch_exception_random,
927 &catch_exception_random,
928 &catch_exception_random,
929 &catch_exception_random,
930 &catch_exception_random,
931 &catch_exception_random,
932 &catch_exception_random,
933 &catch_exception_random,
934 &catch_exception_random,
935 &catch_exception_random,
936 &catch_exception_random,
937 &catch_exception_random,
938 &catch_exception_random,
939 &catch_exception_random,
940 &catch_exception_random,
941 &catch_exception_random,
942 &catch_exception_random,
943 &catch_exception_random,
944 &catch_exception_random,
945 &catch_exception_random,
946 &catch_exception_random,
947 &catch_exception_random,
948 &catch_exception_random,
949 &catch_exception_random,
950 &catch_exception_random,
951 &catch_exception_random,
952 &catch_exception_random,
953 &catch_exception_random,
954 &catch_exception_random,
955 &catch_exception_random,
956 &catch_exception_random,
957 &catch_exception_random,
958 &catch_exception_random,
959 &catch_exception_random,
960 &catch_exception_random,
961 &catch_exception_random,
962 &catch_exception_random,
963 &catch_exception_random,
964 &catch_exception_random,
965 &catch_exception_random,
966 &catch_exception_random,
967 &catch_exception_random,
968 &catch_exception_random,
969 &catch_exception_random,
970 &catch_exception_random,
971 &catch_exception_random,
972 &catch_exception_random,
973 &catch_exception_random,
974 &catch_exception_random,
975 &catch_exception_random,
976 &catch_exception_random,
977 &catch_exception_random,
978 &catch_exception_random,
979 &catch_exception_random,
980 &catch_exception_random,
981 &catch_exception_random,
982 &catch_exception_random,
983 &catch_exception_random,
984 &catch_exception_random,
985 &catch_exception_random,
986 &catch_exception_random,
987 &catch_exception_random,
988 &catch_exception_random,
989 &catch_exception_random,
990 &catch_exception_random,
991 &catch_exception_random,
992 &catch_exception_random,
993 &catch_exception_random,
994 &catch_exception_random,
995 &catch_exception_random,
996 &catch_exception_random,
997 &catch_exception_random,
998 &catch_exception_random,
999 &catch_exception_random,
1000 &catch_exception_random,
1001 &catch_exception_random,
1002 &catch_exception_random,
1003 &catch_exception_random,
1004 &catch_exception_random,
1005 &catch_exception_random,
1006 &catch_exception_random,
1007 &catch_exception_random,
1008 &catch_exception_random,
1009 &catch_exception_random,
1010 &catch_exception_random,
1011 &catch_exception_random,
1012 &catch_exception_random,
1013 &catch_exception_random,
1014 &catch_exception_random,
1015 &catch_exception_random,
1016 &catch_exception_random,
1017 &catch_exception_random,
1018 &catch_exception_random,
1019 &catch_exception_random,
1020 &catch_exception_random,
1021 &catch_exception_random,
1022 &catch_exception_random,
1023 &catch_exception_random,
1024 &catch_exception_random,
1025 &catch_exception_random,
1026 &catch_exception_random,
1027 &catch_exception_random,
1028 &catch_exception_random,
1029 &catch_exception_random,
1030 &catch_exception_random,
1031 &catch_exception_random,
1032 &catch_exception_random,
1033 &catch_exception_random,
1034 &catch_exception_random,
1035 &catch_exception_random,
1036 &catch_exception_random,
1037 &catch_exception_random,
1038 &catch_exception_random,
1039 &catch_exception_random,
1040 &catch_exception_random,
1041 &catch_exception_random,
1042 &catch_exception_random,
1043 &catch_exception_random,
1044 &catch_exception_random,
1045 &catch_exception_random,
1046 &catch_exception_random,
1047 &catch_exception_random,
1048 &catch_exception_random,
1049 &catch_exception_random,
1050 &catch_exception_random,
1051 &catch_exception_random,
1052 &catch_exception_random,
1053 &catch_exception_random,
1054 &catch_exception_random,
1055 &catch_exception_random,
1056 &catch_exception_random,
1057 &catch_exception_random,
1058 &catch_exception_random,
1059 &catch_exception_random,
1060 &catch_exception_random,
1061 &catch_exception_random,
1062 &catch_exception_random,
1063 &catch_exception_random,
1064 &catch_exception_random,
1065 &catch_exception_random,
1066 &catch_exception_random,
1067 &catch_exception_random,
1068 &catch_exception_random,
1069 &catch_exception_random,
1070 &catch_exception_random,
1071 &catch_exception_random,
1072 &catch_exception_random,
1073 &catch_exception_random,
1074 &catch_exception_random,
1075 &catch_exception_random,
1076 &catch_exception_random,
1077 &catch_exception_random,
1078 &catch_exception_random,
1079 &catch_exception_random,
1080 &catch_exception_random,
1081 &catch_exception_random,
1082 &catch_exception_random,
1083 &catch_exception_random,
1084 &catch_exception_random,
1085 &catch_exception_random,
1086 &catch_exception_random,
1087 &catch_exception_random,
1088 &catch_exception_random,
1089 &catch_exception_random,
1090 &catch_exception_random,
1091 &catch_exception_random,
1092 &catch_exception_random,
1093 &catch_exception_random,
1094 &catch_exception_random,
1095 &catch_exception_random,
1096 &catch_exception_random,
1097 &catch_exception_random,
1098 &catch_exception_random,
1099 &catch_exception_random,
1100 &catch_exception_random,
1101 &catch_exception_random,
1102 &catch_exception_random,
1103 &catch_exception_random,
1104 &catch_exception_random,
1105 &catch_exception_random,
1106 &catch_exception_random,
1107 &catch_exception_random,
1108 &catch_exception_255}};
1109
1110#define BCR (*(volatile short *)(0x05FFFFA0)) /* Bus control register */
1111#define BAS (0x800) /* Byte access select */
1112#define WCR1 (*(volatile short *)(0x05ffffA2)) /* Wait state control register */
c906108c
SS		 1113
1114asm ("_BINIT: mov.l L1,r15");
1115asm ("bra _INIT");
1116asm ("nop");
1117asm ("L1: .long _init_stack + 8*1024*4");
1118void
1119INIT (void)
1120{
1121 /* First turn on the ram */
1122 WCR1 = 0; /* Never sample wait */
1123 BCR = BAS; /* use lowbyte/high byte */
1124
1125 init_serial();
1126
1127#ifdef MONITOR
1128 reset_hook ();
1129#endif
1130
1131
1132 in_nmi = 0;
1133 dofault = 1;
1134 stepped = 0;
1135
1136 stub_sp = stub_stack + stub_stack_size;
1137 breakpoint ();
1138
1139 while (1)
1140 ;
1141}
1142
1143
1144static void sr()
1145{
1146
1147
1148 /* Calling Reset does the same as pressing the button */
1149 asm (".global _Reset
1150 .global _WarmReset
1151_Reset:
1152_WarmReset:
1153 mov.l L_sp,r15
1154 bra _INIT
1155 nop
1156 .align 2
1157L_sp: .long _init_stack + 8000");
1158
1159 asm("saveRegisters:
1160 mov.l @(L_reg, pc), r0
1161 mov.l @r15+, r1 ! pop R0
1162 mov.l r2, @(0x08, r0) ! save R2
1163 mov.l r1, @r0 ! save R0
1164 mov.l @r15+, r1 ! pop R1
1165 mov.l r3, @(0x0c, r0) ! save R3
1166 mov.l r1, @(0x04, r0) ! save R1
1167 mov.l r4, @(0x10, r0) ! save R4
1168 mov.l r5, @(0x14, r0) ! save R5
1169 mov.l r6, @(0x18, r0) ! save R6
1170 mov.l r7, @(0x1c, r0) ! save R7
1171 mov.l r8, @(0x20, r0) ! save R8
1172 mov.l r9, @(0x24, r0) ! save R9
1173 mov.l r10, @(0x28, r0) ! save R10
1174 mov.l r11, @(0x2c, r0) ! save R11
1175 mov.l r12, @(0x30, r0) ! save R12
1176 mov.l r13, @(0x34, r0) ! save R13
1177 mov.l r14, @(0x38, r0) ! save R14
1178 mov.l @r15+, r4 ! save arg to handleException
1179 add #8, r15 ! hide PC/SR values on stack
1180 mov.l r15, @(0x3c, r0) ! save R15
1181 add #-8, r15 ! save still needs old SP value
1182 add #92, r0 ! readjust register pointer
1183 mov r15, r2
1184 add #4, r2
1185 mov.l @r2, r2 ! R2 has SR
1186 mov.l @r15, r1 ! R1 has PC
1187 mov.l r2, @-r0 ! save SR
1188 sts.l macl, @-r0 ! save MACL
1189 sts.l mach, @-r0 ! save MACH
1190 stc.l vbr, @-r0 ! save VBR
1191 stc.l gbr, @-r0 ! save GBR
1192 sts.l pr, @-r0 ! save PR
1193 mov.l @(L_stubstack, pc), r2
1194 mov.l @(L_hdl_except, pc), r3
1195 mov.l @r2, r15
1196 jsr @r3
1197 mov.l r1, @-r0 ! save PC
1198 mov.l @(L_stubstack, pc), r0
1199 mov.l @(L_reg, pc), r1
1200 bra restoreRegisters
1201 mov.l r15, @r0 ! save __stub_stack
1202
1203 .align 2
1204L_reg:
1205 .long _registers
1206L_stubstack:
1207 .long _stub_sp
1208L_hdl_except:
1209 .long _handle_exception");
1210
1211}
1212
1213static void rr()
1214{
1215asm("
1216 .align 2
1217 .global _resume
1218_resume:
1219 mov r4,r1
1220restoreRegisters:
1221 add #8, r1 ! skip to R2
1222 mov.l @r1+, r2 ! restore R2
1223 mov.l @r1+, r3 ! restore R3
1224 mov.l @r1+, r4 ! restore R4
1225 mov.l @r1+, r5 ! restore R5
1226 mov.l @r1+, r6 ! restore R6
1227 mov.l @r1+, r7 ! restore R7
1228 mov.l @r1+, r8 ! restore R8
1229 mov.l @r1+, r9 ! restore R9
1230 mov.l @r1+, r10 ! restore R10
1231 mov.l @r1+, r11 ! restore R11
1232 mov.l @r1+, r12 ! restore R12
1233 mov.l @r1+, r13 ! restore R13
1234 mov.l @r1+, r14 ! restore R14
1235 mov.l @r1+, r15 ! restore programs stack
1236 mov.l @r1+, r0
1237 add #-8, r15 ! uncover PC/SR on stack
1238 mov.l r0, @r15 ! restore PC onto stack
1239 lds.l @r1+, pr ! restore PR
1240 ldc.l @r1+, gbr ! restore GBR
1241 ldc.l @r1+, vbr ! restore VBR
1242 lds.l @r1+, mach ! restore MACH
1243 lds.l @r1+, macl ! restore MACL
1244 mov.l @r1, r0
1245 add #-88, r1 ! readjust reg pointer to R1
1246 mov.l r0, @(4, r15) ! restore SR onto stack+4
1247 mov.l r2, @-r15
1248 mov.l L_in_nmi, r0
1249 mov #0, r2
1250 mov.b r2, @r0
1251 mov.l @r15+, r2
1252 mov.l @r1+, r0 ! restore R0
1253 rte
1254 mov.l @r1, r1 ! restore R1
1255
1256");
1257}
1258
1259
1260static __inline__ void code_for_catch_exception(int n)
1261{
1262 asm(" .globl _catch_exception_%O0" : : "i" (n) );
1263 asm(" _catch_exception_%O0:" :: "i" (n) );
1264
1265 asm(" add #-4, r15 ! reserve spot on stack ");
1266 asm(" mov.l r1, @-r15 ! push R1 ");
1267
1268 if (n == NMI_VEC)
1269 {
1270 /* Special case for NMI - make sure that they don't nest */
1271 asm(" mov.l r0, @-r15 ! push R0");
1272 asm(" mov.l L_in_nmi, r0");
1273 asm(" tas.b @r0 ! Fend off against addtnl NMIs");
1274 asm(" bt noNMI");
1275 asm(" mov.l @r15+, r0");
1276 asm(" mov.l @r15+, r1");
1277 asm(" add #4, r15");
1278 asm(" rte");
1279 asm(" nop");
1280 asm(".align 2");
1281 asm("L_in_nmi: .long _in_nmi");
1282 asm("noNMI:");
1283 }
1284 else
1285 {
1286
1287 if (n == CPU_BUS_ERROR_VEC)
1288 {
1289 /* Exception 9 (bus errors) are disasbleable - so that you
1290 can probe memory and get zero instead of a fault.
1291 Because the vector table may be in ROM we don't revector
1292 the interrupt like all the other stubs, we check in here
1293 */
1294 asm("mov.l L_dofault,r1");
1295 asm("mov.l @r1,r1");
1296 asm("tst r1,r1");
1297 asm("bf faultaway");
1298 asm("bsr _handle_buserror");
1299 asm(".align 2");
1300 asm("L_dofault: .long _dofault");
1301 asm("faultaway:");
1302 }
1303 asm(" mov #15<<4, r1 ");
1304 asm(" ldc r1, sr ! disable interrupts ");
1305 asm(" mov.l r0, @-r15 ! push R0 ");
1306 }
1307
1308 /* Prepare for saving context, we've already pushed r0 and r1, stick exception number
1309 into the frame */
1310 asm(" mov r15, r0 ");
1311 asm(" add #8, r0 ");
1312 asm(" mov %0,r1" :: "i" (n) );
1313 asm(" extu.b r1,r1 ");
1314 asm(" bra saveRegisters ! save register values ");
1315 asm(" mov.l r1, @r0 ! save exception # ");
1316}
1317
1318
1319static void
1320exceptions()
1321{
1322 code_for_catch_exception (CPU_BUS_ERROR_VEC);
1323 code_for_catch_exception (DMA_BUS_ERROR_VEC);
1324 code_for_catch_exception (INVALID_INSN_VEC);
1325 code_for_catch_exception (INVALID_SLOT_VEC);
1326 code_for_catch_exception (NMI_VEC);
1327 code_for_catch_exception (TRAP_VEC);
1328 code_for_catch_exception (USER_VEC);
1329 code_for_catch_exception (IO_VEC);
1330}
1331
1332
1333
1334
1335
1336
1337/* Support for Serial I/O using on chip uart */
1338
1339#define SMR0 (*(volatile char *)(0x05FFFEC0)) /* Channel 0 serial mode register */
1340#define BRR0 (*(volatile char *)(0x05FFFEC1)) /* Channel 0 bit rate register */
1341#define SCR0 (*(volatile char *)(0x05FFFEC2)) /* Channel 0 serial control register */
1342#define TDR0 (*(volatile char *)(0x05FFFEC3)) /* Channel 0 transmit data register */
1343#define SSR0 (*(volatile char *)(0x05FFFEC4)) /* Channel 0 serial status register */
1344#define RDR0 (*(volatile char *)(0x05FFFEC5)) /* Channel 0 receive data register */
1345
1346#define SMR1 (*(volatile char *)(0x05FFFEC8)) /* Channel 1 serial mode register */
1347#define BRR1 (*(volatile char *)(0x05FFFEC9)) /* Channel 1 bit rate register */
1348#define SCR1 (*(volatile char *)(0x05FFFECA)) /* Channel 1 serial control register */
1349#define TDR1 (*(volatile char *)(0x05FFFECB)) /* Channel 1 transmit data register */
1350#define SSR1 (*(volatile char *)(0x05FFFECC)) /* Channel 1 serial status register */
1351#define RDR1 (*(volatile char *)(0x05FFFECD)) /* Channel 1 receive data register */
1352
1353/*
1354 * Serial mode register bits
1355 */
1356
1357#define SYNC_MODE 0x80
1358#define SEVEN_BIT_DATA 0x40
1359#define PARITY_ON 0x20
1360#define ODD_PARITY 0x10
1361#define STOP_BITS_2 0x08
1362#define ENABLE_MULTIP 0x04
1363#define PHI_64 0x03
1364#define PHI_16 0x02
1365#define PHI_4 0x01
1366
1367/*
1368 * Serial control register bits
1369 */
1370#define SCI_TIE 0x80 /* Transmit interrupt enable */
1371#define SCI_RIE 0x40 /* Receive interrupt enable */
1372#define SCI_TE 0x20 /* Transmit enable */
1373#define SCI_RE 0x10 /* Receive enable */
1374#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
1375#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
1376#define SCI_CKE1 0x02 /* Clock enable 1 */
1377#define SCI_CKE0 0x01 /* Clock enable 0 */
1378
1379/*
1380 * Serial status register bits
1381 */
1382#define SCI_TDRE 0x80 /* Transmit data register empty */
1383#define SCI_RDRF 0x40 /* Receive data register full */
1384#define SCI_ORER 0x20 /* Overrun error */
1385#define SCI_FER 0x10 /* Framing error */
1386#define SCI_PER 0x08 /* Parity error */
1387#define SCI_TEND 0x04 /* Transmit end */
1388#define SCI_MPB 0x02 /* Multiprocessor bit */
1389#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
1390
1391
1392/*
1393 * Port B IO Register (PBIOR)
1394 */
1395#define PBIOR (*(volatile char *)(0x05FFFFC6))
1396#define PB15IOR 0x8000
1397#define PB14IOR 0x4000
1398#define PB13IOR 0x2000
1399#define PB12IOR 0x1000
1400#define PB11IOR 0x0800
1401#define PB10IOR 0x0400
1402#define PB9IOR 0x0200
1403#define PB8IOR 0x0100
1404#define PB7IOR 0x0080
1405#define PB6IOR 0x0040
1406#define PB5IOR 0x0020
1407#define PB4IOR 0x0010
1408#define PB3IOR 0x0008
1409#define PB2IOR 0x0004
1410#define PB1IOR 0x0002
1411#define PB0IOR 0x0001
1412
1413/*
1414 * Port B Control Register (PBCR1)
1415 */
1416#define PBCR1 (*(volatile short *)(0x05FFFFCC))
1417#define PB15MD1 0x8000
1418#define PB15MD0 0x4000
1419#define PB14MD1 0x2000
1420#define PB14MD0 0x1000
1421#define PB13MD1 0x0800
1422#define PB13MD0 0x0400
1423#define PB12MD1 0x0200
1424#define PB12MD0 0x0100
1425#define PB11MD1 0x0080
1426#define PB11MD0 0x0040
1427#define PB10MD1 0x0020
1428#define PB10MD0 0x0010
1429#define PB9MD1 0x0008
1430#define PB9MD0 0x0004
1431#define PB8MD1 0x0002
1432#define PB8MD0 0x0001
1433
1434#define PB15MD PB15MD1|PB14MD0
1435#define PB14MD PB14MD1|PB14MD0
1436#define PB13MD PB13MD1|PB13MD0
1437#define PB12MD PB12MD1|PB12MD0
1438#define PB11MD PB11MD1|PB11MD0
1439#define PB10MD PB10MD1|PB10MD0
1440#define PB9MD PB9MD1|PB9MD0
1441#define PB8MD PB8MD1|PB8MD0
1442
1443#define PB_TXD1 PB11MD1
1444#define PB_RXD1 PB10MD1
1445#define PB_TXD0 PB9MD1
1446#define PB_RXD0 PB8MD1
1447
1448/*
1449 * Port B Control Register (PBCR2)
1450 */
1451#define PBCR2 0x05FFFFCE
1452#define PB7MD1 0x8000
1453#define PB7MD0 0x4000
1454#define PB6MD1 0x2000
1455#define PB6MD0 0x1000
1456#define PB5MD1 0x0800
1457#define PB5MD0 0x0400
1458#define PB4MD1 0x0200
1459#define PB4MD0 0x0100
1460#define PB3MD1 0x0080
1461#define PB3MD0 0x0040
1462#define PB2MD1 0x0020
1463#define PB2MD0 0x0010
1464#define PB1MD1 0x0008
1465#define PB1MD0 0x0004
1466#define PB0MD1 0x0002
1467#define PB0MD0 0x0001
1468
1469#define PB7MD PB7MD1|PB7MD0
1470#define PB6MD PB6MD1|PB6MD0
1471#define PB5MD PB5MD1|PB5MD0
1472#define PB4MD PB4MD1|PB4MD0
1473#define PB3MD PB3MD1|PB3MD0
1474#define PB2MD PB2MD1|PB2MD0
1475#define PB1MD PB1MD1|PB1MD0
1476#define PB0MD PB0MD1|PB0MD0
1477
1478
1479#ifdef MHZ
1480#define BPS 32 * 9600 * MHZ / ( BAUD * 10)
1481#else
1482#define BPS 32 /* 9600 for 10 Mhz */
1483#endif
1484
1485void handleError (char theSSR);
1486
1487void
1488nop ()
1489{
1490
1491}
1492void
1493init_serial()
1494{
1495 int i;
1496
1497 /* Clear TE and RE in Channel 1's SCR */
1498 SCR1 &= ~(SCI_TE | SCI_RE);
1499
1500 /* Set communication to be async, 8-bit data, no parity, 1 stop bit and use internal clock */
1501
1502 SMR1 = 0;
1503 BRR1 = BPS;
1504
1505 SCR1 &= ~(SCI_CKE1 | SCI_CKE0);
1506
1507 /* let the hardware settle */
1508
1509 for (i = 0; i < 1000; i++)
1510 nop ();
1511
1512 /* Turn on in and out */
1513 SCR1 |= SCI_RE | SCI_TE;
1514
1515 /* Set the PFC to make RXD1 (pin PB8) an input pin and TXD1 (pin PB9) an output pin */
1516 PBCR1 &= ~(PB_TXD1 | PB_RXD1);
1517 PBCR1 |= PB_TXD1 | PB_RXD1;
1518}
1519
1520
1521int
1522getDebugCharReady (void)
1523{
1524 char mySSR;
1525 mySSR = SSR1 & ( SCI_PER | SCI_FER | SCI_ORER );
1526 if ( mySSR )
1527 handleError ( mySSR );
1528 return SSR1 & SCI_RDRF ;
1529}
1530
1531char
1532getDebugChar (void)
1533{
1534 char ch;
1535 char mySSR;
1536
1537 while ( ! getDebugCharReady())
1538 ;
1539
1540 ch = RDR1;
1541 SSR1 &= ~SCI_RDRF;
1542
1543 mySSR = SSR1 & (SCI_PER | SCI_FER | SCI_ORER);
1544
1545 if (mySSR)
1546 handleError (mySSR);
1547
1548 return ch;
1549}
1550
1551int
1552putDebugCharReady()
1553{
1554 return (SSR1 & SCI_TDRE);
1555}
1556
1557void
1558putDebugChar (char ch)
1559{
1560 while (!putDebugCharReady())
1561 ;
1562
1563 /*
1564 * Write data into TDR and clear TDRE
1565 */
1566 TDR1 = ch;
1567 SSR1 &= ~SCI_TDRE;
1568}
1569
1570void
1571handleError (char theSSR)
1572{
1573 SSR1 &= ~(SCI_ORER | SCI_PER | SCI_FER);
1574}
1575
9e086581 1576#endif
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