[binutils.git] / gdb / config / mips / tm-mips.h

/* Definitions to make GDB run on a mips box under 4.3bsd.
   Copyright 1986, 1987, 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
   Contributed by Per Bothner ([email protected]) at U.Wisconsin
   and by Alessandro Forin ([email protected]) at CMU..

This file is part of GDB.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */

#include <bfd.h>
#include "coff/sym.h"		/* Needed for PDR below.  */
#include "coff/symconst.h"

#if !defined (TARGET_BYTE_ORDER)
#define TARGET_BYTE_ORDER LITTLE_ENDIAN
#endif

#if !defined (GDB_TARGET_IS_MIPS64)
#define GDB_TARGET_IS_MIPS64 0
#endif

/* Floating point is IEEE compliant */
#define IEEE_FLOAT

extern int mips_processor_id;

/* Some MIPS boards are provided both with and without a floating
   point coprocessor; we provide a user settable variable to tell gdb
   whether there is one or not.  */
extern int mips_fpu;

/* Offset from address of function to start of its code.
   Zero on most machines.  */

#define FUNCTION_START_OFFSET 0

/* Advance PC across any function entry prologue instructions
   to reach some "real" code.  */

#define SKIP_PROLOGUE(pc)	pc = mips_skip_prologue (pc, 0)
extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));

/* Return non-zero if PC points to an instruction which will cause a step
   to execute both the instruction at PC and an instruction at PC+4.  */
#define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))

/* Immediately after a function call, return the saved pc.
   Can't always go through the frames for this because on some machines
   the new frame is not set up until the new function executes
   some instructions.  */

#define SAVED_PC_AFTER_CALL(frame)	read_register(RA_REGNUM)

/* Are we currently handling a signal */

extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
#define IN_SIGTRAMP(pc, name)	in_sigtramp(pc, name)

/* Stack grows downward.  */

#define INNER_THAN <

#define BIG_ENDIAN 4321
#if TARGET_BYTE_ORDER == BIG_ENDIAN
#define BREAKPOINT {0, 0x5, 0, 0xd}
#else
#define BREAKPOINT {0xd, 0, 0x5, 0}
#endif

/* Amount PC must be decremented by after a breakpoint.
   This is often the number of bytes in BREAKPOINT
   but not always.  */

#define DECR_PC_AFTER_BREAK 0

/* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */

#define ABOUT_TO_RETURN(pc) (read_memory_integer (pc, 4) == 0x3e00008)

/* Say how long (ordinary) registers are.  This is a piece of bogosity
   used in push_word and a few other places; REGISTER_RAW_SIZE is the
   real way to know how big a register is.  */

#define REGISTER_SIZE 4

/* The size of a register.  This is predefined in tm-mips64.h.  We
   can't use REGISTER_SIZE because that is used for various other
   things.  */

#ifndef MIPS_REGSIZE
#define MIPS_REGSIZE 4
#endif

/* Number of machine registers */

#define NUM_REGS 80

/* Initializer for an array of names of registers.
   There should be NUM_REGS strings in this initializer.  */

#define REGISTER_NAMES 	\
    {	"zero",	"at",	"v0",	"v1",	"a0",	"a1",	"a2",	"a3", \
	"t0",	"t1",	"t2",	"t3",	"t4",	"t5",	"t6",	"t7", \
	"s0",	"s1",	"s2",	"s3",	"s4",	"s5",	"s6",	"s7", \
	"t8",	"t9",	"k0",	"k1",	"gp",	"sp",	"s8",	"ra", \
	"sr",	"lo",	"hi",	"bad",	"cause","pc",    \
	"f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
	"f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
	"f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
	"f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
	"fsr",  "fir",  "fp",   "inx",  "rand", "tlblo","ctxt", "tlbhi",\
	"epc",  "prid"\
    }

/* Register numbers of various important registers.
   Note that some of these values are "real" register numbers,
   and correspond to the general registers of the machine,
   and some are "phony" register numbers which are too large
   to be actual register numbers as far as the user is concerned
   but do serve to get the desired values when passed to read_register.  */

#define ZERO_REGNUM 0		/* read-only register, always 0 */
#define V0_REGNUM 2		/* Function integer return value */
#define A0_REGNUM 4		/* Loc of first arg during a subr call */
#define SP_REGNUM 29		/* Contains address of top of stack */
#define RA_REGNUM 31		/* Contains return address value */
#define PS_REGNUM 32		/* Contains processor status */
#define HI_REGNUM 34            /* Multiple/divide temp */
#define LO_REGNUM 33            /* ... */
#define BADVADDR_REGNUM 35	/* bad vaddr for addressing exception */
#define CAUSE_REGNUM 36		/* describes last exception */
#define PC_REGNUM 37		/* Contains program counter */
#define FP0_REGNUM 38           /* Floating point register 0 (single float) */
#define FCRCS_REGNUM 70         /* FP control/status */
#define FCRIR_REGNUM 71         /* FP implementation/revision */
#define FP_REGNUM 72		/* Pseudo register that contains true address of executing stack frame */
#define	FIRST_EMBED_REGNUM 73	/* First supervisor register for embedded use */
#define	LAST_EMBED_REGNUM 79	/* Last one */

/* Define DO_REGISTERS_INFO() to do machine-specific formatting
   of register dumps. */

#define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)

/* Total amount of space needed to store our copies of the machine's
   register state, the array `registers'.  */
#define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)

/* Index within `registers' of the first byte of the space for
   register N.  */

#define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)

/* Number of bytes of storage in the actual machine representation
   for register N.  On mips, all regs are the same size.  */

#define REGISTER_RAW_SIZE(N) MIPS_REGSIZE

/* Number of bytes of storage in the program's representation
   for register N.  On mips, all regs are the same size.  */

#define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE

/* Largest value REGISTER_RAW_SIZE can have.  */

#define MAX_REGISTER_RAW_SIZE 8

/* Largest value REGISTER_VIRTUAL_SIZE can have.  */

#define MAX_REGISTER_VIRTUAL_SIZE 8

/* Return the GDB type object for the "standard" data type
   of data in register N.  */

#ifndef REGISTER_VIRTUAL_TYPE
#define REGISTER_VIRTUAL_TYPE(N) \
	(((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32)  \
	 ? builtin_type_float : builtin_type_int)
#endif

#if HOST_BYTE_ORDER == BIG_ENDIAN
/* All mips targets store doubles in a register pair with the least
   significant register in the lower numbered register.
   If the host is big endian, double register values need conversion between
   memory and register formats.  */

#define REGISTER_CONVERT_TO_TYPE(n, type, buffer)			\
  do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && 		\
	  TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
        char __temp[4];							\
	memcpy (__temp, ((char *)(buffer))+4, 4);			\
	memcpy (((char *)(buffer))+4, (buffer), 4); 			\
	memcpy (((char *)(buffer)), __temp, 4); }} while (0)

#define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)			\
  do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 &&			\
	  TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
        char __temp[4];							\
	memcpy (__temp, ((char *)(buffer))+4, 4);			\
	memcpy (((char *)(buffer))+4, (buffer), 4); 			\
	memcpy (((char *)(buffer)), __temp, 4); }} while (0)
#endif

/* Store the address of the place in which to copy the structure the
   subroutine will return.  Handled by mips_push_arguments.  */

#define STORE_STRUCT_RETURN(addr, sp)	/**/

/* Extract from an array REGBUF containing the (raw) register state
   a function return value of type TYPE, and copy that, in virtual format,
   into VALBUF.  XXX floats */

#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
  mips_extract_return_value(TYPE, REGBUF, VALBUF)

/* Write into appropriate registers a function return value
   of type TYPE, given in virtual format.  */

#define STORE_RETURN_VALUE(TYPE,VALBUF) \
  mips_store_return_value(TYPE, VALBUF)

/* Extract from an array REGBUF containing the (raw) register state
   the address in which a function should return its structure value,
   as a CORE_ADDR (or an expression that can be used as one).  */
/* The address is passed in a0 upon entry to the function, but when
   the function exits, the compiler has copied the value to v0.  This
   convention is specified by the System V ABI, so I think we can rely
   on it.  */

#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
  (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
		    REGISTER_RAW_SIZE (V0_REGNUM)))

/* Structures are returned by ref in extra arg0 */
#define USE_STRUCT_CONVENTION(gcc_p, type)	1

\f
/* Describe the pointer in each stack frame to the previous stack frame
   (its caller).  */

/* FRAME_CHAIN takes a frame's nominal address
   and produces the frame's chain-pointer. */

#define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)

/* Define other aspects of the stack frame.  */


/* A macro that tells us whether the function invocation represented
   by FI does not have a frame on the stack associated with it.  If it
   does not, FRAMELESS is set to 1, else 0.  */
/* We handle this differently for mips, and maybe we should not */

#define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS)  {(FRAMELESS) = 0;}

/* Saved Pc.  */

#define FRAME_SAVED_PC(FRAME)	(mips_frame_saved_pc(FRAME))

#define FRAME_ARGS_ADDRESS(fi)	(fi)->frame

#define FRAME_LOCALS_ADDRESS(fi) (fi)->frame

/* Return number of args passed to a frame.
   Can return -1, meaning no way to tell.  */

#define FRAME_NUM_ARGS(num, fi)	(num = mips_frame_num_args(fi))

/* Return number of bytes at start of arglist that are not really args.  */

#define FRAME_ARGS_SKIP 0

/* Put here the code to store, into a struct frame_saved_regs,
   the addresses of the saved registers of frame described by FRAME_INFO.
   This includes special registers such as pc and fp saved in special
   ways in the stack frame.  sp is even more special:
   the address we return for it IS the sp for the next frame.  */

#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
  do { \
    if ((frame_info)->saved_regs == NULL) \
      mips_find_saved_regs (frame_info); \
    (frame_saved_regs) = *(frame_info)->saved_regs; \
    (frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \
  } while (0)

\f
/* Things needed for making the inferior call functions.  */

/* Stack has strict alignment. However, use PUSH_ARGUMENTS
   to take care of it. */
/*#define STACK_ALIGN(addr)	(((addr)+3)&~3)*/

#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
    sp = mips_push_arguments(nargs, args, sp, struct_return, struct_addr)

/* Push an empty stack frame, to record the current PC, etc.  */

#define PUSH_DUMMY_FRAME 	mips_push_dummy_frame()

/* Discard from the stack the innermost frame, restoring all registers.  */

#define POP_FRAME		mips_pop_frame()

#define MK_OP(op,rs,rt,offset) (((op)<<26)|((rs)<<21)|((rt)<<16)|(offset))
#ifndef OP_LDFPR
#define OP_LDFPR 061	/* lwc1 */
#endif
#ifndef OP_LDGPR
#define OP_LDGPR 043	/* lw */
#endif
#define CALL_DUMMY_SIZE (16*4)
#define Dest_Reg 2
#define CALL_DUMMY {\
 MK_OP(0,RA_REGNUM,0,8),	/* jr $ra # Fake ABOUT_TO_RETURN ...*/\
 0,				/* nop 	  #  ... to stop raw backtrace*/\
 0x27bd0000,			/* addu	sp,?0 # Pseudo prologue */\
/* Start here; reload FP regs, then GP regs: */\
 MK_OP(OP_LDFPR,SP_REGNUM,12,0             ), /* l[wd]c1 $f12,0(sp) */\
 MK_OP(OP_LDFPR,SP_REGNUM,13,  MIPS_REGSIZE), /* l[wd]c1 $f13,{4,8}(sp) */\
 MK_OP(OP_LDFPR,SP_REGNUM,14,2*MIPS_REGSIZE), /* l[wd]c1 $f14,{8,16}(sp) */\
 MK_OP(OP_LDFPR,SP_REGNUM,15,3*MIPS_REGSIZE), /* l[wd]c1 $f15,{12,24}(sp) */\
 MK_OP(OP_LDGPR,SP_REGNUM, 4,0             ), /* l[wd] $r4,0(sp) */\
 MK_OP(OP_LDGPR,SP_REGNUM, 5,  MIPS_REGSIZE), /* l[wd] $r5,{4,8}(sp) */\
 MK_OP(OP_LDGPR,SP_REGNUM, 6,2*MIPS_REGSIZE), /* l[wd] $r6,{8,16}(sp) */\
 MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
 (017<<26)| (Dest_Reg << 16),	/* lui $r31,<target upper 16 bits>*/\
 MK_OP(13,Dest_Reg,Dest_Reg,0),	/* ori $r31,$r31,<lower 16 bits>*/ \
 (Dest_Reg<<21) | (31<<11) | 9,	/* jalr $r31 */\
 MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
 0x5000d,			/* bpt */\
}

#define CALL_DUMMY_START_OFFSET 12

#define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + (12 * 4))

/* Insert the specified number of args and function address
   into a call sequence of the above form stored at DUMMYNAME.  */

/* For big endian mips machines we need to switch the order of the
   words with a floating-point value (it was already coerced to a double
   by mips_push_arguments).  */
#define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
  do									\
    {									\
      store_unsigned_integer						\
	(dummyname + 11 * 4, 4,						\
	 (extract_unsigned_integer (dummyname + 11 * 4, 4)		\
	  | (((fun) >> 16) & 0xffff)));					\
      store_unsigned_integer						\
	(dummyname + 12 * 4, 4,						\
	 (extract_unsigned_integer (dummyname + 12 * 4, 4)		\
	  | ((fun) & 0xffff)));						\
      if (! mips_fpu)							\
	{								\
	  store_unsigned_integer (dummyname + 3 * 4, 4,			\
				  (unsigned LONGEST) 0);		\
	  store_unsigned_integer (dummyname + 4 * 4, 4,			\
				  (unsigned LONGEST) 0);		\
	  store_unsigned_integer (dummyname + 5 * 4, 4,			\
				  (unsigned LONGEST) 0);		\
	  store_unsigned_integer (dummyname + 6 * 4, 4,			\
				  (unsigned LONGEST) 0);		\
	}								\
      else if (TARGET_BYTE_ORDER == BIG_ENDIAN				\
	       && ! GDB_TARGET_IS_MIPS64)				\
	{								\
	  if (nargs > 0							\
	      && TYPE_CODE (VALUE_TYPE (args[0])) == TYPE_CODE_FLT)	\
	    {								\
	      if (TYPE_LENGTH (VALUE_TYPE (args[0])) > 8)		\
		error ("floating point value too large to pass to function");\
	      store_unsigned_integer					\
		(dummyname + 3 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 12, 4));\
	      store_unsigned_integer					\
		(dummyname + 4 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 13, 0));\
	    }								\
	  if (nargs > 1							\
	      && TYPE_CODE (VALUE_TYPE (args[1])) == TYPE_CODE_FLT)	\
	    {								\
	      if (TYPE_LENGTH (VALUE_TYPE (args[1])) > 8)		\
		error ("floating point value too large to pass to function");\
	      store_unsigned_integer					\
		(dummyname + 5 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 14, 12));\
	      store_unsigned_integer					\
		(dummyname + 6 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 15, 8));\
	    }								\
	}								\
    }									\
  while (0)

/* There's a mess in stack frame creation.  See comments in blockframe.c
   near reference to INIT_FRAME_PC_FIRST.  */

#define	INIT_FRAME_PC(fromleaf, prev) /* nada */

#define INIT_FRAME_PC_FIRST(fromleaf, prev) \
  (prev)->pc = ((fromleaf) ? SAVED_PC_AFTER_CALL ((prev)->next) : \
	      (prev)->next ? FRAME_SAVED_PC ((prev)->next) : read_pc ());

/* Special symbol found in blocks associated with routines.  We can hang
   mips_extra_func_info_t's off of this.  */

#define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"

/* Specific information about a procedure.
   This overlays the MIPS's PDR records, 
   mipsread.c (ab)uses this to save memory */

typedef struct mips_extra_func_info {
	long	numargs;	/* number of args to procedure (was iopt) */
	PDR	pdr;		/* Procedure descriptor record */
} *mips_extra_func_info_t;

#define EXTRA_FRAME_INFO \
  mips_extra_func_info_t proc_desc; \
  int num_args;\
  struct frame_saved_regs *saved_regs;

#define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)

#define	PRINT_EXTRA_FRAME_INFO(fi) \
  { \
    if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
      printf_filtered (" frame pointer is at %s+%d\n", \
                       reg_names[fi->proc_desc->pdr.framereg], \
                                 fi->proc_desc->pdr.frameoffset); \
  }

/* It takes two values to specify a frame on the MIPS.

   In fact, the *PC* is the primary value that sets up a frame.  The
   PC is looked up to see what function it's in; symbol information
   from that function tells us which register is the frame pointer
   base, and what offset from there is the "virtual frame pointer".
   (This is usually an offset from SP.)  On most non-MIPS machines,
   the primary value is the SP, and the PC, if needed, disambiguates
   multiple functions with the same SP.  But on the MIPS we can't do
   that since the PC is not stored in the same part of the frame every
   time.  This does not seem to be a very clever way to set up frames,
   but there is nothing we can do about that).  */

#define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));

/* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */

#define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)

/* Convert a ecoff register number to a gdb REGNUM */

#define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
Commit	Line	Data
5076de82 FF	1	/* Definitions to make GDB run on a mips box under 4.3bsd.
	2	Copyright 1986, 1987, 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
	3	Contributed by Per Bothner ([email protected]) at U.Wisconsin
	4	and by Alessandro Forin ([email protected]) at CMU..
	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
	21
05e9e188	22	#include <bfd.h>
5076de82 FF	23	#include "coff/sym.h" /* Needed for PDR below. */
	24	#include "coff/symconst.h"
	25
	26	#if !defined (TARGET_BYTE_ORDER)
	27	#define TARGET_BYTE_ORDER LITTLE_ENDIAN
	28	#endif
	29
97d3151a ILT	30	#if !defined (GDB_TARGET_IS_MIPS64)
	31	#define GDB_TARGET_IS_MIPS64 0
	32	#endif
	33
5076de82 FF	34	/* Floating point is IEEE compliant */
	35	#define IEEE_FLOAT
	36
669caa9c SS	37	extern int mips_processor_id;
669caa9c SS	38
5076de82 FF	39	/* Some MIPS boards are provided both with and without a floating
	40	point coprocessor; we provide a user settable variable to tell gdb
	41	whether there is one or not. */
	42	extern int mips_fpu;
	43
	44	/* Offset from address of function to start of its code.
	45	Zero on most machines. */
	46
	47	#define FUNCTION_START_OFFSET 0
	48
	49	/* Advance PC across any function entry prologue instructions
	50	to reach some "real" code. */
	51
ee5fb959 JK	52	#define SKIP_PROLOGUE(pc) pc = mips_skip_prologue (pc, 0)
ee5fb959 JK	53	extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
5076de82	54
b5aff268 JK	55	/* Return non-zero if PC points to an instruction which will cause a step
	56	to execute both the instruction at PC and an instruction at PC+4. */
	57	#define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
	58
5076de82 FF	59	/* Immediately after a function call, return the saved pc.
	60	Can't always go through the frames for this because on some machines
	61	the new frame is not set up until the new function executes
	62	some instructions. */
	63
	64	#define SAVED_PC_AFTER_CALL(frame) read_register(RA_REGNUM)
	65
	66	/* Are we currently handling a signal */
	67
e03c0cc6	68	extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
5076de82 FF	69	#define IN_SIGTRAMP(pc, name) in_sigtramp(pc, name)
5076de82 FF	70
5076de82 FF	71	/* Stack grows downward. */
	72
	73	#define INNER_THAN <
	74
	75	#define BIG_ENDIAN 4321
	76	#if TARGET_BYTE_ORDER == BIG_ENDIAN
	77	#define BREAKPOINT {0, 0x5, 0, 0xd}
	78	#else
	79	#define BREAKPOINT {0xd, 0, 0x5, 0}
	80	#endif
	81
	82	/* Amount PC must be decremented by after a breakpoint.
	83	This is often the number of bytes in BREAKPOINT
	84	but not always. */
	85
	86	#define DECR_PC_AFTER_BREAK 0
	87
	88	/* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */
	89
	90	#define ABOUT_TO_RETURN(pc) (read_memory_integer (pc, 4) == 0x3e00008)
	91
f4f0d174 JK	92	/* Say how long (ordinary) registers are. This is a piece of bogosity
	93	used in push_word and a few other places; REGISTER_RAW_SIZE is the
	94	real way to know how big a register is. */
5076de82	95
f4f0d174	96	#define REGISTER_SIZE 4
5076de82	97
4fbce2fd KH	98	/* The size of a register. This is predefined in tm-mips64.h. We
	99	can't use REGISTER_SIZE because that is used for various other
	100	things. */
	101
	102	#ifndef MIPS_REGSIZE
	103	#define MIPS_REGSIZE 4
	104	#endif
	105
5076de82 FF	106	/* Number of machine registers */
	107
	108	#define NUM_REGS 80
	109
	110	/* Initializer for an array of names of registers.
	111	There should be NUM_REGS strings in this initializer. */
	112
	113	#define REGISTER_NAMES \
	114	{ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
	115	"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
	116	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
	117	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
	118	"sr", "lo", "hi", "bad", "cause","pc", \
	119	"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
	120	"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
	121	"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
	122	"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
	123	"fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
	124	"epc", "prid"\
	125	}
	126
	127	/* Register numbers of various important registers.
	128	Note that some of these values are "real" register numbers,
	129	and correspond to the general registers of the machine,
	130	and some are "phony" register numbers which are too large
	131	to be actual register numbers as far as the user is concerned
	132	but do serve to get the desired values when passed to read_register. */
	133
	134	#define ZERO_REGNUM 0 /* read-only register, always 0 */
138dd57c	135	#define V0_REGNUM 2 /* Function integer return value */
5076de82 FF	136	#define A0_REGNUM 4 /* Loc of first arg during a subr call */
	137	#define SP_REGNUM 29 /* Contains address of top of stack */
	138	#define RA_REGNUM 31 /* Contains return address value */
	139	#define PS_REGNUM 32 /* Contains processor status */
	140	#define HI_REGNUM 34 /* Multiple/divide temp */
	141	#define LO_REGNUM 33 /* ... */
	142	#define BADVADDR_REGNUM 35 /* bad vaddr for addressing exception */
	143	#define CAUSE_REGNUM 36 /* describes last exception */
	144	#define PC_REGNUM 37 /* Contains program counter */
	145	#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
	146	#define FCRCS_REGNUM 70 /* FP control/status */
	147	#define FCRIR_REGNUM 71 /* FP implementation/revision */
	148	#define FP_REGNUM 72 /* Pseudo register that contains true address of executing stack frame */
	149	#define FIRST_EMBED_REGNUM 73 /* First supervisor register for embedded use */
	150	#define LAST_EMBED_REGNUM 79 /* Last one */
	151
	152	/* Define DO_REGISTERS_INFO() to do machine-specific formatting
	153	of register dumps. */
	154
	155	#define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
	156
	157	/* Total amount of space needed to store our copies of the machine's
	158	register state, the array `registers'. */
4fbce2fd	159	#define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
5076de82 FF	160
	161	/* Index within `registers' of the first byte of the space for
	162	register N. */
	163
4fbce2fd	164	#define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
5076de82 FF	165
5076de82 FF	166	/* Number of bytes of storage in the actual machine representation
4fbce2fd	167	for register N. On mips, all regs are the same size. */
5076de82	168
4fbce2fd	169	#define REGISTER_RAW_SIZE(N) MIPS_REGSIZE
5076de82 FF	170
5076de82 FF	171	/* Number of bytes of storage in the program's representation
4fbce2fd	172	for register N. On mips, all regs are the same size. */
5076de82	173
4fbce2fd	174	#define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE
5076de82 FF	175
	176	/* Largest value REGISTER_RAW_SIZE can have. */
	177
ac8cf67d	178	#define MAX_REGISTER_RAW_SIZE 8
5076de82 FF	179
	180	/* Largest value REGISTER_VIRTUAL_SIZE can have. */
	181
ac8cf67d	182	#define MAX_REGISTER_VIRTUAL_SIZE 8
5076de82	183
5076de82 FF	184	/* Return the GDB type object for the "standard" data type
	185	of data in register N. */
	186
031b390a	187	#ifndef REGISTER_VIRTUAL_TYPE
5076de82 FF	188	#define REGISTER_VIRTUAL_TYPE(N) \
5076de82 FF	189	(((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) \
031b390a KH	190	? builtin_type_float : builtin_type_int)
031b390a KH	191	#endif
5076de82	192
ac8cf67d PS	193	#if HOST_BYTE_ORDER == BIG_ENDIAN
	194	/* All mips targets store doubles in a register pair with the least
	195	significant register in the lower numbered register.
	196	If the host is big endian, double register values need conversion between
	197	memory and register formats. */
	198
	199	#define REGISTER_CONVERT_TO_TYPE(n, type, buffer) \
	200	do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \
	201	TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
	202	char __temp[4]; \
	203	memcpy (__temp, ((char *)(buffer))+4, 4); \
	204	memcpy (((char *)(buffer))+4, (buffer), 4); \
	205	memcpy (((char *)(buffer)), __temp, 4); }} while (0)
	206
	207	#define REGISTER_CONVERT_FROM_TYPE(n, type, buffer) \
	208	do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \
	209	TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
	210	char __temp[4]; \
	211	memcpy (__temp, ((char *)(buffer))+4, 4); \
	212	memcpy (((char *)(buffer))+4, (buffer), 4); \
	213	memcpy (((char *)(buffer)), __temp, 4); }} while (0)
	214	#endif
	215
5076de82	216	/* Store the address of the place in which to copy the structure the
0c28fe8d	217	subroutine will return. Handled by mips_push_arguments. */
5076de82	218
0c28fe8d	219	#define STORE_STRUCT_RETURN(addr, sp) /**/
5076de82 FF	220
	221	/* Extract from an array REGBUF containing the (raw) register state
	222	a function return value of type TYPE, and copy that, in virtual format,
	223	into VALBUF. XXX floats */
	224
	225	#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
ac8cf67d	226	mips_extract_return_value(TYPE, REGBUF, VALBUF)
5076de82 FF	227
	228	/* Write into appropriate registers a function return value
	229	of type TYPE, given in virtual format. */
	230
	231	#define STORE_RETURN_VALUE(TYPE,VALBUF) \
ac8cf67d	232	mips_store_return_value(TYPE, VALBUF)
5076de82 FF	233
	234	/* Extract from an array REGBUF containing the (raw) register state
	235	the address in which a function should return its structure value,
	236	as a CORE_ADDR (or an expression that can be used as one). */
138dd57c JK	237	/* The address is passed in a0 upon entry to the function, but when
138dd57c JK	238	the function exits, the compiler has copied the value to v0. This
e8239c2f JK	239	convention is specified by the System V ABI, so I think we can rely
e8239c2f JK	240	on it. */
5076de82	241
138dd57c JK	242	#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
	243	(extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
	244	REGISTER_RAW_SIZE (V0_REGNUM)))
5076de82 FF	245
	246	/* Structures are returned by ref in extra arg0 */
	247	#define USE_STRUCT_CONVENTION(gcc_p, type) 1
	248
	249	\f
	250	/* Describe the pointer in each stack frame to the previous stack frame
	251	(its caller). */
	252
	253	/* FRAME_CHAIN takes a frame's nominal address
	254	and produces the frame's chain-pointer. */
	255
669caa9c	256	#define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
5076de82 FF	257
	258	/* Define other aspects of the stack frame. */
	259
	260
	261	/* A macro that tells us whether the function invocation represented
	262	by FI does not have a frame on the stack associated with it. If it
	263	does not, FRAMELESS is set to 1, else 0. */
	264	/* We handle this differently for mips, and maybe we should not */
	265
	266	#define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS) {(FRAMELESS) = 0;}
	267
	268	/* Saved Pc. */
	269
	270	#define FRAME_SAVED_PC(FRAME) (mips_frame_saved_pc(FRAME))
	271
	272	#define FRAME_ARGS_ADDRESS(fi) (fi)->frame
	273
	274	#define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
	275
	276	/* Return number of args passed to a frame.
	277	Can return -1, meaning no way to tell. */
	278
	279	#define FRAME_NUM_ARGS(num, fi) (num = mips_frame_num_args(fi))
	280
	281	/* Return number of bytes at start of arglist that are not really args. */
	282
	283	#define FRAME_ARGS_SKIP 0
	284
	285	/* Put here the code to store, into a struct frame_saved_regs,
	286	the addresses of the saved registers of frame described by FRAME_INFO.
	287	This includes special registers such as pc and fp saved in special
	288	ways in the stack frame. sp is even more special:
	289	the address we return for it IS the sp for the next frame. */
	290
14d79562 JK	291	#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
	292	do { \
	293	if ((frame_info)->saved_regs == NULL) \
	294	mips_find_saved_regs (frame_info); \
	295	(frame_saved_regs) = *(frame_info)->saved_regs; \
	296	(frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \
	297	} while (0)
5076de82 FF	298
	299	\f
	300	/* Things needed for making the inferior call functions. */
	301
	302	/* Stack has strict alignment. However, use PUSH_ARGUMENTS
	303	to take care of it. */
	304	/#define STACK_ALIGN(addr) (((addr)+3)&~3)/
	305
	306	#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
	307	sp = mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
	308
	309	/* Push an empty stack frame, to record the current PC, etc. */
	310
	311	#define PUSH_DUMMY_FRAME mips_push_dummy_frame()
	312
	313	/* Discard from the stack the innermost frame, restoring all registers. */
	314
	315	#define POP_FRAME mips_pop_frame()
	316
	317	#define MK_OP(op,rs,rt,offset) (((op)<<26)\|((rs)<<21)\|((rt)<<16)\|(offset))
4fbce2fd KH	318	#ifndef OP_LDFPR
	319	#define OP_LDFPR 061 /* lwc1 */
	320	#endif
	321	#ifndef OP_LDGPR
	322	#define OP_LDGPR 043 /* lw */
	323	#endif
5076de82 FF	324	#define CALL_DUMMY_SIZE (16*4)
	325	#define Dest_Reg 2
	326	#define CALL_DUMMY {\
	327	MK_OP(0,RA_REGNUM,0,8), /* jr $ra # Fake ABOUT_TO_RETURN ...*/\
	328	0, /* nop # ... to stop raw backtrace*/\
	329	0x27bd0000, /* addu sp,?0 # Pseudo prologue */\
4fbce2fd KH	330	/* Start here; reload FP regs, then GP regs: */\
	331	MK_OP(OP_LDFPR,SP_REGNUM,12,0 ), /* l[wd]c1 $f12,0(sp) */\
	332	MK_OP(OP_LDFPR,SP_REGNUM,13, MIPS_REGSIZE), /* l[wd]c1 $f13,{4,8}(sp) */\
	333	MK_OP(OP_LDFPR,SP_REGNUM,14,2MIPS_REGSIZE), / l[wd]c1 $f14,{8,16}(sp) */\
	334	MK_OP(OP_LDFPR,SP_REGNUM,15,3MIPS_REGSIZE), / l[wd]c1 $f15,{12,24}(sp) */\
	335	MK_OP(OP_LDGPR,SP_REGNUM, 4,0 ), /* l[wd] $r4,0(sp) */\
	336	MK_OP(OP_LDGPR,SP_REGNUM, 5, MIPS_REGSIZE), /* l[wd] $r5,{4,8}(sp) */\
	337	MK_OP(OP_LDGPR,SP_REGNUM, 6,2MIPS_REGSIZE), / l[wd] $r6,{8,16}(sp) */\
	338	MK_OP(OP_LDGPR,SP_REGNUM, 7,3MIPS_REGSIZE), / l[wd] $r7,{12,24}(sp) */\
5076de82 FF	339	(017<<26)\| (Dest_Reg << 16), /* lui $r31,<target upper 16 bits>*/\
	340	MK_OP(13,Dest_Reg,Dest_Reg,0), /* ori $r31,$r31,<lower 16 bits>*/ \
	341	(Dest_Reg<<21) \| (31<<11) \| 9, /* jalr $r31 */\
4fbce2fd	342	MK_OP(OP_LDGPR,SP_REGNUM, 7,3MIPS_REGSIZE), / l[wd] $r7,{12,24}(sp) */\
5076de82 FF	343	0x5000d, /* bpt */\
	344	}
	345
	346	#define CALL_DUMMY_START_OFFSET 12
	347
f0d2557c PS	348	#define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + (12 * 4))
f0d2557c PS	349
5076de82 FF	350	/* Insert the specified number of args and function address
	351	into a call sequence of the above form stored at DUMMYNAME. */
	352
08447510 PS	353	/* For big endian mips machines we need to switch the order of the
	354	words with a floating-point value (it was already coerced to a double
	355	by mips_push_arguments). */
ac8cf67d	356	#define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
97d3151a ILT	357	do \
	358	{ \
	359	store_unsigned_integer \
	360	(dummyname + 11 * 4, 4, \
	361	(extract_unsigned_integer (dummyname + 11 * 4, 4) \
	362	\| (((fun) >> 16) & 0xffff))); \
	363	store_unsigned_integer \
	364	(dummyname + 12 * 4, 4, \
	365	(extract_unsigned_integer (dummyname + 12 * 4, 4) \
	366	\| ((fun) & 0xffff))); \
	367	if (! mips_fpu) \
	368	{ \
	369	store_unsigned_integer (dummyname + 3 * 4, 4, \
	370	(unsigned LONGEST) 0); \
	371	store_unsigned_integer (dummyname + 4 * 4, 4, \
	372	(unsigned LONGEST) 0); \
	373	store_unsigned_integer (dummyname + 5 * 4, 4, \
	374	(unsigned LONGEST) 0); \
	375	store_unsigned_integer (dummyname + 6 * 4, 4, \
	376	(unsigned LONGEST) 0); \
	377	} \
	378	else if (TARGET_BYTE_ORDER == BIG_ENDIAN \
	379	&& ! GDB_TARGET_IS_MIPS64) \
	380	{ \
	381	if (nargs > 0 \
	382	&& TYPE_CODE (VALUE_TYPE (args[0])) == TYPE_CODE_FLT) \
	383	{ \
	384	if (TYPE_LENGTH (VALUE_TYPE (args[0])) > 8) \
	385	error ("floating point value too large to pass to function");\
	386	store_unsigned_integer \
	387	(dummyname + 3 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 12, 4));\
	388	store_unsigned_integer \
	389	(dummyname + 4 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 13, 0));\
	390	} \
	391	if (nargs > 1 \
	392	&& TYPE_CODE (VALUE_TYPE (args[1])) == TYPE_CODE_FLT) \
	393	{ \
	394	if (TYPE_LENGTH (VALUE_TYPE (args[1])) > 8) \
	395	error ("floating point value too large to pass to function");\
	396	store_unsigned_integer \
	397	(dummyname + 5 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 14, 12));\
	398	store_unsigned_integer \
	399	(dummyname + 6 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 15, 8));\
	400	} \
	401	} \
ac8cf67d	402	} \
5076de82 FF	403	while (0)
	404
	405	/* There's a mess in stack frame creation. See comments in blockframe.c
	406	near reference to INIT_FRAME_PC_FIRST. */
	407
	408	#define INIT_FRAME_PC(fromleaf, prev) /* nada */
	409
	410	#define INIT_FRAME_PC_FIRST(fromleaf, prev) \
	411	(prev)->pc = ((fromleaf) ? SAVED_PC_AFTER_CALL ((prev)->next) : \
	412	(prev)->next ? FRAME_SAVED_PC ((prev)->next) : read_pc ());
	413
	414	/* Special symbol found in blocks associated with routines. We can hang
	415	mips_extra_func_info_t's off of this. */
	416
	417	#define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
	418
	419	/* Specific information about a procedure.
	420	This overlays the MIPS's PDR records,
	421	mipsread.c (ab)uses this to save memory */
	422
	423	typedef struct mips_extra_func_info {
	424	long numargs; /* number of args to procedure (was iopt) */
	425	PDR pdr; /* Procedure descriptor record */
	426	} *mips_extra_func_info_t;
	427
	428	#define EXTRA_FRAME_INFO \
	429	mips_extra_func_info_t proc_desc; \
	430	int num_args;\
	431	struct frame_saved_regs *saved_regs;
	432
	433	#define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)
	434
	435	#define PRINT_EXTRA_FRAME_INFO(fi) \
	436	{ \
	437	if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
	438	printf_filtered (" frame pointer is at %s+%d\n", \
	439	reg_names[fi->proc_desc->pdr.framereg], \
	440	fi->proc_desc->pdr.frameoffset); \
	441	}
	442
4df6dcd1 JK	443	/* It takes two values to specify a frame on the MIPS.
	444
	445	In fact, the PC is the primary value that sets up a frame. The
	446	PC is looked up to see what function it's in; symbol information
	447	from that function tells us which register is the frame pointer
	448	base, and what offset from there is the "virtual frame pointer".
	449	(This is usually an offset from SP.) On most non-MIPS machines,
	450	the primary value is the SP, and the PC, if needed, disambiguates
	451	multiple functions with the same SP. But on the MIPS we can't do
	452	that since the PC is not stored in the same part of the frame every
	453	time. This does not seem to be a very clever way to set up frames,
	454	but there is nothing we can do about that). */
5076de82 FF	455
5076de82 FF	456	#define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
5076de82 FF	457	extern struct frame_info setup_arbitrary_frame PARAMS ((int, CORE_ADDR ));
5076de82 FF	458
01422144 PS	459	/* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
	460
	461	#define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
8b15c480 PS	462
	463	/* Convert a ecoff register number to a gdb REGNUM */
	464
	465	#define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)